Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1671023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262436

1

T1

44

T2

321

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	655861	1			T1	212		T2	694		T3	37
values[0x0]	624620	1			T1	31		T2	754		T3	36
values[0x1]	652978	1			T1	240		T2	769		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1294473	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

638986

1

T1

190

T2

736

T3

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7900	1			T2	14		T16	5		T10	82
valid_sources[0x01]	7556	1			T2	3		T13	5		T15	1
valid_sources[0x02]	7277	1			T2	11		T16	8		T10	69
valid_sources[0x03]	8279	1			T1	2		T2	9		T13	20
valid_sources[0x04]	8010	1			T2	4		T15	1		T16	6
valid_sources[0x05]	7408	1			T1	1		T2	7		T13	16
valid_sources[0x06]	7927	1			T1	3		T2	5		T16	2
valid_sources[0x07]	7302	1			T1	1		T2	6		T16	8
valid_sources[0x08]	7176	1			T1	2		T2	15		T15	2
valid_sources[0x09]	7565	1			T1	3		T2	8		T13	9
valid_sources[0x0a]	7307	1			T1	1		T2	7		T13	8
valid_sources[0x0b]	7276	1			T1	1		T2	9		T16	7
valid_sources[0x0c]	7778	1			T1	1		T2	10		T16	9
valid_sources[0x0d]	6867	1			T1	1		T2	7		T3	6
valid_sources[0x0e]	8373	1			T2	9		T15	3		T16	7
valid_sources[0x0f]	7114	1			T2	10		T3	2		T16	9
valid_sources[0x10]	6948	1			T1	3		T2	6		T16	1
valid_sources[0x11]	7288	1			T1	1		T2	7		T15	1
valid_sources[0x12]	7540	1			T1	9		T2	12		T15	1
valid_sources[0x13]	7700	1			T1	6		T2	8		T16	13
valid_sources[0x14]	7354	1			T1	3		T2	10		T16	3
valid_sources[0x15]	7520	1			T1	1		T2	9		T16	4
valid_sources[0x16]	7145	1			T2	4		T15	1		T16	4
valid_sources[0x17]	7549	1			T1	4		T2	17		T15	1
valid_sources[0x18]	7052	1			T1	4		T2	10		T3	1
valid_sources[0x19]	6894	1			T1	2		T2	6		T3	3
valid_sources[0x1a]	7288	1			T1	5		T2	10		T15	1
valid_sources[0x1b]	7960	1			T1	1		T2	11		T3	1
valid_sources[0x1c]	7724	1			T1	3		T2	3		T13	6
valid_sources[0x1d]	8129	1			T1	3		T2	9		T3	3
valid_sources[0x1e]	7821	1			T1	3		T2	5		T16	4
valid_sources[0x1f]	7099	1			T2	7		T15	2		T16	2
valid_sources[0x20]	8192	1			T1	1		T2	6		T3	1
valid_sources[0x21]	7200	1			T2	11		T16	4		T10	151
valid_sources[0x22]	7713	1			T2	6		T3	1		T16	10
valid_sources[0x23]	7340	1			T1	4		T2	7		T15	1
valid_sources[0x24]	8463	1			T2	10		T16	4		T10	107
valid_sources[0x25]	8207	1			T1	3		T2	7		T3	1
valid_sources[0x26]	7108	1			T1	3		T2	10		T16	6
valid_sources[0x27]	7608	1			T1	2		T2	6		T13	10
valid_sources[0x28]	7593	1			T2	5		T15	1		T16	8
valid_sources[0x29]	7435	1			T1	3		T2	9		T16	3
valid_sources[0x2a]	8491	1			T1	3		T2	6		T15	2
valid_sources[0x2b]	8785	1			T2	16		T3	1		T15	1
valid_sources[0x2c]	7434	1			T1	3		T2	5		T10	86
valid_sources[0x2d]	7431	1			T1	3		T2	3		T3	10
valid_sources[0x2e]	7474	1			T1	2		T2	4		T13	13
valid_sources[0x2f]	8149	1			T1	3		T2	7		T15	1
valid_sources[0x30]	8021	1			T1	4		T2	6		T15	2
valid_sources[0x31]	7066	1			T2	6		T16	5		T10	75
valid_sources[0x32]	7767	1			T2	11		T15	1		T16	3
valid_sources[0x33]	7116	1			T1	1		T2	7		T3	6
valid_sources[0x34]	7435	1			T1	3		T2	9		T16	7
valid_sources[0x35]	7622	1			T1	3		T2	9		T3	1
valid_sources[0x36]	7257	1			T1	5		T2	9		T15	1
valid_sources[0x37]	8248	1			T2	3		T13	19		T16	12
valid_sources[0x38]	7427	1			T1	3		T2	4		T16	11
valid_sources[0x39]	7338	1			T1	2		T2	10		T13	20
valid_sources[0x3a]	7024	1			T1	1		T2	15		T16	4
valid_sources[0x3b]	7664	1			T2	8		T13	6		T16	6
valid_sources[0x3c]	8452	1			T1	1		T2	14		T16	7
valid_sources[0x3d]	7432	1			T1	1		T2	5		T16	3
valid_sources[0x3e]	7461	1			T2	7		T16	13		T10	50
valid_sources[0x3f]	7053	1			T1	4		T2	11		T15	2
valid_sources[0x40]	7021	1			T1	4		T2	10		T3	2
valid_sources[0x41]	7432	1			T1	4		T2	5		T16	7
valid_sources[0x42]	8565	1			T1	2		T2	7		T16	4
valid_sources[0x43]	7255	1			T1	3		T2	7		T3	1
valid_sources[0x44]	7579	1			T1	1		T2	9		T3	10
valid_sources[0x45]	7576	1			T1	1		T2	13		T16	8
valid_sources[0x46]	7088	1			T2	8		T15	1		T16	7
valid_sources[0x47]	6999	1			T1	2		T2	7		T13	18
valid_sources[0x48]	7489	1			T1	2		T2	4		T16	8
valid_sources[0x49]	7967	1			T1	4		T2	11		T16	12
valid_sources[0x4a]	8596	1			T1	1		T2	10		T16	3
valid_sources[0x4b]	7522	1			T1	1		T2	9		T15	3
valid_sources[0x4c]	7573	1			T1	3		T2	10		T15	1
valid_sources[0x4d]	8022	1			T2	9		T16	9		T10	74
valid_sources[0x4e]	7351	1			T2	5		T15	1		T16	7
valid_sources[0x4f]	7193	1			T1	2		T2	9		T13	7
valid_sources[0x50]	7308	1			T1	1		T2	9		T16	9
valid_sources[0x51]	6945	1			T2	9		T16	2		T10	161
valid_sources[0x52]	8644	1			T1	2		T2	13		T16	2
valid_sources[0x53]	7635	1			T1	4		T2	4		T16	4
valid_sources[0x54]	7726	1			T1	4		T2	6		T15	1
valid_sources[0x55]	7614	1			T1	3		T2	10		T16	3
valid_sources[0x56]	7712	1			T2	12		T16	7		T10	42
valid_sources[0x57]	7484	1			T2	5		T13	8		T15	1
valid_sources[0x58]	7827	1			T1	2		T2	12		T15	1
valid_sources[0x59]	7405	1			T1	1		T2	6		T13	15
valid_sources[0x5a]	7754	1			T1	1		T2	18		T16	13
valid_sources[0x5b]	7880	1			T1	2		T2	8		T3	2
valid_sources[0x5c]	9024	1			T1	1		T2	6		T16	3
valid_sources[0x5d]	7274	1			T1	1		T2	10		T16	4
valid_sources[0x5e]	7059	1			T1	1		T2	9		T16	3
valid_sources[0x5f]	6655	1			T1	5		T2	11		T3	1
valid_sources[0x60]	8908	1			T2	5		T3	1		T16	6
valid_sources[0x61]	7561	1			T1	1		T2	9		T16	4
valid_sources[0x62]	8288	1			T1	6		T2	8		T3	1
valid_sources[0x63]	7272	1			T1	1		T2	3		T13	12
valid_sources[0x64]	6794	1			T1	3		T2	5		T16	6
valid_sources[0x65]	7200	1			T1	1		T2	15		T15	1
valid_sources[0x66]	7212	1			T1	1		T2	11		T13	8
valid_sources[0x67]	7874	1			T2	9		T16	4		T10	89
valid_sources[0x68]	8266	1			T2	5		T16	4		T10	143
valid_sources[0x69]	7512	1			T1	1		T2	7		T3	1
valid_sources[0x6a]	7370	1			T1	2		T2	11		T15	1
valid_sources[0x6b]	6984	1			T1	2		T2	9		T15	1
valid_sources[0x6c]	8186	1			T1	2		T2	6		T16	6
valid_sources[0x6d]	7947	1			T1	3		T2	6		T16	1
valid_sources[0x6e]	6998	1			T2	7		T13	5		T16	2
valid_sources[0x6f]	7846	1			T1	2		T2	13		T16	8
valid_sources[0x70]	8380	1			T1	1		T2	11		T15	1
valid_sources[0x71]	7573	1			T1	1		T2	11		T16	11
valid_sources[0x72]	7219	1			T1	3		T2	18		T15	1
valid_sources[0x73]	6695	1			T2	8		T15	2		T16	3
valid_sources[0x74]	7672	1			T1	3		T2	5		T13	10
valid_sources[0x75]	8291	1			T1	1		T2	8		T16	6
valid_sources[0x76]	7463	1			T2	9		T16	4		T10	85
valid_sources[0x77]	7138	1			T2	8		T13	7		T15	1
valid_sources[0x78]	7504	1			T2	12		T16	4		T10	101
valid_sources[0x79]	7326	1			T1	5		T2	6		T16	7
valid_sources[0x7a]	7201	1			T1	1		T2	7		T15	1
valid_sources[0x7b]	8129	1			T1	2		T2	8		T15	1
valid_sources[0x7c]	7599	1			T1	7		T2	9		T16	6
valid_sources[0x7d]	8017	1			T1	4		T2	4		T15	1
valid_sources[0x7e]	7706	1			T2	11		T16	8		T10	171
valid_sources[0x7f]	8159	1			T1	1		T2	13		T13	6
valid_sources[0x80]	8093	1			T1	3		T2	5		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27518

1

T1

19

T2

24

T13

4

values[0x0]

all_enables

biggest_size

207178

1

T1

10

T2

263

T3

8

values[0x1]

all_enables

biggest_size

27740

1

T1

15

T2

34

T13

10