Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	336795703	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	336795703	0	0
T1	12915000	239167	0	0
T2	17860304	2396647	0	0
T3	27664	525	0	0
T10	2406376	111770	0	0
T12	3098872	135602	0	0
T13	60984	2056	0	0
T14	28224	632	0	0
T15	5312664	166041	0	0
T16	166936	6803	0	0
T17	5692960	1428518	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12915000	12888960	0	0
T2	17860304	17860136	0	0
T3	27664	25256	0	0
T10	2406376	2386888	0	0
T12	3098872	3036320	0	0
T13	60984	60480	0	0
T14	28224	26544	0	0
T15	5312664	5311432	0	0
T16	166936	165088	0	0
T17	5692960	5692848	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12915000	12888960	0	0
T2	17860304	17860136	0	0
T3	27664	25256	0	0
T10	2406376	2386888	0	0
T12	3098872	3036320	0	0
T13	60984	60480	0	0
T14	28224	26544	0	0
T15	5312664	5311432	0	0
T16	166936	165088	0	0
T17	5692960	5692848	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12915000	12888960	0	0
T2	17860304	17860136	0	0
T3	27664	25256	0	0
T10	2406376	2386888	0	0
T12	3098872	3036320	0	0
T13	60984	60480	0	0
T14	28224	26544	0	0
T15	5312664	5311432	0	0
T16	166936	165088	0	0
T17	5692960	5692848	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T10	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	126057050	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	126057050	0	0
T1	230625	102191	0	0
T2	318934	157245	0	0
T3	494	204	0	0
T10	42971	39170	0	0
T12	55337	51029	0	0
T13	1089	515	0	0
T14	504	242	0	0
T15	94869	91905	0	0
T16	2981	2654	0	0
T17	101660	578356	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	85215868	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	85215868	0	0
T1	230625	34929	0	0
T2	318934	736007	0	0
T3	494	107	0	0
T10	42971	25144	0	0
T12	55337	29994	0	0
T13	1089	515	0	0
T14	504	130	0	0
T15	94869	36825	0	0
T16	2981	1383	0	0
T17	101660	279891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1493377	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1493377	0	0
T1	230625	3439	0	0
T2	318934	35896	0	0
T3	494	1	0	0
T10	42971	940	0	0
T12	55337	958	0	0
T13	1089	20	0	0
T14	504	4	0	0
T15	94869	48	0	0
T16	2981	45	0	0
T17	101660	5796	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2877062	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2877062	0	0
T1	230625	1592	0	0
T2	318934	27347	0	0
T3	494	1	0	0
T10	42971	940	0	0
T12	55337	958	0	0
T13	1089	20	0	0
T14	504	4	0	0
T15	94869	4084	0	0
T16	2981	45	0	0
T17	101660	5601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1534737	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1534737	0	0
T1	230625	1800	0	0
T2	318934	29996	0	0
T3	494	3	0	0
T10	42971	1266	0	0
T12	55337	1708	0	0
T13	1089	22	0	0
T14	504	1	0	0
T15	94869	13	0	0
T16	2981	55	0	0
T17	101660	8435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2480017	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2480017	0	0
T1	230625	888	0	0
T2	318934	30462	0	0
T3	494	3	0	0
T10	42971	1266	0	0
T12	55337	1708	0	0
T13	1089	22	0	0
T14	504	1	0	0
T15	94869	897	0	0
T16	2981	55	0	0
T17	101660	9963	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1492694	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1492694	0	0
T1	230625	1620	0	0
T2	318934	23150	0	0
T3	494	5	0	0
T10	42971	479	0	0
T12	55337	915	0	0
T13	1089	18	0	0
T14	504	3	0	0
T15	94869	15	0	0
T16	2981	53	0	0
T17	101660	9526	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	4008671	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	4008671	0	0
T1	230625	905	0	0
T2	318934	26956	0	0
T3	494	5	0	0
T10	42971	479	0	0
T12	55337	915	0	0
T13	1089	18	0	0
T14	504	3	0	0
T15	94869	819	0	0
T16	2981	53	0	0
T17	101660	10895	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1511619	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1511619	0	0
T1	230625	1505	0	0
T2	318934	30497	0	0
T3	494	6	0	0
T10	42971	1352	0	0
T12	55337	849	0	0
T13	1089	21	0	0
T14	504	2	0	0
T15	94869	17	0	0
T16	2981	50	0	0
T17	101660	10432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3053065	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3053065	0	0
T1	230625	783	0	0
T2	318934	26940	0	0
T3	494	6	0	0
T10	42971	1352	0	0
T12	55337	849	0	0
T13	1089	21	0	0
T14	504	2	0	0
T15	94869	1360	0	0
T16	2981	50	0	0
T17	101660	11486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1545538	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1545538	0	0
T1	230625	3072	0	0
T2	318934	25493	0	0
T3	494	2	0	0
T10	42971	504	0	0
T12	55337	626	0	0
T13	1089	23	0	0
T14	504	3	0	0
T15	94869	12	0	0
T16	2981	57	0	0
T17	101660	13066	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3439632	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3439632	0	0
T1	230625	1453	0	0
T2	318934	29998	0	0
T3	494	2	0	0
T10	42971	504	0	0
T12	55337	626	0	0
T13	1089	23	0	0
T14	504	3	0	0
T15	94869	1716	0	0
T16	2981	57	0	0
T17	101660	9653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1538299	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1538299	0	0
T1	230625	3454	0	0
T2	318934	25495	0	0
T3	494	4	0	0
T10	42971	833	0	0
T12	55337	1313	0	0
T13	1089	23	0	0
T14	504	4	0	0
T15	94869	35	0	0
T16	2981	47	0	0
T17	101660	11231	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2625480	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2625480	0	0
T1	230625	1773	0	0
T2	318934	20721	0	0
T3	494	4	0	0
T10	42971	833	0	0
T12	55337	1313	0	0
T13	1089	23	0	0
T14	504	4	0	0
T15	94869	2401	0	0
T16	2981	47	0	0
T17	101660	7270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1507352	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1507352	0	0
T1	230625	2921	0	0
T2	318934	32007	0	0
T3	494	5	0	0
T10	42971	1001	0	0
T12	55337	822	0	0
T13	1089	17	0	0
T14	504	4	0	0
T15	94869	15	0	0
T16	2981	40	0	0
T17	101660	7534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3161985	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3161985	0	0
T1	230625	1510	0	0
T2	318934	32160	0	0
T3	494	5	0	0
T10	42971	1001	0	0
T12	55337	822	0	0
T13	1089	17	0	0
T14	504	4	0	0
T15	94869	1052	0	0
T16	2981	40	0	0
T17	101660	7384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1531850	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1531850	0	0
T1	230625	3350	0	0
T2	318934	29464	0	0
T3	494	4	0	0
T10	42971	802	0	0
T12	55337	1702	0	0
T13	1089	13	0	0
T14	504	7	0	0
T15	94869	8	0	0
T16	2981	43	0	0
T17	101660	13410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2510035	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2510035	0	0
T1	230625	1604	0	0
T2	318934	27018	0	0
T3	494	4	0	0
T10	42971	802	0	0
T12	55337	1701	0	0
T13	1089	13	0	0
T14	504	7	0	0
T15	94869	854	0	0
T16	2981	43	0	0
T17	101660	17116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1559097	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1559097	0	0
T1	230625	1654	0	0
T2	318934	29255	0	0
T3	494	1	0	0
T10	42971	1034	0	0
T12	55337	858	0	0
T13	1089	24	0	0
T14	504	2	0	0
T15	94869	2	0	0
T16	2981	65	0	0
T17	101660	6504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3213565	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3213565	0	0
T1	230625	843	0	0
T2	318934	26444	0	0
T3	494	1	0	0
T10	42971	1034	0	0
T12	55337	858	0	0
T13	1089	24	0	0
T14	504	2	0	0
T15	94869	159	0	0
T16	2981	65	0	0
T17	101660	8940	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1507359	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1507359	0	0
T1	230625	1828	0	0
T2	318934	30437	0	0
T3	494	5	0	0
T10	42971	773	0	0
T12	55337	1305	0	0
T13	1089	20	0	0
T14	504	5	0	0
T15	94869	27	0	0
T16	2981	44	0	0
T17	101660	13679	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3506840	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3506840	0	0
T1	230625	935	0	0
T2	318934	29220	0	0
T3	494	5	0	0
T10	42971	773	0	0
T12	55337	1304	0	0
T13	1089	20	0	0
T14	504	5	0	0
T15	94869	1661	0	0
T16	2981	44	0	0
T17	101660	10340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1532306	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1532306	0	0
T1	230625	1454	0	0
T2	318934	34156	0	0
T3	494	2	0	0
T10	42971	787	0	0
T12	55337	673	0	0
T13	1089	17	0	0
T14	504	6	0	0
T15	94869	9	0	0
T16	2981	51	0	0
T17	101660	12899	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3340217	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3340217	0	0
T1	230625	816	0	0
T2	318934	34026	0	0
T3	494	2	0	0
T10	42971	787	0	0
T12	55337	673	0	0
T13	1089	17	0	0
T14	504	6	0	0
T15	94869	602	0	0
T16	2981	51	0	0
T17	101660	13882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1579123	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1579123	0	0
T1	230625	3194	0	0
T2	318934	30246	0	0
T3	494	7	0	0
T10	42971	747	0	0
T12	55337	660	0	0
T13	1089	17	0	0
T14	504	6	0	0
T15	94869	25	0	0
T16	2981	56	0	0
T17	101660	12178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3129586	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3129586	0	0
T1	230625	1468	0	0
T2	318934	35162	0	0
T3	494	7	0	0
T10	42971	747	0	0
T12	55337	660	0	0
T13	1089	17	0	0
T14	504	6	0	0
T15	94869	2965	0	0
T16	2981	56	0	0
T17	101660	12806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1516565	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1516565	0	0
T1	230625	1600	0	0
T2	318934	33610	0	0
T3	494	3	0	0
T10	42971	759	0	0
T12	55337	1441	0	0
T13	1089	22	0	0
T14	504	7	0	0
T15	94869	19	0	0
T16	2981	46	0	0
T17	101660	13177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2790916	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2790916	0	0
T1	230625	780	0	0
T2	318934	29822	0	0
T3	494	3	0	0
T10	42971	759	0	0
T12	55337	1441	0	0
T13	1089	22	0	0
T14	504	7	0	0
T15	94869	1334	0	0
T16	2981	46	0	0
T17	101660	8577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1533494	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1533494	0	0
T1	230625	1740	0	0
T2	318934	24714	0	0
T3	494	3	0	0
T10	42971	487	0	0
T12	55337	577	0	0
T13	1089	16	0	0
T14	504	5	0	0
T15	94869	15	0	0
T16	2981	48	0	0
T17	101660	16114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3333779	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3333779	0	0
T1	230625	922	0	0
T2	318934	22035	0	0
T3	494	3	0	0
T10	42971	487	0	0
T12	55337	577	0	0
T13	1089	16	0	0
T14	504	5	0	0
T15	94869	1056	0	0
T16	2981	48	0	0
T17	101660	16303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1531159	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1531159	0	0
T1	230625	1563	0	0
T2	318934	23085	0	0
T3	494	1	0	0
T10	42971	513	0	0
T12	55337	604	0	0
T13	1089	21	0	0
T14	504	5	0	0
T15	94869	4	0	0
T16	2981	43	0	0
T17	101660	9684	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2861690	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2861690	0	0
T1	230625	922	0	0
T2	318934	22234	0	0
T3	494	1	0	0
T10	42971	513	0	0
T12	55337	604	0	0
T13	1089	21	0	0
T14	504	5	0	0
T15	94869	66	0	0
T16	2981	43	0	0
T17	101660	9404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1517215	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1517215	0	0
T1	230625	5028	0	0
T2	318934	28863	0	0
T3	494	5	0	0
T10	42971	786	0	0
T12	55337	1191	0	0
T13	1089	14	0	0
T14	504	2	0	0
T15	94869	6	0	0
T16	2981	51	0	0
T17	101660	10795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3556008	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3556008	0	0
T1	230625	2147	0	0
T2	318934	25387	0	0
T3	494	5	0	0
T10	42971	786	0	0
T12	55337	1191	0	0
T13	1089	14	0	0
T14	504	2	0	0
T15	94869	78	0	0
T16	2981	51	0	0
T17	101660	9284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1516877	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1516877	0	0
T1	230625	1869	0	0
T2	318934	21931	0	0
T3	494	4	0	0
T10	42971	1080	0	0
T12	55337	648	0	0
T13	1089	16	0	0
T14	504	6	0	0
T15	94869	19	0	0
T16	2981	49	0	0
T17	101660	14195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2650126	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2650126	0	0
T1	230625	855	0	0
T2	318934	21867	0	0
T3	494	4	0	0
T10	42971	1080	0	0
T12	55337	648	0	0
T13	1089	16	0	0
T14	504	6	0	0
T15	94869	1725	0	0
T16	2981	49	0	0
T17	101660	12705	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1510711	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1510711	0	0
T1	230625	1631	0	0
T2	318934	31195	0	0
T3	494	7	0	0
T10	42971	490	0	0
T12	55337	1104	0	0
T13	1089	16	0	0
T14	504	4	0	0
T15	94869	30	0	0
T16	2981	69	0	0
T17	101660	9626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3414797	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3414797	0	0
T1	230625	805	0	0
T2	318934	31628	0	0
T3	494	7	0	0
T10	42971	490	0	0
T12	55337	1104	0	0
T13	1089	16	0	0
T14	504	4	0	0
T15	94869	2252	0	0
T16	2981	69	0	0
T17	101660	10131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1558150	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1558150	0	0
T1	230625	1536	0	0
T2	318934	33034	0	0
T3	494	6	0	0
T10	42971	725	0	0
T12	55337	613	0	0
T13	1089	19	0	0
T14	504	9	0	0
T15	94869	9	0	0
T16	2981	48	0	0
T17	101660	9253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3403092	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3403092	0	0
T1	230625	742	0	0
T2	318934	27942	0	0
T3	494	6	0	0
T10	42971	725	0	0
T12	55337	613	0	0
T13	1089	19	0	0
T14	504	9	0	0
T15	94869	1010	0	0
T16	2981	48	0	0
T17	101660	9927	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1534641	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1534641	0	0
T1	230625	4840	0	0
T2	318934	30207	0	0
T3	494	7	0	0
T10	42971	2036	0	0
T12	55337	1195	0	0
T13	1089	23	0	0
T14	504	7	0	0
T15	94869	18	0	0
T16	2981	65	0	0
T17	101660	11216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2649858	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2649858	0	0
T1	230625	2244	0	0
T2	318934	31699	0	0
T3	494	7	0	0
T10	42971	2036	0	0
T12	55337	1195	0	0
T13	1089	23	0	0
T14	504	7	0	0
T15	94869	592	0	0
T16	2981	65	0	0
T17	101660	9553	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1516351	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1516351	0	0
T1	230625	1660	0	0
T2	318934	28575	0	0
T3	494	3	0	0
T10	42971	1275	0	0
T12	55337	625	0	0
T13	1089	22	0	0
T14	504	9	0	0
T15	94869	28	0	0
T16	2981	53	0	0
T17	101660	12092	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3305404	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3305404	0	0
T1	230625	827	0	0
T2	318934	26221	0	0
T3	494	3	0	0
T10	42971	1275	0	0
T12	55337	625	0	0
T13	1089	22	0	0
T14	504	9	0	0
T15	94869	1532	0	0
T16	2981	53	0	0
T17	101660	11211	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1506319	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1506319	0	0
T1	230625	3078	0	0
T2	318934	23796	0	0
T3	494	3	0	0
T10	42971	830	0	0
T12	55337	1755	0	0
T13	1089	15	0	0
T14	504	4	0	0
T15	94869	37	0	0
T16	2981	48	0	0
T17	101660	9826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3114594	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3114594	0	0
T1	230625	1498	0	0
T2	318934	28433	0	0
T3	494	3	0	0
T10	42971	830	0	0
T12	55337	1755	0	0
T13	1089	15	0	0
T14	504	4	0	0
T15	94869	3494	0	0
T16	2981	48	0	0
T17	101660	8501	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1532754	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1532754	0	0
T1	230625	5925	0	0
T2	318934	19452	0	0
T3	494	5	0	0
T10	42971	802	0	0
T12	55337	825	0	0
T13	1089	17	0	0
T14	504	13	0	0
T15	94869	4	0	0
T16	2981	73	0	0
T17	101660	11785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3858251	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3858251	0	0
T1	230625	2791	0	0
T2	318934	26411	0	0
T3	494	5	0	0
T10	42971	802	0	0
T12	55337	825	0	0
T13	1089	17	0	0
T14	504	13	0	0
T15	94869	982	0	0
T16	2981	73	0	0
T17	101660	10508	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1549090	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1549090	0	0
T1	230625	3768	0	0
T2	318934	33319	0	0
T3	494	5	0	0
T10	42971	723	0	0
T12	55337	619	0	0
T13	1089	16	0	0
T14	504	4	0	0
T15	94869	5	0	0
T16	2981	48	0	0
T17	101660	5542	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3378568	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3378568	0	0
T1	230625	1872	0	0
T2	318934	29905	0	0
T3	494	5	0	0
T10	42971	723	0	0
T12	55337	619	0	0
T13	1089	16	0	0
T14	504	4	0	0
T15	94869	254	0	0
T16	2981	48	0	0
T17	101660	8992	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1508163	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1508163	0	0
T1	230625	1658	0	0
T2	318934	24089	0	0
T3	494	3	0	0
T10	42971	511	0	0
T12	55337	1348	0	0
T13	1089	14	0	0
T14	504	1	0	0
T15	94869	28	0	0
T16	2981	51	0	0
T17	101660	14609	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2873221	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2873221	0	0
T1	230625	874	0	0
T2	318934	20703	0	0
T3	494	3	0	0
T10	42971	511	0	0
T12	55337	1348	0	0
T13	1089	14	0	0
T14	504	1	0	0
T15	94869	1441	0	0
T16	2981	51	0	0
T17	101660	11060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1529800	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1529800	0	0
T1	230625	1621	0	0
T2	318934	31597	0	0
T3	494	6	0	0
T10	42971	1469	0	0
T12	55337	1229	0	0
T13	1089	25	0	0
T14	504	3	0	0
T15	94869	7	0	0
T16	2981	34	0	0
T17	101660	9940	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	3030026	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	3030026	0	0
T1	230625	780	0	0
T2	318934	25863	0	0
T3	494	6	0	0
T10	42971	1469	0	0
T12	55337	1229	0	0
T13	1089	25	0	0
T14	504	3	0	0
T15	94869	1025	0	0
T16	2981	34	0	0
T17	101660	10270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	1512172	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	1512172	0	0
T1	230625	1718	0	0
T2	318934	24644	0	0
T3	494	1	0	0
T10	42971	724	0	0
T12	55337	1128	0	0
T13	1089	22	0	0
T14	504	4	0	0
T15	94869	31	0	0
T16	2981	51	0	0
T17	101660	7836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	306407584	2749488	0	0
DepthKnown_A	306407584	306276794	0	0
RvalidKnown_A	306407584	306276794	0	0
WreadyKnown_A	306407584	306276794	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	2749488	0	0
T1	230625	892	0	0
T2	318934	18588	0	0
T3	494	1	0	0
T10	42971	724	0	0
T12	55337	1127	0	0
T13	1089	22	0	0
T14	504	4	0	0
T15	94869	1414	0	0
T16	2981	51	0	0
T17	101660	8129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306407584	306276794	0	0
T1	230625	230160	0	0
T2	318934	318931	0	0
T3	494	451	0	0
T10	42971	42623	0	0
T12	55337	54220	0	0
T13	1089	1080	0	0
T14	504	474	0	0
T15	94869	94847	0	0
T16	2981	2948	0	0
T17	101660	101658	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0