Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1742505	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

273707

1

T1

7

T2

43

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	681809	1			T1	48		T2	202		T3	38
values[0x0]	650954	1			T1	8		T2	30		T3	30
values[0x1]	683449	1			T1	51		T2	209		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1349646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

666566

1

T1

32

T2

162

T3

43

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7486	1			T2	1		T3	1		T15	10
valid_sources[0x01]	7655	1			T2	2		T15	6		T13	61
valid_sources[0x02]	7367	1			T2	1		T3	1		T15	7
valid_sources[0x03]	8717	1			T2	2		T4	10		T15	12
valid_sources[0x04]	7740	1			T1	2		T2	1		T4	10
valid_sources[0x05]	7524	1			T2	1		T15	14		T13	58
valid_sources[0x06]	7322	1			T4	24		T15	5		T13	71
valid_sources[0x07]	8162	1			T2	3		T3	2		T4	18
valid_sources[0x08]	8492	1			T2	2		T3	1		T15	11
valid_sources[0x09]	7673	1			T2	3		T3	1		T15	8
valid_sources[0x0a]	7877	1			T2	4		T3	2		T4	19
valid_sources[0x0b]	7606	1			T2	2		T15	8		T13	53
valid_sources[0x0c]	8656	1			T2	1		T15	11		T13	72
valid_sources[0x0d]	7944	1			T1	2		T2	5		T4	17
valid_sources[0x0e]	8016	1			T2	1		T3	1		T4	8
valid_sources[0x0f]	7304	1			T2	3		T15	7		T13	35
valid_sources[0x10]	7404	1			T2	1		T3	3		T4	31
valid_sources[0x11]	7430	1			T2	1		T15	11		T13	24
valid_sources[0x12]	7253	1			T15	13		T13	45		T16	3
valid_sources[0x13]	8015	1			T2	4		T3	2		T12	93
valid_sources[0x14]	7292	1			T2	3		T15	7		T13	22
valid_sources[0x15]	7177	1			T1	19		T2	1		T3	1
valid_sources[0x16]	8479	1			T2	1		T4	15		T15	7
valid_sources[0x17]	7539	1			T1	2		T4	6		T15	11
valid_sources[0x18]	7290	1			T2	1		T4	15		T15	6
valid_sources[0x19]	7950	1			T2	3		T3	1		T4	33
valid_sources[0x1a]	7499	1			T1	4		T2	2		T3	1
valid_sources[0x1b]	7419	1			T2	5		T4	5		T15	8
valid_sources[0x1c]	8104	1			T2	2		T15	11		T13	59
valid_sources[0x1d]	7750	1			T1	8		T2	1		T3	1
valid_sources[0x1e]	7707	1			T15	13		T13	57		T16	5
valid_sources[0x1f]	7478	1			T2	1		T15	15		T13	91
valid_sources[0x20]	7157	1			T2	3		T15	13		T13	50
valid_sources[0x21]	7359	1			T12	252		T15	7		T13	35
valid_sources[0x22]	7527	1			T2	7		T15	11		T13	95
valid_sources[0x23]	7178	1			T2	1		T15	11		T13	76
valid_sources[0x24]	7863	1			T1	2		T2	1		T3	1
valid_sources[0x25]	7499	1			T2	2		T4	8		T15	11
valid_sources[0x26]	8097	1			T2	1		T4	17		T15	17
valid_sources[0x27]	8600	1			T1	4		T5	67		T12	94
valid_sources[0x28]	7420	1			T2	6		T4	5		T15	12
valid_sources[0x29]	7869	1			T2	2		T12	140		T15	8
valid_sources[0x2a]	8016	1			T4	5		T15	10		T13	37
valid_sources[0x2b]	8052	1			T4	10		T15	4		T13	29
valid_sources[0x2c]	8059	1			T4	22		T15	11		T13	26
valid_sources[0x2d]	7622	1			T2	1		T15	3		T13	37
valid_sources[0x2e]	7704	1			T2	2		T3	1		T15	13
valid_sources[0x2f]	7278	1			T2	1		T15	6		T13	84
valid_sources[0x30]	9686	1			T3	2		T15	10		T13	86
valid_sources[0x31]	7564	1			T4	13		T15	10		T13	50
valid_sources[0x32]	7263	1			T2	1		T15	6		T13	42
valid_sources[0x33]	7899	1			T2	2		T5	121		T15	10
valid_sources[0x34]	8003	1			T2	1		T3	1		T4	7
valid_sources[0x35]	7336	1			T15	6		T13	35		T16	2
valid_sources[0x36]	8202	1			T2	2		T4	7		T15	5
valid_sources[0x37]	8722	1			T2	2		T4	13		T15	12
valid_sources[0x38]	7518	1			T2	4		T4	15		T15	12
valid_sources[0x39]	7812	1			T2	1		T3	1		T15	10
valid_sources[0x3a]	7161	1			T4	30		T15	9		T13	31
valid_sources[0x3b]	6876	1			T3	1		T15	16		T13	76
valid_sources[0x3c]	7553	1			T2	1		T15	13		T13	45
valid_sources[0x3d]	7956	1			T2	3		T3	1		T15	5
valid_sources[0x3e]	8280	1			T15	4		T13	64		T16	2
valid_sources[0x3f]	7937	1			T2	1		T4	17		T15	11
valid_sources[0x40]	6980	1			T2	1		T4	13		T15	7
valid_sources[0x41]	8011	1			T2	2		T3	1		T15	11
valid_sources[0x42]	7517	1			T2	2		T3	1		T15	11
valid_sources[0x43]	8589	1			T2	1		T4	33		T15	10
valid_sources[0x44]	8114	1			T2	3		T4	11		T15	6
valid_sources[0x45]	8682	1			T2	1		T3	1		T4	29
valid_sources[0x46]	7731	1			T2	3		T3	2		T15	9
valid_sources[0x47]	8069	1			T1	11		T15	7		T13	53
valid_sources[0x48]	8093	1			T3	1		T15	6		T13	50
valid_sources[0x49]	7410	1			T1	3		T2	4		T3	2
valid_sources[0x4a]	7783	1			T2	1		T3	2		T12	124
valid_sources[0x4b]	8029	1			T2	2		T3	1		T15	7
valid_sources[0x4c]	8176	1			T2	1		T15	12		T13	12
valid_sources[0x4d]	7675	1			T4	15		T15	8		T13	42
valid_sources[0x4e]	8373	1			T3	3		T15	5		T13	91
valid_sources[0x4f]	8168	1			T2	3		T15	7		T13	68
valid_sources[0x50]	7615	1			T2	1		T4	9		T12	58
valid_sources[0x51]	8072	1			T4	5		T15	15		T13	48
valid_sources[0x52]	8344	1			T2	2		T4	14		T15	8
valid_sources[0x53]	7474	1			T12	31		T15	4		T13	55
valid_sources[0x54]	7758	1			T15	8		T13	64		T14	5
valid_sources[0x55]	9061	1			T2	3		T3	2		T4	8
valid_sources[0x56]	7927	1			T2	1		T3	1		T4	32
valid_sources[0x57]	7591	1			T2	2		T4	25		T15	13
valid_sources[0x58]	7606	1			T2	1		T4	5		T15	11
valid_sources[0x59]	7579	1			T2	3		T15	6		T13	93
valid_sources[0x5a]	8374	1			T2	2		T4	22		T15	9
valid_sources[0x5b]	7691	1			T2	4		T15	8		T13	62
valid_sources[0x5c]	7853	1			T2	3		T3	1		T4	13
valid_sources[0x5d]	7546	1			T1	2		T2	3		T15	5
valid_sources[0x5e]	6990	1			T2	1		T12	95		T15	13
valid_sources[0x5f]	9258	1			T1	6		T2	1		T15	11
valid_sources[0x60]	8273	1			T1	5		T2	4		T4	16
valid_sources[0x61]	8253	1			T4	24		T15	15		T13	76
valid_sources[0x62]	8360	1			T2	4		T15	6		T13	61
valid_sources[0x63]	8122	1			T15	3		T13	21		T16	10
valid_sources[0x64]	7447	1			T2	2		T15	12		T13	71
valid_sources[0x65]	8386	1			T2	2		T4	19		T15	13
valid_sources[0x66]	7080	1			T2	1		T4	11		T15	4
valid_sources[0x67]	7188	1			T2	2		T15	9		T13	63
valid_sources[0x68]	7697	1			T15	10		T13	14		T14	3
valid_sources[0x69]	8861	1			T2	3		T3	2		T4	15
valid_sources[0x6a]	8691	1			T15	20		T13	136		T14	5
valid_sources[0x6b]	7346	1			T2	3		T15	6		T13	14
valid_sources[0x6c]	7295	1			T2	3		T3	1		T4	28
valid_sources[0x6d]	8400	1			T2	1		T15	10		T13	79
valid_sources[0x6e]	8067	1			T2	2		T3	1		T4	5
valid_sources[0x6f]	7805	1			T2	5		T15	5		T13	92
valid_sources[0x70]	8426	1			T2	2		T15	3		T13	59
valid_sources[0x71]	6562	1			T2	2		T15	9		T13	59
valid_sources[0x72]	8169	1			T2	3		T15	7		T13	62
valid_sources[0x73]	7973	1			T4	14		T12	78		T15	11
valid_sources[0x74]	7330	1			T4	6		T15	10		T13	72
valid_sources[0x75]	7387	1			T2	3		T4	23		T15	15
valid_sources[0x76]	8093	1			T12	448		T15	8		T13	52
valid_sources[0x77]	8558	1			T2	7		T3	1		T15	10
valid_sources[0x78]	8615	1			T2	3		T3	1		T4	11
valid_sources[0x79]	7191	1			T2	1		T4	7		T15	15
valid_sources[0x7a]	8047	1			T2	4		T15	9		T13	24
valid_sources[0x7b]	8154	1			T2	5		T3	2		T15	11
valid_sources[0x7c]	7315	1			T2	1		T4	35		T15	19
valid_sources[0x7d]	7399	1			T2	2		T3	2		T15	15
valid_sources[0x7e]	7258	1			T2	2		T15	9		T13	36
valid_sources[0x7f]	7846	1			T2	1		T3	1		T15	11
valid_sources[0x80]	8408	1			T1	3		T2	4		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29090

1

T1

2

T2

20

T3

5

values[0x0]

all_enables

biggest_size

215870

1

T1

3

T2

10

T3

9

values[0x1]

all_enables

biggest_size

28747

1

T1

2

T2

13

T3

4