Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	354738239	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354738239	0	0
T1	312088	12933	0	0
T2	14669088	363134	0	0
T3	4799368	149470	0	0
T4	3687936	56110	0	0
T5	57904	1850	0	0
T12	287336	12163	0	0
T13	18114824	325388	0	0
T14	2026752	88954	0	0
T15	286328	12163	0	0
T16	1433488	28894	0	0
T17	0	88507	0	0
T18	0	21677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	312088	308056	0	0
T2	14669088	14667184	0	0
T3	4799368	4798696	0	0
T4	3687936	3683960	0	0
T5	57904	56168	0	0
T12	287336	284032	0	0
T13	18114824	17993192	0	0
T14	2026752	2024008	0	0
T15	286328	283192	0	0
T16	1433488	1431920	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	312088	308056	0	0
T2	14669088	14667184	0	0
T3	4799368	4798696	0	0
T4	3687936	3683960	0	0
T5	57904	56168	0	0
T12	287336	284032	0	0
T13	18114824	17993192	0	0
T14	2026752	2024008	0	0
T15	286328	283192	0	0
T16	1433488	1431920	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	312088	308056	0	0
T2	14669088	14667184	0	0
T3	4799368	4798696	0	0
T4	3687936	3683960	0	0
T5	57904	56168	0	0
T12	287336	284032	0	0
T13	18114824	17993192	0	0
T14	2026752	2024008	0	0
T15	286328	283192	0	0
T16	1433488	1431920	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	128462295	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	128462295	0	0
T1	5573	5030	0	0
T2	261948	151801	0	0
T3	85703	83950	0	0
T4	65856	13972	0	0
T5	1034	719	0	0
T12	5131	4732	0	0
T13	323479	142101	0	0
T14	36192	32872	0	0
T15	5113	4732	0	0
T16	25598	9741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	92786313	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	92786313	0	0
T1	5573	2637	0	0
T2	261948	78320	0	0
T3	85703	32699	0	0
T4	65856	14091	0	0
T5	1034	377	0	0
T12	5131	2477	0	0
T13	323479	43794	0	0
T14	36192	19948	0	0
T15	5113	2477	0	0
T16	25598	4706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1538287	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1538287	0	0
T1	5573	100	0	0
T2	261948	2156	0	0
T3	85703	29	0	0
T4	65856	588	0	0
T5	1034	12	0	0
T12	5131	86	0	0
T13	323479	4999	0	0
T14	36192	479	0	0
T15	5113	111	0	0
T16	25598	0	0	0
T17	0	4404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3489249	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3489249	0	0
T1	5573	100	0	0
T2	261948	2320	0	0
T3	85703	1297	0	0
T4	65856	535	0	0
T5	1034	12	0	0
T12	5131	86	0	0
T13	323479	1939	0	0
T14	36192	479	0	0
T15	5113	111	0	0
T16	25598	0	0	0
T17	0	1875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1540102	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1540102	0	0
T1	5573	108	0	0
T2	261948	2420	0	0
T3	85703	28	0	0
T4	65856	572	0	0
T5	1034	9	0	0
T12	5131	80	0	0
T13	323479	3769	0	0
T14	36192	504	0	0
T15	5113	97	0	0
T16	25598	0	0	0
T17	0	1626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3389803	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3389803	0	0
T1	5573	108	0	0
T2	261948	2429	0	0
T3	85703	1608	0	0
T4	65856	570	0	0
T5	1034	9	0	0
T12	5131	80	0	0
T13	323479	1703	0	0
T14	36192	504	0	0
T15	5113	97	0	0
T16	25598	0	0	0
T17	0	2061	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1581456	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1581456	0	0
T1	5573	99	0	0
T2	261948	2384	0	0
T3	85703	21	0	0
T4	65856	438	0	0
T5	1034	14	0	0
T12	5131	89	0	0
T13	323479	2934	0	0
T14	36192	978	0	0
T15	5113	85	0	0
T16	25598	0	0	0
T17	0	1174	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3803824	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3803824	0	0
T1	5573	99	0	0
T2	261948	2530	0	0
T3	85703	1656	0	0
T4	65856	461	0	0
T5	1034	14	0	0
T12	5131	89	0	0
T13	323479	1251	0	0
T14	36192	978	0	0
T15	5113	85	0	0
T16	25598	0	0	0
T17	0	1559	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1487040	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1487040	0	0
T1	5573	96	0	0
T2	261948	2463	0	0
T3	85703	31	0	0
T4	65856	601	0	0
T5	1034	13	0	0
T12	5131	93	0	0
T13	323479	3415	0	0
T14	36192	701	0	0
T15	5113	87	0	0
T16	25598	0	0	0
T17	0	4533	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3052642	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3052642	0	0
T1	5573	96	0	0
T2	261948	2608	0	0
T3	85703	1459	0	0
T4	65856	578	0	0
T5	1034	13	0	0
T12	5131	93	0	0
T13	323479	1813	0	0
T14	36192	701	0	0
T15	5113	87	0	0
T16	25598	0	0	0
T17	0	4243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1548808	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1548808	0	0
T1	5573	121	0	0
T2	261948	2541	0	0
T3	85703	4	0	0
T4	65856	483	0	0
T5	1034	14	0	0
T12	5131	84	0	0
T13	323479	4454	0	0
T14	36192	904	0	0
T15	5113	100	0	0
T16	25598	0	0	0
T17	0	905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3191756	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3191756	0	0
T1	5573	121	0	0
T2	261948	2371	0	0
T3	85703	662	0	0
T4	65856	514	0	0
T5	1034	14	0	0
T12	5131	84	0	0
T13	323479	1786	0	0
T14	36192	904	0	0
T15	5113	100	0	0
T16	25598	0	0	0
T17	0	1892	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1508145	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1508145	0	0
T1	5573	105	0	0
T2	261948	2178	0	0
T3	85703	20	0	0
T4	65856	563	0	0
T5	1034	6	0	0
T12	5131	79	0	0
T13	323479	2518	0	0
T14	36192	472	0	0
T15	5113	106	0	0
T16	25598	0	0	0
T17	0	2236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3709943	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3709943	0	0
T1	5573	105	0	0
T2	261948	2132	0	0
T3	85703	1576	0	0
T4	65856	467	0	0
T5	1034	6	0	0
T12	5131	79	0	0
T13	323479	942	0	0
T14	36192	472	0	0
T15	5113	106	0	0
T16	25598	0	0	0
T17	0	1458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1526731	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1526731	0	0
T1	5573	103	0	0
T2	261948	2660	0	0
T3	85703	26	0	0
T4	65856	517	0	0
T5	1034	22	0	0
T12	5131	105	0	0
T13	323479	2283	0	0
T14	36192	482	0	0
T15	5113	107	0	0
T16	25598	0	0	0
T17	0	1554	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3165774	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3165774	0	0
T1	5573	103	0	0
T2	261948	2488	0	0
T3	85703	1030	0	0
T4	65856	552	0	0
T5	1034	22	0	0
T12	5131	105	0	0
T13	323479	954	0	0
T14	36192	482	0	0
T15	5113	107	0	0
T16	25598	0	0	0
T17	0	731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1559627	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1559627	0	0
T1	5573	79	0	0
T2	261948	2636	0	0
T3	85703	10	0	0
T4	65856	634	0	0
T5	1034	8	0	0
T12	5131	98	0	0
T13	323479	2009	0	0
T14	36192	707	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	3016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3530630	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3530630	0	0
T1	5573	79	0	0
T2	261948	2655	0	0
T3	85703	412	0	0
T4	65856	689	0	0
T5	1034	8	0	0
T12	5131	98	0	0
T13	323479	863	0	0
T14	36192	707	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	1038	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1534520	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1534520	0	0
T1	5573	81	0	0
T2	261948	2581	0	0
T3	85703	19	0	0
T4	65856	672	0	0
T5	1034	18	0	0
T12	5131	100	0	0
T13	323479	2389	0	0
T14	36192	684	0	0
T15	5113	110	0	0
T16	25598	1654	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3365157	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3365157	0	0
T1	5573	81	0	0
T2	261948	2454	0	0
T3	85703	1915	0	0
T4	65856	689	0	0
T5	1034	18	0	0
T12	5131	100	0	0
T13	323479	961	0	0
T14	36192	684	0	0
T15	5113	110	0	0
T16	25598	674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1534328	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1534328	0	0
T1	5573	86	0	0
T2	261948	2619	0	0
T3	85703	8	0	0
T4	65856	560	0	0
T5	1034	13	0	0
T12	5131	101	0	0
T13	323479	2295	0	0
T14	36192	807	0	0
T15	5113	89	0	0
T16	25598	0	0	0
T17	0	1569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3551240	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3551240	0	0
T1	5573	86	0	0
T2	261948	2709	0	0
T3	85703	999	0	0
T4	65856	637	0	0
T5	1034	13	0	0
T12	5131	101	0	0
T13	323479	1015	0	0
T14	36192	807	0	0
T15	5113	89	0	0
T16	25598	0	0	0
T17	0	1371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1561032	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1561032	0	0
T1	5573	88	0	0
T2	261948	2265	0	0
T3	85703	7	0	0
T4	65856	607	0	0
T5	1034	16	0	0
T12	5131	98	0	0
T13	323479	2963	0	0
T14	36192	498	0	0
T15	5113	86	0	0
T16	25598	0	0	0
T17	0	1716	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3271019	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3271019	0	0
T1	5573	88	0	0
T2	261948	2119	0	0
T3	85703	1508	0	0
T4	65856	620	0	0
T5	1034	16	0	0
T12	5131	98	0	0
T13	323479	1246	0	0
T14	36192	498	0	0
T15	5113	86	0	0
T16	25598	0	0	0
T17	0	827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1486835	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1486835	0	0
T1	5573	98	0	0
T2	261948	2423	0	0
T3	85703	0	0	0
T4	65856	468	0	0
T5	1034	18	0	0
T12	5131	90	0	0
T13	323479	2187	0	0
T14	36192	762	0	0
T15	5113	74	0	0
T16	25598	0	0	0
T17	0	1315	0	0
T18	0	10023	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3886836	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3886836	0	0
T1	5573	98	0	0
T2	261948	2460	0	0
T3	85703	0	0	0
T4	65856	490	0	0
T5	1034	18	0	0
T12	5131	90	0	0
T13	323479	902	0	0
T14	36192	762	0	0
T15	5113	74	0	0
T16	25598	0	0	0
T17	0	1730	0	0
T18	0	11654	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1543375	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1543375	0	0
T1	5573	85	0	0
T2	261948	2301	0	0
T3	85703	0	0	0
T4	65856	483	0	0
T5	1034	16	0	0
T12	5131	97	0	0
T13	323479	2132	0	0
T14	36192	476	0	0
T15	5113	84	0	0
T16	25598	1679	0	0
T17	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3444122	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3444122	0	0
T1	5573	85	0	0
T2	261948	2377	0	0
T3	85703	0	0	0
T4	65856	494	0	0
T5	1034	16	0	0
T12	5131	97	0	0
T13	323479	916	0	0
T14	36192	476	0	0
T15	5113	84	0	0
T16	25598	663	0	0
T17	0	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1532956	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1532956	0	0
T1	5573	99	0	0
T2	261948	2572	0	0
T3	85703	11	0	0
T4	65856	438	0	0
T5	1034	8	0	0
T12	5131	107	0	0
T13	323479	2289	0	0
T14	36192	690	0	0
T15	5113	73	0	0
T16	25598	0	0	0
T17	0	1649	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3634884	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3634884	0	0
T1	5573	99	0	0
T2	261948	2426	0	0
T3	85703	1122	0	0
T4	65856	453	0	0
T5	1034	8	0	0
T12	5131	107	0	0
T13	323479	978	0	0
T14	36192	690	0	0
T15	5113	73	0	0
T16	25598	0	0	0
T17	0	2806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1506701	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1506701	0	0
T1	5573	87	0	0
T2	261948	2271	0	0
T3	85703	32	0	0
T4	65856	483	0	0
T5	1034	18	0	0
T12	5131	102	0	0
T13	323479	7255	0	0
T14	36192	714	0	0
T15	5113	82	0	0
T16	25598	0	0	0
T17	0	2263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3206330	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3206330	0	0
T1	5573	87	0	0
T2	261948	2262	0	0
T3	85703	1519	0	0
T4	65856	574	0	0
T5	1034	18	0	0
T12	5131	102	0	0
T13	323479	3118	0	0
T14	36192	714	0	0
T15	5113	82	0	0
T16	25598	0	0	0
T17	0	2382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1582580	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1582580	0	0
T1	5573	87	0	0
T2	261948	2450	0	0
T3	85703	18	0	0
T4	65856	525	0	0
T5	1034	16	0	0
T12	5131	85	0	0
T13	323479	3663	0	0
T14	36192	464	0	0
T15	5113	86	0	0
T16	25598	988	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	2691410	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	2691410	0	0
T1	5573	87	0	0
T2	261948	2424	0	0
T3	85703	1139	0	0
T4	65856	518	0	0
T5	1034	16	0	0
T12	5131	85	0	0
T13	323479	1606	0	0
T14	36192	464	0	0
T15	5113	86	0	0
T16	25598	844	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1584700	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1584700	0	0
T1	5573	113	0	0
T2	261948	2562	0	0
T3	85703	25	0	0
T4	65856	480	0	0
T5	1034	10	0	0
T12	5131	95	0	0
T13	323479	2072	0	0
T14	36192	438	0	0
T15	5113	90	0	0
T16	25598	0	0	0
T17	0	3013	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	2905754	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	2905754	0	0
T1	5573	113	0	0
T2	261948	2651	0	0
T3	85703	2910	0	0
T4	65856	466	0	0
T5	1034	10	0	0
T12	5131	95	0	0
T13	323479	817	0	0
T14	36192	438	0	0
T15	5113	90	0	0
T16	25598	0	0	0
T17	0	2229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1544746	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1544746	0	0
T1	5573	106	0	0
T2	261948	2304	0	0
T3	85703	16	0	0
T4	65856	585	0	0
T5	1034	10	0	0
T12	5131	102	0	0
T13	323479	7321	0	0
T14	36192	995	0	0
T15	5113	88	0	0
T16	25598	0	0	0
T17	0	1808	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	2987539	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	2987539	0	0
T1	5573	106	0	0
T2	261948	2498	0	0
T3	85703	933	0	0
T4	65856	566	0	0
T5	1034	10	0	0
T12	5131	102	0	0
T13	323479	3348	0	0
T14	36192	995	0	0
T15	5113	88	0	0
T16	25598	0	0	0
T17	0	1405	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1580372	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1580372	0	0
T1	5573	97	0	0
T2	261948	2424	0	0
T3	85703	12	0	0
T4	65856	428	0	0
T5	1034	10	0	0
T12	5131	76	0	0
T13	323479	2486	0	0
T14	36192	481	0	0
T15	5113	89	0	0
T16	25598	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	4110479	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	4110479	0	0
T1	5573	97	0	0
T2	261948	2719	0	0
T3	85703	912	0	0
T4	65856	419	0	0
T5	1034	10	0	0
T12	5131	76	0	0
T13	323479	980	0	0
T14	36192	481	0	0
T15	5113	89	0	0
T16	25598	745	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1534757	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1534757	0	0
T1	5573	94	0	0
T2	261948	2564	0	0
T3	85703	21	0	0
T4	65856	516	0	0
T5	1034	20	0	0
T12	5131	87	0	0
T13	323479	3985	0	0
T14	36192	456	0	0
T15	5113	85	0	0
T16	25598	0	0	0
T17	0	2840	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3297387	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3297387	0	0
T1	5573	94	0	0
T2	261948	2651	0	0
T3	85703	1237	0	0
T4	65856	488	0	0
T5	1034	20	0	0
T12	5131	87	0	0
T13	323479	1728	0	0
T14	36192	456	0	0
T15	5113	85	0	0
T16	25598	0	0	0
T17	0	2725	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1555214	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1555214	0	0
T1	5573	101	0	0
T2	261948	2654	0	0
T3	85703	49	0	0
T4	65856	360	0	0
T5	1034	15	0	0
T12	5131	101	0	0
T13	323479	1866	0	0
T14	36192	1042	0	0
T15	5113	99	0	0
T16	25598	1287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3426402	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3426402	0	0
T1	5573	101	0	0
T2	261948	2591	0	0
T3	85703	1576	0	0
T4	65856	463	0	0
T5	1034	15	0	0
T12	5131	101	0	0
T13	323479	827	0	0
T14	36192	1042	0	0
T15	5113	99	0	0
T16	25598	881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1531779	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1531779	0	0
T1	5573	97	0	0
T2	261948	2259	0	0
T3	85703	11	0	0
T4	65856	483	0	0
T5	1034	13	0	0
T12	5131	81	0	0
T13	323479	4356	0	0
T14	36192	708	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	2270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	2720392	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	2720392	0	0
T1	5573	97	0	0
T2	261948	2504	0	0
T3	85703	1761	0	0
T4	65856	453	0	0
T5	1034	13	0	0
T12	5131	81	0	0
T13	323479	1954	0	0
T14	36192	708	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	1200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1536306	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1536306	0	0
T1	5573	108	0	0
T2	261948	2395	0	0
T3	85703	29	0	0
T4	65856	650	0	0
T5	1034	13	0	0
T12	5131	98	0	0
T13	323479	4090	0	0
T14	36192	655	0	0
T15	5113	109	0	0
T16	25598	0	0	0
T17	0	4978	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	2957263	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	2957263	0	0
T1	5573	108	0	0
T2	261948	2404	0	0
T3	85703	2431	0	0
T4	65856	541	0	0
T5	1034	13	0	0
T12	5131	98	0	0
T13	323479	1701	0	0
T14	36192	655	0	0
T15	5113	109	0	0
T16	25598	0	0	0
T17	0	2755	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1516727	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1516727	0	0
T1	5573	102	0	0
T2	261948	2145	0	0
T3	85703	12	0	0
T4	65856	470	0	0
T5	1034	22	0	0
T12	5131	81	0	0
T13	323479	2398	0	0
T14	36192	486	0	0
T15	5113	77	0	0
T16	25598	0	0	0
T17	0	2188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3883524	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3883524	0	0
T1	5573	102	0	0
T2	261948	2408	0	0
T3	85703	1103	0	0
T4	65856	369	0	0
T5	1034	22	0	0
T12	5131	81	0	0
T13	323479	956	0	0
T14	36192	486	0	0
T15	5113	77	0	0
T16	25598	0	0	0
T17	0	1290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1569794	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1569794	0	0
T1	5573	89	0	0
T2	261948	2560	0	0
T3	85703	12	0	0
T4	65856	434	0	0
T5	1034	14	0	0
T12	5131	92	0	0
T13	323479	7395	0	0
T14	36192	753	0	0
T15	5113	109	0	0
T16	25598	0	0	0
T17	0	3616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3534458	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3534458	0	0
T1	5573	89	0	0
T2	261948	2743	0	0
T3	85703	361	0	0
T4	65856	451	0	0
T5	1034	14	0	0
T12	5131	92	0	0
T13	323479	3382	0	0
T14	36192	753	0	0
T15	5113	109	0	0
T16	25598	0	0	0
T17	0	1342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1539510	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1539510	0	0
T1	5573	105	0	0
T2	261948	2592	0	0
T3	85703	25	0	0
T4	65856	425	0	0
T5	1034	15	0	0
T12	5131	87	0	0
T13	323479	6078	0	0
T14	36192	759	0	0
T15	5113	78	0	0
T16	25598	2265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3726368	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3726368	0	0
T1	5573	105	0	0
T2	261948	2751	0	0
T3	85703	965	0	0
T4	65856	556	0	0
T5	1034	15	0	0
T12	5131	87	0	0
T13	323479	2704	0	0
T14	36192	759	0	0
T15	5113	78	0	0
T16	25598	899	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	1501377	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	1501377	0	0
T1	5573	99	0	0
T2	261948	2476	0	0
T3	85703	6	0	0
T4	65856	501	0	0
T5	1034	14	0	0
T12	5131	83	0	0
T13	323479	3862	0	0
T14	36192	972	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	1451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	322773370	3987641	0	0
DepthKnown_A	322773370	322648098	0	0
RvalidKnown_A	322773370	322648098	0	0
WreadyKnown_A	322773370	322648098	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	3987641	0	0
T1	5573	99	0	0
T2	261948	2474	0	0
T3	85703	248	0	0
T4	65856	470	0	0
T5	1034	14	0	0
T12	5131	83	0	0
T13	323479	1640	0	0
T14	36192	972	0	0
T15	5113	92	0	0
T16	25598	0	0	0
T17	0	1282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322773370	322648098	0	0
T1	5573	5501	0	0
T2	261948	261914	0	0
T3	85703	85691	0	0
T4	65856	65785	0	0
T5	1034	1003	0	0
T12	5131	5072	0	0
T13	323479	321307	0	0
T14	36192	36143	0	0
T15	5113	5057	0	0
T16	25598	25570	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0