Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1807316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

283502

1

T1

2120

T2

369

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	706252	1			T1	5137		T2	971		T3	32
values[0x0]	677873	1			T1	5072		T2	985		T3	32
values[0x1]	706693	1			T1	5117		T2	978		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1402261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

688557

1

T1

5027

T2

907

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8094	1			T1	192		T13	43		T15	4
valid_sources[0x01]	9319	1			T1	57		T13	46		T15	11
valid_sources[0x02]	9547	1			T1	513		T4	14		T13	47
valid_sources[0x03]	8023	1			T1	93		T13	48		T14	8
valid_sources[0x04]	7501	1			T1	28		T13	21		T15	4
valid_sources[0x05]	9338	1			T1	38		T2	85		T13	33
valid_sources[0x06]	7499	1			T1	97		T13	26		T15	4
valid_sources[0x07]	7678	1			T1	22		T4	21		T13	37
valid_sources[0x08]	8792	1			T1	35		T3	1		T13	30
valid_sources[0x09]	8211	1			T1	2		T4	112		T13	34
valid_sources[0x0a]	8436	1			T1	134		T13	24		T14	1
valid_sources[0x0b]	8145	1			T1	114		T4	28		T12	14
valid_sources[0x0c]	7411	1			T1	35		T2	121		T13	42
valid_sources[0x0d]	8456	1			T1	67		T4	21		T12	6
valid_sources[0x0e]	7920	1			T1	3		T3	1		T13	16
valid_sources[0x0f]	8259	1			T1	101		T3	2		T4	1
valid_sources[0x10]	8949	1			T1	8		T4	17		T13	54
valid_sources[0x11]	8446	1			T1	88		T13	31		T15	3
valid_sources[0x12]	9845	1			T1	34		T13	21		T15	1
valid_sources[0x13]	9803	1			T1	4		T3	1		T4	11
valid_sources[0x14]	7493	1			T1	147		T13	19		T14	3
valid_sources[0x15]	8484	1			T1	5		T13	17		T15	5
valid_sources[0x16]	8487	1			T1	12		T4	4		T13	31
valid_sources[0x17]	8438	1			T1	14		T13	35		T15	7
valid_sources[0x18]	7573	1			T1	101		T13	64		T15	2
valid_sources[0x19]	8544	1			T1	7		T13	22		T15	6
valid_sources[0x1a]	8351	1			T1	12		T3	1		T13	31
valid_sources[0x1b]	8318	1			T1	38		T4	5		T12	19
valid_sources[0x1c]	7547	1			T1	68		T3	2		T4	6
valid_sources[0x1d]	7993	1			T1	41		T2	107		T4	86
valid_sources[0x1e]	7878	1			T1	79		T3	3		T13	49
valid_sources[0x1f]	7444	1			T1	245		T13	14		T15	5
valid_sources[0x20]	7731	1			T1	41		T13	16		T15	5
valid_sources[0x21]	7723	1			T1	49		T13	49		T14	25
valid_sources[0x22]	7375	1			T1	32		T4	23		T13	39
valid_sources[0x23]	8397	1			T1	222		T2	75		T3	1
valid_sources[0x24]	10022	1			T1	89		T3	1		T13	42
valid_sources[0x25]	7627	1			T1	57		T13	25		T14	2
valid_sources[0x26]	8076	1			T1	22		T3	1		T13	28
valid_sources[0x27]	8975	1			T1	35		T2	86		T3	2
valid_sources[0x28]	8200	1			T1	1		T13	11		T15	6
valid_sources[0x29]	8992	1			T1	8		T3	1		T13	20
valid_sources[0x2a]	7883	1			T1	40		T13	26		T15	9
valid_sources[0x2b]	8031	1			T1	8		T4	18		T13	56
valid_sources[0x2c]	8681	1			T1	5		T3	2		T13	61
valid_sources[0x2d]	7977	1			T1	10		T3	1		T12	9
valid_sources[0x2e]	8656	1			T1	124		T13	55		T15	6
valid_sources[0x2f]	8121	1			T1	6		T3	2		T4	25
valid_sources[0x30]	9118	1			T1	165		T4	6		T13	39
valid_sources[0x31]	7743	1			T1	47		T2	59		T13	22
valid_sources[0x32]	7543	1			T1	9		T13	58		T15	14
valid_sources[0x33]	7508	1			T1	16		T2	39		T3	2
valid_sources[0x34]	7380	1			T1	14		T13	34		T15	7
valid_sources[0x35]	7606	1			T1	24		T4	25		T13	27
valid_sources[0x36]	8547	1			T1	521		T13	54		T15	7
valid_sources[0x37]	8104	1			T1	16		T13	61		T15	5
valid_sources[0x38]	7415	1			T1	33		T4	62		T13	16
valid_sources[0x39]	7674	1			T1	19		T13	45		T15	3
valid_sources[0x3a]	7883	1			T1	9		T13	27		T15	9
valid_sources[0x3b]	7625	1			T1	51		T13	36		T15	8
valid_sources[0x3c]	8351	1			T1	27		T2	63		T13	16
valid_sources[0x3d]	7194	1			T1	12		T4	8		T13	15
valid_sources[0x3e]	7847	1			T1	9		T3	3		T13	46
valid_sources[0x3f]	7610	1			T1	31		T13	59		T15	4
valid_sources[0x40]	8865	1			T1	76		T13	19		T15	5
valid_sources[0x41]	7189	1			T1	12		T13	33		T15	1
valid_sources[0x42]	8026	1			T1	43		T3	1		T13	73
valid_sources[0x43]	7838	1			T1	117		T13	25		T15	4
valid_sources[0x44]	8281	1			T1	69		T13	43		T15	4
valid_sources[0x45]	7765	1			T1	34		T3	1		T4	45
valid_sources[0x46]	9148	1			T1	18		T2	113		T4	23
valid_sources[0x47]	8431	1			T1	64		T3	2		T13	57
valid_sources[0x48]	7864	1			T4	56		T13	29		T15	2
valid_sources[0x49]	9821	1			T1	29		T12	17		T13	36
valid_sources[0x4a]	8730	1			T1	61		T3	1		T13	32
valid_sources[0x4b]	8115	1			T1	109		T13	24		T15	5
valid_sources[0x4c]	8063	1			T1	149		T13	32		T15	8
valid_sources[0x4d]	7255	1			T1	20		T4	5		T13	50
valid_sources[0x4e]	7650	1			T1	13		T13	43		T15	4
valid_sources[0x4f]	8628	1			T1	66		T13	51		T15	10
valid_sources[0x50]	8497	1			T1	47		T4	20		T13	41
valid_sources[0x51]	7538	1			T1	6		T13	42		T15	14
valid_sources[0x52]	9157	1			T1	44		T4	35		T13	24
valid_sources[0x53]	7407	1			T1	156		T3	1		T4	19
valid_sources[0x54]	9236	1			T1	30		T13	29		T15	9
valid_sources[0x55]	8269	1			T1	50		T13	25		T15	11
valid_sources[0x56]	8129	1			T1	5		T4	1		T13	21
valid_sources[0x57]	7935	1			T1	6		T3	1		T13	29
valid_sources[0x58]	8061	1			T1	24		T4	60		T13	26
valid_sources[0x59]	7844	1			T1	125		T3	1		T13	60
valid_sources[0x5a]	9628	1			T1	41		T13	55		T14	38
valid_sources[0x5b]	7739	1			T1	49		T13	24		T14	9
valid_sources[0x5c]	7569	1			T1	11		T13	41		T15	2
valid_sources[0x5d]	8356	1			T1	12		T3	1		T4	7
valid_sources[0x5e]	9116	1			T1	23		T2	222		T3	1
valid_sources[0x5f]	9897	1			T1	307		T4	11		T13	74
valid_sources[0x60]	7669	1			T1	3		T4	4		T13	67
valid_sources[0x61]	7602	1			T1	36		T3	2		T13	7
valid_sources[0x62]	7866	1			T1	168		T13	16		T14	4
valid_sources[0x63]	8998	1			T1	42		T13	18		T14	8
valid_sources[0x64]	7537	1			T1	37		T13	28		T15	6
valid_sources[0x65]	7591	1			T1	12		T4	13		T13	41
valid_sources[0x66]	10060	1			T1	12		T13	46		T15	3
valid_sources[0x67]	7797	1			T1	37		T13	25		T14	8
valid_sources[0x68]	8623	1			T1	6		T4	14		T13	50
valid_sources[0x69]	9221	1			T1	76		T4	1		T13	30
valid_sources[0x6a]	7486	1			T1	16		T3	1		T13	30
valid_sources[0x6b]	8618	1			T1	90		T3	1		T4	24
valid_sources[0x6c]	8722	1			T1	20		T13	43		T15	7
valid_sources[0x6d]	7889	1			T1	18		T3	1		T4	3
valid_sources[0x6e]	8747	1			T1	41		T13	22		T15	5
valid_sources[0x6f]	8751	1			T1	91		T4	7		T13	27
valid_sources[0x70]	7813	1			T1	56		T13	16		T15	6
valid_sources[0x71]	8397	1			T1	9		T13	68		T14	2
valid_sources[0x72]	7974	1			T1	40		T2	232		T3	1
valid_sources[0x73]	8876	1			T1	50		T4	48		T13	30
valid_sources[0x74]	7571	1			T1	69		T3	3		T13	26
valid_sources[0x75]	7770	1			T1	123		T3	1		T13	57
valid_sources[0x76]	7887	1			T1	11		T3	1		T13	28
valid_sources[0x77]	7388	1			T1	49		T4	54		T13	55
valid_sources[0x78]	8119	1			T1	50		T13	71		T15	12
valid_sources[0x79]	8376	1			T1	249		T3	1		T13	51
valid_sources[0x7a]	7928	1			T1	23		T3	1		T4	4
valid_sources[0x7b]	8068	1			T1	14		T3	1		T4	12
valid_sources[0x7c]	8178	1			T1	2		T13	52		T15	14
valid_sources[0x7d]	10060	1			T1	215		T13	28		T14	1
valid_sources[0x7e]	7358	1			T1	13		T13	65		T15	5
valid_sources[0x7f]	8408	1			T1	12		T13	42		T15	16
valid_sources[0x80]	8132	1			T1	149		T4	9		T13	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30037

1

T1

206

T2

38

T4

19

values[0x0]

all_enables

biggest_size

223956

1

T1

1699

T2

303

T3

6

values[0x1]

all_enables

biggest_size

29509

1

T1

215

T2

28

T4

22