Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	346680468	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	346680468	0	0
T1	20320104	373757	0	0
T2	322952	14428	0	0
T3	7425544	185047	0	0
T4	2515184	66311	0	0
T12	5285224	145719	0	0
T13	10648176	215450	0	0
T14	457016	8135	0	0
T15	9032240	1705305	0	0
T16	2427656	37189	0	0
T17	72912	3016	0	0
T18	0	903790	0	0
T19	0	16928	0	0
T20	0	4223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20320104	20317752	0	0
T2	322952	321944	0	0
T3	7425544	7421960	0	0
T4	2515184	2512944	0	0
T12	5285224	5282928	0	0
T13	10648176	10647112	0	0
T14	457016	438424	0	0
T15	9032240	9032184	0	0
T16	2427656	2422392	0	0
T17	72912	69048	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20320104	20317752	0	0
T2	322952	321944	0	0
T3	7425544	7421960	0	0
T4	2515184	2512944	0	0
T12	5285224	5282928	0	0
T13	10648176	10647112	0	0
T14	457016	438424	0	0
T15	9032240	9032184	0	0
T16	2427656	2422392	0	0
T17	72912	69048	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20320104	20317752	0	0
T2	322952	321944	0	0
T3	7425544	7421960	0	0
T4	2515184	2512944	0	0
T12	5285224	5282928	0	0
T13	10648176	10647112	0	0
T14	457016	438424	0	0
T15	9032240	9032184	0	0
T16	2427656	2422392	0	0
T17	72912	69048	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	128448248	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	128448248	0	0
T1	362859	159399	0	0
T2	5767	5626	0	0
T3	132599	78695	0	0
T4	44914	27095	0	0
T12	94379	92834	0	0
T13	190146	86903	0	0
T14	8161	3799	0	0
T15	161290	776321	0	0
T16	43351	17122	0	0
T17	1302	754	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	89307454	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	89307454	0	0
T1	362859	51748	0	0
T2	5767	2934	0	0
T3	132599	37723	0	0
T4	44914	13147	0	0
T12	94379	26214	0	0
T13	190146	31670	0	0
T14	8161	973	0	0
T15	161290	195922	0	0
T16	43351	5416	0	0
T17	1302	754	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1460083	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1460083	0	0
T1	362859	1511	0	0
T2	5767	94	0	0
T3	132599	2604	0	0
T4	44914	449	0	0
T12	94379	1	0	0
T13	190146	2947	0	0
T14	8161	55	0	0
T15	161290	18568	0	0
T16	43351	432	0	0
T17	1302	0	0	0
T19	0	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3059678	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3059678	0	0
T1	362859	659	0	0
T2	5767	94	0	0
T3	132599	2184	0	0
T4	44914	500	0	0
T12	94379	477	0	0
T13	190146	1805	0	0
T14	8161	19	0	0
T15	161290	7577	0	0
T16	43351	144	0	0
T17	1302	0	0	0
T19	0	517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1470987	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1470987	0	0
T1	362859	1953	0	0
T2	5767	98	0	0
T3	132599	2159	0	0
T4	44914	504	0	0
T12	94379	22	0	0
T13	190146	5793	0	0
T14	8161	93	0	0
T15	161290	20052	0	0
T16	43351	457	0	0
T17	1302	0	0	0
T19	0	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2579272	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2579272	0	0
T1	362859	776	0	0
T2	5767	98	0	0
T3	132599	1598	0	0
T4	44914	458	0	0
T12	94379	1246	0	0
T13	190146	2530	0	0
T14	8161	38	0	0
T15	161290	6067	0	0
T16	43351	216	0	0
T17	1302	0	0	0
T19	0	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1458811	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1458811	0	0
T1	362859	1822	0	0
T2	5767	111	0	0
T3	132599	399	0	0
T4	44914	447	0	0
T12	94379	22	0	0
T13	190146	1329	0	0
T14	8161	81	0	0
T15	161290	22031	0	0
T16	43351	279	0	0
T17	1302	0	0	0
T19	0	1001	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3173035	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3173035	0	0
T1	362859	811	0	0
T2	5767	111	0	0
T3	132599	784	0	0
T4	44914	542	0	0
T12	94379	1334	0	0
T13	190146	703	0	0
T14	8161	29	0	0
T15	161290	7482	0	0
T16	43351	73	0	0
T17	1302	0	0	0
T19	0	1001	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1552440	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1552440	0	0
T1	362859	3335	0	0
T2	5767	115	0	0
T3	132599	655	0	0
T4	44914	795	0	0
T12	94379	22	0	0
T13	190146	5101	0	0
T14	8161	65	0	0
T15	161290	13676	0	0
T16	43351	349	0	0
T17	1302	0	0	0
T18	0	2407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	4131552	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	4131552	0	0
T1	362859	1306	0	0
T2	5767	115	0	0
T3	132599	104	0	0
T4	44914	600	0	0
T12	94379	1003	0	0
T13	190146	2338	0	0
T14	8161	52	0	0
T15	161290	7021	0	0
T16	43351	190	0	0
T17	1302	0	0	0
T18	0	189086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1474341	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1474341	0	0
T1	362859	1922	0	0
T2	5767	103	0	0
T3	132599	279	0	0
T4	44914	383	0	0
T12	94379	21	0	0
T13	190146	2681	0	0
T14	8161	56	0	0
T15	161290	17316	0	0
T16	43351	416	0	0
T17	1302	0	0	0
T19	0	507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3432763	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3432763	0	0
T1	362859	786	0	0
T2	5767	103	0	0
T3	132599	347	0	0
T4	44914	387	0	0
T12	94379	698	0	0
T13	190146	1445	0	0
T14	8161	29	0	0
T15	161290	5372	0	0
T16	43351	128	0	0
T17	1302	0	0	0
T19	0	507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1505446	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1505446	0	0
T1	362859	5823	0	0
T2	5767	84	0	0
T3	132599	425	0	0
T4	44914	443	0	0
T12	94379	44	0	0
T13	190146	1445	0	0
T14	8161	247	0	0
T15	161290	21211	0	0
T16	43351	374	0	0
T17	1302	0	0	0
T19	0	519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2926730	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2926730	0	0
T1	362859	2318	0	0
T2	5767	84	0	0
T3	132599	1471	0	0
T4	44914	457	0	0
T12	94379	1829	0	0
T13	190146	615	0	0
T14	8161	80	0	0
T15	161290	8121	0	0
T16	43351	159	0	0
T17	1302	0	0	0
T19	0	519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1492461	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1492461	0	0
T1	362859	3688	0	0
T2	5767	101	0	0
T3	132599	839	0	0
T4	44914	664	0	0
T12	94379	17	0	0
T13	190146	1684	0	0
T14	8161	34	0	0
T15	161290	18018	0	0
T16	43351	419	0	0
T17	1302	0	0	0
T18	0	1270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3284663	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3284663	0	0
T1	362859	2570	0	0
T2	5767	101	0	0
T3	132599	1494	0	0
T4	44914	767	0	0
T12	94379	553	0	0
T13	190146	658	0	0
T14	8161	20	0	0
T15	161290	7900	0	0
T16	43351	133	0	0
T17	1302	0	0	0
T18	0	98025	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1509305	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1509305	0	0
T1	362859	7091	0	0
T2	5767	109	0	0
T3	132599	1123	0	0
T4	44914	397	0	0
T12	94379	12	0	0
T13	190146	3849	0	0
T14	8161	72	0	0
T15	161290	13748	0	0
T16	43351	328	0	0
T17	1302	0	0	0
T18	0	1209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3613856	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3613856	0	0
T1	362859	3462	0	0
T2	5767	109	0	0
T3	132599	603	0	0
T4	44914	450	0	0
T12	94379	276	0	0
T13	190146	1660	0	0
T14	8161	32	0	0
T15	161290	6343	0	0
T16	43351	93	0	0
T17	1302	0	0	0
T18	0	89869	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1491274	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1491274	0	0
T1	362859	5458	0	0
T2	5767	124	0	0
T3	132599	414	0	0
T4	44914	476	0	0
T12	94379	29	0	0
T13	190146	3497	0	0
T14	8161	42	0	0
T15	161290	16937	0	0
T16	43351	384	0	0
T17	1302	0	0	0
T19	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3488950	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3488950	0	0
T1	362859	2402	0	0
T2	5767	124	0	0
T3	132599	500	0	0
T4	44914	464	0	0
T12	94379	2066	0	0
T13	190146	1691	0	0
T14	8161	23	0	0
T15	161290	5241	0	0
T16	43351	166	0	0
T17	1302	0	0	0
T19	0	240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1475609	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1475609	0	0
T1	362859	3575	0	0
T2	5767	125	0	0
T3	132599	1288	0	0
T4	44914	461	0	0
T12	94379	14	0	0
T13	190146	1836	0	0
T14	8161	70	0	0
T15	161290	24172	0	0
T16	43351	257	0	0
T17	1302	0	0	0
T19	0	235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2877671	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2877671	0	0
T1	362859	1486	0	0
T2	5767	125	0	0
T3	132599	1547	0	0
T4	44914	468	0	0
T12	94379	973	0	0
T13	190146	841	0	0
T14	8161	10	0	0
T15	161290	7590	0	0
T16	43351	137	0	0
T17	1302	0	0	0
T19	0	235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1489017	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1489017	0	0
T1	362859	3623	0	0
T2	5767	101	0	0
T3	132599	837	0	0
T4	44914	527	0	0
T12	94379	29	0	0
T13	190146	1309	0	0
T14	8161	28	0	0
T15	161290	24089	0	0
T16	43351	369	0	0
T17	1302	0	0	0
T19	0	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3354251	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3354251	0	0
T1	362859	1474	0	0
T2	5767	101	0	0
T3	132599	1314	0	0
T4	44914	592	0	0
T12	94379	918	0	0
T13	190146	639	0	0
T14	8161	8	0	0
T15	161290	5063	0	0
T16	43351	104	0	0
T17	1302	0	0	0
T19	0	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1506270	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1506270	0	0
T1	362859	4252	0	0
T2	5767	110	0	0
T3	132599	1212	0	0
T4	44914	506	0	0
T12	94379	19	0	0
T13	190146	6034	0	0
T14	8161	105	0	0
T15	161290	22307	0	0
T16	43351	384	0	0
T17	1302	0	0	0
T19	0	714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3423373	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3423373	0	0
T1	362859	1808	0	0
T2	5767	110	0	0
T3	132599	518	0	0
T4	44914	413	0	0
T12	94379	1185	0	0
T13	190146	2540	0	0
T14	8161	31	0	0
T15	161290	5806	0	0
T16	43351	187	0	0
T17	1302	0	0	0
T19	0	714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1574918	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1574918	0	0
T1	362859	5508	0	0
T2	5767	100	0	0
T3	132599	1765	0	0
T4	44914	379	0	0
T12	94379	0	0	0
T13	190146	1558	0	0
T14	8161	152	0	0
T15	161290	18784	0	0
T16	43351	458	0	0
T17	1302	0	0	0
T18	0	1050	0	0
T19	0	495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3696571	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3696571	0	0
T1	362859	2233	0	0
T2	5767	100	0	0
T3	132599	2460	0	0
T4	44914	411	0	0
T12	94379	0	0	0
T13	190146	670	0	0
T14	8161	56	0	0
T15	161290	8294	0	0
T16	43351	186	0	0
T17	1302	0	0	0
T18	0	80622	0	0
T19	0	495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1516958	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1516958	0	0
T1	362859	4261	0	0
T2	5767	122	0	0
T3	132599	1036	0	0
T4	44914	355	0	0
T12	94379	11	0	0
T13	190146	1342	0	0
T14	8161	55	0	0
T15	161290	20516	0	0
T16	43351	407	0	0
T17	1302	0	0	0
T18	0	957	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3714936	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3714936	0	0
T1	362859	2284	0	0
T2	5767	122	0	0
T3	132599	2145	0	0
T4	44914	389	0	0
T12	94379	1078	0	0
T13	190146	553	0	0
T14	8161	11	0	0
T15	161290	6990	0	0
T16	43351	168	0	0
T17	1302	0	0	0
T18	0	76459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1484835	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1484835	0	0
T1	362859	12159	0	0
T2	5767	115	0	0
T3	132599	1856	0	0
T4	44914	496	0	0
T12	94379	19	0	0
T13	190146	1629	0	0
T14	8161	125	0	0
T15	161290	22756	0	0
T16	43351	302	0	0
T17	1302	0	0	0
T18	0	923	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2890202	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2890202	0	0
T1	362859	6040	0	0
T2	5767	115	0	0
T3	132599	1484	0	0
T4	44914	438	0	0
T12	94379	240	0	0
T13	190146	775	0	0
T14	8161	44	0	0
T15	161290	5725	0	0
T16	43351	135	0	0
T17	1302	0	0	0
T18	0	67226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1578418	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1578418	0	0
T1	362859	3776	0	0
T2	5767	103	0	0
T3	132599	1399	0	0
T4	44914	517	0	0
T12	94379	11	0	0
T13	190146	1530	0	0
T14	8161	45	0	0
T15	161290	15813	0	0
T16	43351	406	0	0
T17	1302	0	0	0
T18	0	1381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	4100884	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	4100884	0	0
T1	362859	1688	0	0
T2	5767	103	0	0
T3	132599	1895	0	0
T4	44914	447	0	0
T12	94379	778	0	0
T13	190146	680	0	0
T14	8161	8	0	0
T15	161290	5371	0	0
T16	43351	181	0	0
T17	1302	0	0	0
T18	0	104634	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1506376	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1506376	0	0
T1	362859	3762	0	0
T2	5767	112	0	0
T3	132599	2430	0	0
T4	44914	462	0	0
T12	94379	23	0	0
T13	190146	3567	0	0
T14	8161	75	0	0
T15	161290	18689	0	0
T16	43351	332	0	0
T17	1302	0	0	0
T18	0	1088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3130710	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3130710	0	0
T1	362859	1437	0	0
T2	5767	112	0	0
T3	132599	1996	0	0
T4	44914	434	0	0
T12	94379	1614	0	0
T13	190146	2387	0	0
T14	8161	26	0	0
T15	161290	8016	0	0
T16	43351	112	0	0
T17	1302	0	0	0
T18	0	92054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1527419	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1527419	0	0
T1	362859	1831	0	0
T2	5767	106	0	0
T3	132599	2581	0	0
T4	44914	391	0	0
T12	94379	34	0	0
T13	190146	3525	0	0
T14	8161	87	0	0
T15	161290	23844	0	0
T16	43351	499	0	0
T17	1302	0	0	0
T19	0	789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3168567	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3168567	0	0
T1	362859	734	0	0
T2	5767	106	0	0
T3	132599	4018	0	0
T4	44914	352	0	0
T12	94379	1728	0	0
T13	190146	1643	0	0
T14	8161	25	0	0
T15	161290	7130	0	0
T16	43351	164	0	0
T17	1302	0	0	0
T19	0	789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1463438	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1463438	0	0
T1	362859	4069	0	0
T2	5767	109	0	0
T3	132599	1198	0	0
T4	44914	448	0	0
T12	94379	21	0	0
T13	190146	1560	0	0
T14	8161	309	0	0
T15	161290	22044	0	0
T16	43351	452	0	0
T17	1302	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2875973	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2875973	0	0
T1	362859	1693	0	0
T2	5767	109	0	0
T3	132599	1461	0	0
T4	44914	453	0	0
T12	94379	1826	0	0
T13	190146	626	0	0
T14	8161	117	0	0
T15	161290	8669	0	0
T16	43351	233	0	0
T17	1302	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1524316	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1524316	0	0
T1	362859	3096	0	0
T2	5767	115	0	0
T3	132599	1020	0	0
T4	44914	406	0	0
T12	94379	0	0	0
T13	190146	3435	0	0
T14	8161	39	0	0
T15	161290	24692	0	0
T16	43351	319	0	0
T17	1302	0	0	0
T19	0	243	0	0
T20	0	2972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3103735	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3103735	0	0
T1	362859	1253	0	0
T2	5767	115	0	0
T3	132599	1822	0	0
T4	44914	551	0	0
T12	94379	0	0	0
T13	190146	1589	0	0
T14	8161	32	0	0
T15	161290	9845	0	0
T16	43351	123	0	0
T17	1302	0	0	0
T19	0	243	0	0
T20	0	1251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1443798	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1443798	0	0
T1	362859	2038	0	0
T2	5767	101	0	0
T3	132599	234	0	0
T4	44914	468	0	0
T12	94379	2	0	0
T13	190146	1385	0	0
T14	8161	32	0	0
T15	161290	16095	0	0
T16	43351	380	0	0
T17	1302	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3078466	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3078466	0	0
T1	362859	893	0	0
T2	5767	101	0	0
T3	132599	960	0	0
T4	44914	471	0	0
T12	94379	8	0	0
T13	190146	587	0	0
T14	8161	4	0	0
T15	161290	7998	0	0
T16	43351	128	0	0
T17	1302	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1501228	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1501228	0	0
T1	362859	5923	0	0
T2	5767	124	0	0
T3	132599	443	0	0
T4	44914	606	0	0
T12	94379	9	0	0
T13	190146	1399	0	0
T14	8161	127	0	0
T15	161290	21186	0	0
T16	43351	366	0	0
T17	1302	0	0	0
T19	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3280726	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3280726	0	0
T1	362859	2639	0	0
T2	5767	124	0	0
T3	132599	381	0	0
T4	44914	652	0	0
T12	94379	1435	0	0
T13	190146	632	0	0
T14	8161	49	0	0
T15	161290	6689	0	0
T16	43351	144	0	0
T17	1302	0	0	0
T19	0	494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1510215	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1510215	0	0
T1	362859	5217	0	0
T2	5767	109	0	0
T3	132599	1405	0	0
T4	44914	536	0	0
T12	94379	22	0	0
T13	190146	1505	0	0
T14	8161	49	0	0
T15	161290	19422	0	0
T16	43351	423	0	0
T17	1302	0	0	0
T19	0	1046	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2721657	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2721657	0	0
T1	362859	2320	0	0
T2	5767	109	0	0
T3	132599	1116	0	0
T4	44914	499	0	0
T12	94379	1238	0	0
T13	190146	615	0	0
T14	8161	20	0	0
T15	161290	8204	0	0
T16	43351	178	0	0
T17	1302	0	0	0
T19	0	1046	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1534100	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1534100	0	0
T1	362859	3716	0	0
T2	5767	100	0	0
T3	132599	309	0	0
T4	44914	450	0	0
T12	94379	21	0	0
T13	190146	1377	0	0
T14	8161	112	0	0
T15	161290	19744	0	0
T16	43351	332	0	0
T17	1302	0	0	0
T19	0	254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3475209	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3475209	0	0
T1	362859	1503	0	0
T2	5767	100	0	0
T3	132599	2002	0	0
T4	44914	493	0	0
T12	94379	1449	0	0
T13	190146	681	0	0
T14	8161	39	0	0
T15	161290	9721	0	0
T16	43351	172	0	0
T17	1302	0	0	0
T19	0	254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1450455	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1450455	0	0
T1	362859	2756	0	0
T2	5767	116	0	0
T3	132599	2179	0	0
T4	44914	351	0	0
T12	94379	11	0	0
T13	190146	1555	0	0
T14	8161	79	0	0
T15	161290	20833	0	0
T16	43351	356	0	0
T17	1302	0	0	0
T19	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2928287	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2928287	0	0
T1	362859	1597	0	0
T2	5767	116	0	0
T3	132599	2309	0	0
T4	44914	371	0	0
T12	94379	652	0	0
T13	190146	641	0	0
T14	8161	36	0	0
T15	161290	8978	0	0
T16	43351	166	0	0
T17	1302	0	0	0
T19	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1491830	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1491830	0	0
T1	362859	5984	0	0
T2	5767	127	0	0
T3	132599	1	0	0
T4	44914	424	0	0
T12	94379	6	0	0
T13	190146	1388	0	0
T14	8161	65	0	0
T15	161290	19842	0	0
T16	43351	431	0	0
T17	1302	0	0	0
T18	0	1282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	3944486	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	3944486	0	0
T1	362859	2810	0	0
T2	5767	127	0	0
T3	132599	91	0	0
T4	44914	515	0	0
T12	94379	793	0	0
T13	190146	752	0	0
T14	8161	35	0	0
T15	161290	6954	0	0
T16	43351	174	0	0
T17	1302	0	0	0
T18	0	94248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	1510466	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	1510466	0	0
T1	362859	3845	0	0
T2	5767	100	0	0
T3	132599	816	0	0
T4	44914	592	0	0
T12	94379	15	0	0
T13	190146	1588	0	0
T14	8161	139	0	0
T15	161290	20756	0	0
T16	43351	529	0	0
T17	1302	274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	308216723	2963749	0	0
DepthKnown_A	308216723	308096368	0	0
RvalidKnown_A	308216723	308096368	0	0
WreadyKnown_A	308216723	308096368	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	2963749	0	0
T1	362859	1634	0	0
T2	5767	100	0	0
T3	132599	1119	0	0
T4	44914	562	0	0
T12	94379	817	0	0
T13	190146	733	0	0
T14	8161	52	0	0
T15	161290	7754	0	0
T16	43351	217	0	0
T17	1302	274	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308216723	308096368	0	0
T1	362859	362817	0	0
T2	5767	5749	0	0
T3	132599	132535	0	0
T4	44914	44874	0	0
T12	94379	94338	0	0
T13	190146	190127	0	0
T14	8161	7829	0	0
T15	161290	161289	0	0
T16	43351	43257	0	0
T17	1302	1233	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0