Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1746168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

275502

1

T1

20

T2

370

T3

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	681163	1			T1	60		T2	898		T3	158
values[0x0]	657914	1			T1	69		T2	828		T3	134
values[0x1]	682593	1			T1	60		T2	899		T3	121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1355016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

666654

1

T1

45

T2

868

T3

131

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7681	1			T3	10		T15	5		T17	3
valid_sources[0x01]	8273	1			T17	2		T19	18		T20	30
valid_sources[0x02]	8095	1			T2	204		T3	8		T17	8
valid_sources[0x03]	7877	1			T15	7		T16	1		T17	2
valid_sources[0x04]	7912	1			T15	2		T16	3		T17	9
valid_sources[0x05]	8459	1			T17	6		T18	4		T19	18
valid_sources[0x06]	7189	1			T15	2		T17	2		T18	7
valid_sources[0x07]	7715	1			T4	2		T17	2		T18	5
valid_sources[0x08]	7850	1			T14	2		T17	8		T19	17
valid_sources[0x09]	7489	1			T3	4		T4	2		T17	3
valid_sources[0x0a]	8211	1			T16	1		T17	5		T18	6
valid_sources[0x0b]	7617	1			T3	2		T4	1		T17	3
valid_sources[0x0c]	7958	1			T4	1		T15	2		T13	5
valid_sources[0x0d]	8468	1			T3	1		T15	1		T17	9
valid_sources[0x0e]	7080	1			T17	8		T18	1		T19	18
valid_sources[0x0f]	7503	1			T3	2		T17	3		T18	1
valid_sources[0x10]	7604	1			T4	1		T17	3		T18	11
valid_sources[0x11]	7940	1			T2	79		T4	3		T17	4
valid_sources[0x12]	8277	1			T16	4		T17	3		T19	20
valid_sources[0x13]	7830	1			T3	5		T17	3		T19	18
valid_sources[0x14]	7262	1			T3	3		T16	1		T17	1
valid_sources[0x15]	7618	1			T3	2		T17	5		T18	4
valid_sources[0x16]	7845	1			T12	1		T17	1		T19	19
valid_sources[0x17]	7759	1			T15	1		T12	1		T18	1
valid_sources[0x18]	8137	1			T3	12		T15	1		T17	6
valid_sources[0x19]	7475	1			T3	2		T4	1		T17	3
valid_sources[0x1a]	8768	1			T17	5		T18	1		T19	18
valid_sources[0x1b]	8501	1			T3	2		T17	9		T19	17
valid_sources[0x1c]	7435	1			T3	14		T17	5		T18	15
valid_sources[0x1d]	8820	1			T15	1		T17	3		T18	1
valid_sources[0x1e]	7217	1			T3	23		T16	1		T17	5
valid_sources[0x1f]	7617	1			T4	1		T14	1		T15	2
valid_sources[0x20]	7862	1			T15	2		T13	24		T16	1
valid_sources[0x21]	7726	1			T2	37		T4	1		T14	2
valid_sources[0x22]	7659	1			T3	4		T4	1		T13	4
valid_sources[0x23]	7632	1			T4	2		T17	2		T18	15
valid_sources[0x24]	7045	1			T4	1		T17	5		T18	3
valid_sources[0x25]	8059	1			T17	3		T19	17		T21	84
valid_sources[0x26]	6934	1			T4	1		T16	3		T17	10
valid_sources[0x27]	8305	1			T14	1		T17	1		T18	10
valid_sources[0x28]	7668	1			T1	9		T17	8		T18	1
valid_sources[0x29]	7440	1			T4	1		T14	3		T17	5
valid_sources[0x2a]	7615	1			T1	1		T15	2		T17	4
valid_sources[0x2b]	7378	1			T4	1		T14	1		T12	1
valid_sources[0x2c]	9245	1			T3	1		T17	5		T18	2
valid_sources[0x2d]	7465	1			T2	60		T17	8		T18	5
valid_sources[0x2e]	7680	1			T2	24		T4	1		T15	3
valid_sources[0x2f]	8475	1			T3	1		T4	2		T14	1
valid_sources[0x30]	8799	1			T3	3		T4	2		T15	2
valid_sources[0x31]	9000	1			T14	1		T17	3		T18	3
valid_sources[0x32]	7977	1			T15	1		T17	2		T19	18
valid_sources[0x33]	8209	1			T2	88		T17	9		T18	2
valid_sources[0x34]	7377	1			T17	1		T18	8		T19	17
valid_sources[0x35]	7486	1			T14	1		T17	3		T18	2
valid_sources[0x36]	7585	1			T2	151		T4	1		T15	1
valid_sources[0x37]	8112	1			T2	1		T4	2		T15	2
valid_sources[0x38]	7193	1			T4	1		T14	1		T12	1
valid_sources[0x39]	7035	1			T4	2		T17	2		T18	5
valid_sources[0x3a]	7444	1			T14	1		T17	4		T18	2
valid_sources[0x3b]	7581	1			T16	2		T17	3		T18	2
valid_sources[0x3c]	7998	1			T1	15		T17	2		T18	5
valid_sources[0x3d]	7810	1			T17	4		T18	1		T19	17
valid_sources[0x3e]	8420	1			T1	1		T13	4		T17	4
valid_sources[0x3f]	7102	1			T3	2		T14	1		T15	2
valid_sources[0x40]	7091	1			T17	6		T19	17		T21	116
valid_sources[0x41]	8407	1			T3	4		T17	4		T18	2
valid_sources[0x42]	7776	1			T4	1		T17	5		T18	6
valid_sources[0x43]	7865	1			T14	1		T17	3		T18	1
valid_sources[0x44]	7494	1			T14	1		T15	2		T17	9
valid_sources[0x45]	8186	1			T2	57		T3	6		T17	5
valid_sources[0x46]	8847	1			T15	2		T12	1		T17	3
valid_sources[0x47]	7197	1			T15	1		T17	3		T18	7
valid_sources[0x48]	8519	1			T2	95		T3	2		T4	1
valid_sources[0x49]	7645	1			T14	1		T17	1		T18	7
valid_sources[0x4a]	7930	1			T17	3		T19	19		T20	1
valid_sources[0x4b]	7906	1			T3	5		T17	3		T18	2
valid_sources[0x4c]	7504	1			T14	1		T15	2		T17	9
valid_sources[0x4d]	8724	1			T17	2		T18	1		T19	18
valid_sources[0x4e]	7554	1			T16	1		T17	5		T18	1
valid_sources[0x4f]	8349	1			T3	11		T4	1		T17	6
valid_sources[0x50]	7405	1			T14	1		T15	3		T13	1
valid_sources[0x51]	8456	1			T4	1		T17	3		T19	19
valid_sources[0x52]	7328	1			T1	47		T14	1		T15	3
valid_sources[0x53]	8010	1			T1	11		T2	165		T3	12
valid_sources[0x54]	8599	1			T4	1		T17	2		T18	2
valid_sources[0x55]	8789	1			T17	5		T18	5		T19	20
valid_sources[0x56]	7315	1			T4	1		T14	1		T17	4
valid_sources[0x57]	8108	1			T3	11		T4	2		T17	10
valid_sources[0x58]	7291	1			T17	1		T19	19		T21	83
valid_sources[0x59]	8347	1			T13	2		T17	2		T18	2
valid_sources[0x5a]	7450	1			T3	3		T4	1		T15	2
valid_sources[0x5b]	7764	1			T17	4		T18	4		T19	18
valid_sources[0x5c]	8163	1			T14	1		T17	3		T18	1
valid_sources[0x5d]	8380	1			T3	2		T17	2		T19	16
valid_sources[0x5e]	9054	1			T14	1		T16	1		T17	7
valid_sources[0x5f]	8267	1			T14	1		T17	5		T18	4
valid_sources[0x60]	7179	1			T14	1		T13	2		T17	3
valid_sources[0x61]	7038	1			T14	1		T15	1		T16	1
valid_sources[0x62]	8392	1			T14	3		T16	3		T17	5
valid_sources[0x63]	8013	1			T14	1		T17	2		T18	4
valid_sources[0x64]	7128	1			T1	1		T4	1		T16	1
valid_sources[0x65]	7950	1			T3	1		T15	3		T17	2
valid_sources[0x66]	9689	1			T17	4		T18	1		T19	19
valid_sources[0x67]	8753	1			T14	1		T15	1		T12	1
valid_sources[0x68]	8706	1			T4	1		T16	1		T17	1
valid_sources[0x69]	8183	1			T14	1		T17	4		T19	18
valid_sources[0x6a]	7824	1			T3	3		T14	1		T17	6
valid_sources[0x6b]	7259	1			T14	1		T15	1		T16	1
valid_sources[0x6c]	7380	1			T13	2		T16	1		T17	2
valid_sources[0x6d]	8195	1			T3	8		T14	1		T17	1
valid_sources[0x6e]	7371	1			T14	1		T17	4		T19	17
valid_sources[0x6f]	8081	1			T14	2		T17	4		T18	9
valid_sources[0x70]	7796	1			T14	1		T17	4		T18	4
valid_sources[0x71]	7445	1			T3	9		T4	1		T15	2
valid_sources[0x72]	7936	1			T4	1		T17	1		T19	17
valid_sources[0x73]	7798	1			T2	97		T3	4		T4	1
valid_sources[0x74]	7455	1			T17	3		T18	13		T19	18
valid_sources[0x75]	7728	1			T4	1		T14	1		T12	1
valid_sources[0x76]	7311	1			T4	1		T18	5		T19	17
valid_sources[0x77]	7815	1			T14	2		T16	1		T17	1
valid_sources[0x78]	7288	1			T3	9		T14	1		T15	1
valid_sources[0x79]	7426	1			T14	1		T13	2		T17	2
valid_sources[0x7a]	7537	1			T14	2		T12	1		T16	2
valid_sources[0x7b]	7480	1			T3	23		T16	1		T17	1
valid_sources[0x7c]	7834	1			T3	13		T15	1		T17	1
valid_sources[0x7d]	8070	1			T4	2		T15	4		T17	5
valid_sources[0x7e]	7924	1			T4	2		T14	1		T17	7
valid_sources[0x7f]	8176	1			T17	3		T18	3		T19	19
valid_sources[0x80]	7979	1			T4	2		T14	1		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28772

1

T1

3

T2

44

T3

5

values[0x0]

all_enables

biggest_size

218233

1

T1

13

T2

282

T3

44

values[0x1]

all_enables

biggest_size

28497

1

T1

4

T2

44

T3

4