Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	343423635	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343423635	0	0
T1	306656	8354	0	0
T2	308112	10341	0	0
T3	61656	2034	0	0
T4	38472	550	0	0
T12	491568	9846	0	0
T13	2815624	51270	0	0
T14	5221272	169409	0	0
T15	45584	630	0	0
T16	10317496	226406	0	0
T17	28183512	737157	0	0
T18	0	7622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	306656	306040	0	0
T2	308112	305312	0	0
T3	61656	59864	0	0
T4	38472	34048	0	0
T12	491568	489104	0	0
T13	2815624	2789920	0	0
T14	5221272	5220040	0	0
T15	45584	41664	0	0
T16	10317496	10316488	0	0
T17	28183512	28177632	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	306656	306040	0	0
T2	308112	305312	0	0
T3	61656	59864	0	0
T4	38472	34048	0	0
T12	491568	489104	0	0
T13	2815624	2789920	0	0
T14	5221272	5220040	0	0
T15	45584	41664	0	0
T16	10317496	10316488	0	0
T17	28183512	28177632	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	306656	306040	0	0
T2	308112	305312	0	0
T3	61656	59864	0	0
T4	38472	34048	0	0
T12	491568	489104	0	0
T13	2815624	2789920	0	0
T14	5221272	5220040	0	0
T15	45584	41664	0	0
T16	10317496	10316488	0	0
T17	28183512	28177632	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	120791260	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	120791260	0	0
T1	5476	3539	0	0
T2	5502	5140	0	0
T3	1101	795	0	0
T4	687	211	0	0
T12	8778	3999	0	0
T13	50279	23392	0	0
T14	93237	90848	0	0
T15	814	243	0	0
T16	184241	91577	0	0
T17	503277	266243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	91427351	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	91427351	0	0
T1	5476	1672	0	0
T2	5502	2625	0	0
T3	1101	413	0	0
T4	687	113	0	0
T12	8778	2684	0	0
T13	50279	6751	0	0
T14	93237	39067	0	0
T15	814	129	0	0
T16	184241	47841	0	0
T17	503277	171575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1525829	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1525829	0	0
T1	5476	96	0	0
T2	5502	66	0	0
T3	1101	13	0	0
T4	687	3	0	0
T12	8778	49	0	0
T13	50279	509	0	0
T14	93237	19	0	0
T15	814	3	0	0
T16	184241	1131	0	0
T17	503277	8110	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3343492	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3343492	0	0
T1	5476	119	0	0
T2	5502	66	0	0
T3	1101	13	0	0
T4	687	3	0	0
T12	8778	34	0	0
T13	50279	225	0	0
T14	93237	2543	0	0
T15	814	3	0	0
T16	184241	1686	0	0
T17	503277	7783	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1523071	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1523071	0	0
T1	5476	99	0	0
T2	5502	52	0	0
T3	1101	27	0	0
T4	687	3	0	0
T12	8778	42	0	0
T13	50279	312	0	0
T14	93237	17	0	0
T15	814	6	0	0
T16	184241	979	0	0
T17	503277	2664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3100501	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3100501	0	0
T1	5476	168	0	0
T2	5502	52	0	0
T3	1101	27	0	0
T4	687	3	0	0
T12	8778	75	0	0
T13	50279	114	0	0
T14	93237	1175	0	0
T15	814	6	0	0
T16	184241	1395	0	0
T17	503277	2904	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1492661	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1492661	0	0
T1	5476	111	0	0
T2	5502	43	0	0
T3	1101	10	0	0
T4	687	6	0	0
T12	8778	65	0	0
T13	50279	303	0	0
T14	93237	19	0	0
T15	814	4	0	0
T16	184241	2208	0	0
T17	503277	2901	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3297014	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3297014	0	0
T1	5476	88	0	0
T2	5502	43	0	0
T3	1101	10	0	0
T4	687	6	0	0
T12	8778	50	0	0
T13	50279	158	0	0
T14	93237	1618	0	0
T15	814	4	0	0
T16	184241	1671	0	0
T17	503277	2757	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1444686	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1444686	0	0
T1	5476	31	0	0
T2	5502	43	0	0
T3	1101	18	0	0
T4	687	4	0	0
T12	8778	56	0	0
T13	50279	477	0	0
T14	93237	10	0	0
T15	814	7	0	0
T16	184241	2894	0	0
T17	503277	4482	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	2679344	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	2679344	0	0
T1	5476	21	0	0
T2	5502	43	0	0
T3	1101	18	0	0
T4	687	4	0	0
T12	8778	23	0	0
T13	50279	118	0	0
T14	93237	600	0	0
T15	814	7	0	0
T16	184241	2308	0	0
T17	503277	4249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1524252	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1524252	0	0
T1	5476	25	0	0
T2	5502	45	0	0
T3	1101	11	0	0
T4	687	7	0	0
T12	8778	61	0	0
T13	50279	2141	0	0
T14	93237	3	0	0
T15	814	6	0	0
T16	184241	3265	0	0
T17	503277	7334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3521887	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3521887	0	0
T1	5476	62	0	0
T2	5502	45	0	0
T3	1101	11	0	0
T4	687	7	0	0
T12	8778	42	0	0
T13	50279	885	0	0
T14	93237	1000	0	0
T15	814	6	0	0
T16	184241	3794	0	0
T17	503277	6947	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1524420	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1524420	0	0
T1	5476	9	0	0
T2	5502	53	0	0
T3	1101	15	0	0
T4	687	5	0	0
T12	8778	67	0	0
T13	50279	1941	0	0
T14	93237	8	0	0
T15	814	7	0	0
T16	184241	473	0	0
T17	503277	7127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3489622	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3489622	0	0
T1	5476	7	0	0
T2	5502	53	0	0
T3	1101	15	0	0
T4	687	5	0	0
T12	8778	72	0	0
T13	50279	811	0	0
T14	93237	1530	0	0
T15	814	7	0	0
T16	184241	236	0	0
T17	503277	7212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1513758	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1513758	0	0
T1	5476	85	0	0
T2	5502	41	0	0
T3	1101	12	0	0
T4	687	2	0	0
T12	8778	59	0	0
T13	50279	415	0	0
T14	93237	32	0	0
T15	814	4	0	0
T16	184241	2182	0	0
T17	503277	4342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	2447846	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	2447846	0	0
T1	5476	102	0	0
T2	5502	41	0	0
T3	1101	12	0	0
T4	687	2	0	0
T12	8778	51	0	0
T13	50279	127	0	0
T14	93237	2336	0	0
T15	814	4	0	0
T16	184241	2731	0	0
T17	503277	4224	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1507073	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1507073	0	0
T1	5476	63	0	0
T2	5502	44	0	0
T3	1101	19	0	0
T4	687	9	0	0
T12	8778	36	0	0
T13	50279	360	0	0
T14	93237	5	0	0
T15	814	6	0	0
T16	184241	354	0	0
T17	503277	4371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	2877498	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	2877498	0	0
T1	5476	43	0	0
T2	5502	44	0	0
T3	1101	19	0	0
T4	687	9	0	0
T12	8778	13	0	0
T13	50279	131	0	0
T14	93237	1087	0	0
T15	814	6	0	0
T16	184241	30	0	0
T17	503277	5045	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1511491	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1511491	0	0
T1	5476	76	0	0
T2	5502	58	0	0
T3	1101	17	0	0
T4	687	3	0	0
T12	8778	54	0	0
T13	50279	1831	0	0
T14	93237	16	0	0
T15	814	8	0	0
T16	184241	1447	0	0
T17	503277	2810	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	4092055	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	4092055	0	0
T1	5476	98	0	0
T2	5502	58	0	0
T3	1101	17	0	0
T4	687	3	0	0
T12	8778	67	0	0
T13	50279	753	0	0
T14	93237	1745	0	0
T15	814	8	0	0
T16	184241	1427	0	0
T17	503277	2683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1517347	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1517347	0	0
T1	5476	16	0	0
T2	5502	48	0	0
T3	1101	13	0	0
T4	687	6	0	0
T12	8778	60	0	0
T13	50279	309	0	0
T14	93237	19	0	0
T15	814	9	0	0
T16	184241	791	0	0
T17	503277	4478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3286680	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3286680	0	0
T1	5476	30	0	0
T2	5502	48	0	0
T3	1101	13	0	0
T4	687	6	0	0
T12	8778	28	0	0
T13	50279	139	0	0
T14	93237	2094	0	0
T15	814	9	0	0
T16	184241	1776	0	0
T17	503277	4602	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1479231	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1479231	0	0
T1	5476	82	0	0
T2	5502	31	0	0
T3	1101	17	0	0
T4	687	3	0	0
T12	8778	102	0	0
T13	50279	390	0	0
T14	93237	24	0	0
T15	814	4	0	0
T16	184241	1245	0	0
T17	503277	6028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	2605718	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	2605718	0	0
T1	5476	44	0	0
T2	5502	31	0	0
T3	1101	17	0	0
T4	687	3	0	0
T12	8778	117	0	0
T13	50279	160	0	0
T14	93237	1650	0	0
T15	814	4	0	0
T16	184241	1400	0	0
T17	503277	6024	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1512527	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1512527	0	0
T1	5476	28	0	0
T2	5502	57	0	0
T3	1101	16	0	0
T4	687	2	0	0
T12	8778	67	0	0
T13	50279	313	0	0
T14	93237	16	0	0
T15	814	4	0	0
T16	184241	2063	0	0
T17	503277	5131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3400085	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3400085	0	0
T1	5476	42	0	0
T2	5502	57	0	0
T3	1101	16	0	0
T4	687	2	0	0
T12	8778	98	0	0
T13	50279	161	0	0
T14	93237	1128	0	0
T15	814	4	0	0
T16	184241	1132	0	0
T17	503277	4967	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1504495	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1504495	0	0
T1	5476	46	0	0
T2	5502	53	0	0
T3	1101	21	0	0
T4	687	3	0	0
T12	8778	51	0	0
T13	50279	334	0	0
T14	93237	14	0	0
T15	814	3	0	0
T16	184241	1385	0	0
T17	503277	11601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3137916	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3137916	0	0
T1	5476	55	0	0
T2	5502	53	0	0
T3	1101	21	0	0
T4	687	3	0	0
T12	8778	39	0	0
T13	50279	183	0	0
T14	93237	1495	0	0
T15	814	3	0	0
T16	184241	929	0	0
T17	503277	11712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1553805	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1553805	0	0
T1	5476	21	0	0
T2	5502	40	0	0
T3	1101	18	0	0
T4	687	5	0	0
T12	8778	20	0	0
T13	50279	272	0	0
T14	93237	30	0	0
T15	814	6	0	0
T16	184241	1028	0	0
T17	503277	3861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	4084334	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	4084334	0	0
T1	5476	18	0	0
T2	5502	40	0	0
T3	1101	18	0	0
T4	687	5	0	0
T12	8778	16	0	0
T13	50279	122	0	0
T14	93237	1409	0	0
T15	814	6	0	0
T16	184241	554	0	0
T17	503277	4436	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1537097	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1537097	0	0
T1	5476	21	0	0
T2	5502	37	0	0
T3	1101	21	0	0
T4	687	1	0	0
T12	8778	91	0	0
T13	50279	358	0	0
T14	93237	14	0	0
T15	814	4	0	0
T16	184241	463	0	0
T17	503277	2990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3485943	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3485943	0	0
T1	5476	24	0	0
T2	5502	37	0	0
T3	1101	21	0	0
T4	687	1	0	0
T12	8778	97	0	0
T13	50279	126	0	0
T14	93237	1039	0	0
T15	814	4	0	0
T16	184241	2276	0	0
T17	503277	2765	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1567767	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1567767	0	0
T1	5476	69	0	0
T2	5502	45	0	0
T3	1101	16	0	0
T4	687	7	0	0
T12	8778	18	0	0
T13	50279	368	0	0
T14	93237	14	0	0
T15	814	7	0	0
T16	184241	2442	0	0
T17	503277	2942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3977343	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3977343	0	0
T1	5476	103	0	0
T2	5502	45	0	0
T3	1101	16	0	0
T4	687	7	0	0
T12	8778	2	0	0
T13	50279	176	0	0
T14	93237	1244	0	0
T15	814	7	0	0
T16	184241	4696	0	0
T17	503277	3086	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1479371	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1479371	0	0
T1	5476	61	0	0
T2	5502	56	0	0
T3	1101	12	0	0
T4	687	3	0	0
T12	8778	82	0	0
T13	50279	323	0	0
T14	93237	10	0	0
T15	814	6	0	0
T16	184241	1019	0	0
T17	503277	2504	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	2813118	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	2813118	0	0
T1	5476	68	0	0
T2	5502	56	0	0
T3	1101	12	0	0
T4	687	3	0	0
T12	8778	64	0	0
T13	50279	80	0	0
T14	93237	1005	0	0
T15	814	6	0	0
T16	184241	834	0	0
T17	503277	2477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1483644	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1483644	0	0
T1	5476	79	0	0
T2	5502	54	0	0
T3	1101	15	0	0
T4	687	3	0	0
T12	8778	14	0	0
T13	50279	243	0	0
T14	93237	32	0	0
T15	814	3	0	0
T16	184241	2974	0	0
T17	503277	17254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3055775	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3055775	0	0
T1	5476	102	0	0
T2	5502	54	0	0
T3	1101	15	0	0
T4	687	3	0	0
T12	8778	27	0	0
T13	50279	147	0	0
T14	93237	2914	0	0
T15	814	3	0	0
T16	184241	2386	0	0
T17	503277	17091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1552452	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1552452	0	0
T1	5476	57	0	0
T2	5502	53	0	0
T3	1101	8	0	0
T4	687	5	0	0
T12	8778	59	0	0
T13	50279	335	0	0
T14	93237	17	0	0
T15	814	0	0	0
T16	184241	104	0	0
T17	503277	9508	0	0
T18	0	5773	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3380897	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3380897	0	0
T1	5476	86	0	0
T2	5502	53	0	0
T3	1101	8	0	0
T4	687	5	0	0
T12	8778	41	0	0
T13	50279	167	0	0
T14	93237	1221	0	0
T15	814	0	0	0
T16	184241	683	0	0
T17	503277	9401	0	0
T18	0	1849	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1506929	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1506929	0	0
T1	5476	18	0	0
T2	5502	45	0	0
T3	1101	20	0	0
T4	687	2	0	0
T12	8778	42	0	0
T13	50279	315	0	0
T14	93237	17	0	0
T15	814	5	0	0
T16	184241	3021	0	0
T17	503277	8683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3059021	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3059021	0	0
T1	5476	23	0	0
T2	5502	45	0	0
T3	1101	20	0	0
T4	687	2	0	0
T12	8778	58	0	0
T13	50279	109	0	0
T14	93237	1082	0	0
T15	814	5	0	0
T16	184241	3807	0	0
T17	503277	8208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1525114	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1525114	0	0
T1	5476	35	0	0
T2	5502	43	0	0
T3	1101	12	0	0
T4	687	6	0	0
T12	8778	111	0	0
T13	50279	346	0	0
T14	93237	24	0	0
T15	814	2	0	0
T16	184241	525	0	0
T17	503277	2563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3595035	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3595035	0	0
T1	5476	31	0	0
T2	5502	43	0	0
T3	1101	12	0	0
T4	687	6	0	0
T12	8778	101	0	0
T13	50279	128	0	0
T14	93237	2378	0	0
T15	814	2	0	0
T16	184241	312	0	0
T17	503277	2607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1531012	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1531012	0	0
T1	5476	52	0	0
T2	5502	57	0	0
T3	1101	14	0	0
T4	687	3	0	0
T12	8778	74	0	0
T13	50279	347	0	0
T14	93237	13	0	0
T15	814	4	0	0
T16	184241	953	0	0
T17	503277	4486	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3308040	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3308040	0	0
T1	5476	83	0	0
T2	5502	57	0	0
T3	1101	14	0	0
T4	687	3	0	0
T12	8778	55	0	0
T13	50279	129	0	0
T14	93237	853	0	0
T15	814	4	0	0
T16	184241	1999	0	0
T17	503277	4623	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1467948	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1467948	0	0
T1	5476	23	0	0
T2	5502	45	0	0
T3	1101	10	0	0
T4	687	3	0	0
T12	8778	76	0	0
T13	50279	333	0	0
T14	93237	14	0	0
T15	814	4	0	0
T16	184241	1107	0	0
T17	503277	6469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3744274	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3744274	0	0
T1	5476	40	0	0
T2	5502	45	0	0
T3	1101	10	0	0
T4	687	3	0	0
T12	8778	88	0	0
T13	50279	137	0	0
T14	93237	1187	0	0
T15	814	4	0	0
T16	184241	3310	0	0
T17	503277	6399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1536124	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1536124	0	0
T1	5476	17	0	0
T2	5502	41	0	0
T3	1101	13	0	0
T4	687	1	0	0
T12	8778	53	0	0
T13	50279	942	0	0
T14	93237	20	0	0
T15	814	4	0	0
T16	184241	2165	0	0
T17	503277	6246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3810722	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3810722	0	0
T1	5476	13	0	0
T2	5502	41	0	0
T3	1101	13	0	0
T4	687	1	0	0
T12	8778	53	0	0
T13	50279	321	0	0
T14	93237	1499	0	0
T15	814	4	0	0
T16	184241	1309	0	0
T17	503277	7072	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1511395	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1511395	0	0
T1	5476	147	0	0
T2	5502	40	0	0
T3	1101	15	0	0
T4	687	6	0	0
T12	8778	104	0	0
T13	50279	345	0	0
T14	93237	3	0	0
T15	814	7	0	0
T16	184241	603	0	0
T17	503277	3060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3732842	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3732842	0	0
T1	5476	121	0	0
T2	5502	40	0	0
T3	1101	15	0	0
T4	687	6	0	0
T12	8778	122	0	0
T13	50279	171	0	0
T14	93237	270	0	0
T15	814	7	0	0
T16	184241	2095	0	0
T17	503277	2949	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1516051	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1516051	0	0
T1	5476	59	0	0
T2	5502	36	0	0
T3	1101	20	0	0
T4	687	7	0	0
T12	8778	73	0	0
T13	50279	459	0	0
T14	93237	15	0	0
T15	814	2	0	0
T16	184241	1117	0	0
T17	503277	2370	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3306403	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3306403	0	0
T1	5476	55	0	0
T2	5502	36	0	0
T3	1101	20	0	0
T4	687	7	0	0
T12	8778	62	0	0
T13	50279	213	0	0
T14	93237	2770	0	0
T15	814	2	0	0
T16	184241	1294	0	0
T17	503277	2317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	1552451	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	1552451	0	0
T1	5476	45	0	0
T2	5502	62	0	0
T3	1101	10	0	0
T4	687	5	0	0
T12	8778	37	0	0
T13	50279	331	0	0
T14	93237	2	0	0
T15	814	4	0	0
T16	184241	1209	0	0
T17	503277	5201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316885438	3669618	0	0
DepthKnown_A	316885438	316762886	0	0
RvalidKnown_A	316885438	316762886	0	0
WreadyKnown_A	316885438	316762886	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	3669618	0	0
T1	5476	26	0	0
T2	5502	62	0	0
T3	1101	10	0	0
T4	687	5	0	0
T12	8778	45	0	0
T13	50279	184	0	0
T14	93237	195	0	0
T15	814	4	0	0
T16	184241	1771	0	0
T17	503277	5283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316885438	316762886	0	0
T1	5476	5465	0	0
T2	5502	5452	0	0
T3	1101	1069	0	0
T4	687	608	0	0
T12	8778	8734	0	0
T13	50279	49820	0	0
T14	93237	93215	0	0
T15	814	744	0	0
T16	184241	184223	0	0
T17	503277	503172	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0