Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1801022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282970

1

T1

286

T2

86

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	704099	1			T1	715		T2	211		T3	24
values[0x0]	675018	1			T1	729		T2	224		T3	5
values[0x1]	704875	1			T1	736		T2	219		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1396292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

687700

1

T1

707

T2

209

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8194	1			T1	9		T2	3		T22	3
valid_sources[0x01]	8643	1			T1	3		T2	3		T21	13
valid_sources[0x02]	7679	1			T1	6		T3	1		T21	11
valid_sources[0x03]	8140	1			T1	7		T2	2		T21	5
valid_sources[0x04]	7297	1			T1	4		T2	1		T21	20
valid_sources[0x05]	7337	1			T1	10		T2	4		T22	7
valid_sources[0x06]	7582	1			T1	7		T2	3		T22	9
valid_sources[0x07]	8775	1			T1	8		T2	3		T22	6
valid_sources[0x08]	8822	1			T1	4		T2	2		T21	14
valid_sources[0x09]	7761	1			T1	5		T2	2		T22	5
valid_sources[0x0a]	8051	1			T1	10		T2	2		T20	3
valid_sources[0x0b]	7835	1			T1	6		T2	2		T23	6
valid_sources[0x0c]	7388	1			T1	4		T2	3		T3	1
valid_sources[0x0d]	7863	1			T1	7		T2	2		T20	14
valid_sources[0x0e]	8186	1			T1	8		T2	4		T3	1
valid_sources[0x0f]	7501	1			T1	10		T2	4		T20	7
valid_sources[0x10]	8590	1			T1	1		T2	4		T21	7
valid_sources[0x11]	8130	1			T1	14		T3	1		T21	6
valid_sources[0x12]	8910	1			T1	4		T2	4		T21	6
valid_sources[0x13]	8533	1			T1	13		T2	3		T3	1
valid_sources[0x14]	8104	1			T1	12		T2	6		T22	2
valid_sources[0x15]	7572	1			T1	4		T2	2		T23	56
valid_sources[0x16]	8164	1			T1	6		T2	2		T21	7
valid_sources[0x17]	7944	1			T1	7		T2	1		T22	9
valid_sources[0x18]	8222	1			T1	8		T15	1		T22	13
valid_sources[0x19]	7825	1			T1	4		T2	5		T22	12
valid_sources[0x1a]	8773	1			T1	11		T2	2		T21	13
valid_sources[0x1b]	7512	1			T1	4		T2	1		T20	16
valid_sources[0x1c]	7931	1			T1	7		T2	2		T21	16
valid_sources[0x1d]	7601	1			T1	9		T2	2		T22	7
valid_sources[0x1e]	8198	1			T1	9		T2	6		T3	1
valid_sources[0x1f]	7937	1			T1	6		T2	1		T21	26
valid_sources[0x20]	7910	1			T1	6		T2	4		T3	2
valid_sources[0x21]	8371	1			T1	6		T2	3		T22	9
valid_sources[0x22]	8299	1			T1	5		T2	2		T20	42
valid_sources[0x23]	8955	1			T1	14		T2	1		T23	35
valid_sources[0x24]	8084	1			T1	2		T23	10		T22	5
valid_sources[0x25]	8397	1			T1	12		T21	5		T22	5
valid_sources[0x26]	7257	1			T1	6		T2	1		T22	7
valid_sources[0x27]	8422	1			T1	6		T2	6		T20	42
valid_sources[0x28]	7941	1			T1	9		T3	1		T21	16
valid_sources[0x29]	7956	1			T1	12		T2	5		T22	1
valid_sources[0x2a]	8502	1			T1	12		T21	34		T22	10
valid_sources[0x2b]	7794	1			T1	6		T2	1		T3	1
valid_sources[0x2c]	7517	1			T1	9		T2	1		T22	4
valid_sources[0x2d]	7950	1			T1	11		T2	3		T22	6
valid_sources[0x2e]	9273	1			T1	11		T2	3		T22	5
valid_sources[0x2f]	7906	1			T1	13		T22	3		T25	3
valid_sources[0x30]	10354	1			T1	9		T3	1		T22	5
valid_sources[0x31]	8113	1			T1	8		T2	4		T22	9
valid_sources[0x32]	7669	1			T1	12		T2	4		T24	49
valid_sources[0x33]	7979	1			T1	8		T2	3		T3	1
valid_sources[0x34]	8639	1			T1	8		T2	3		T22	12
valid_sources[0x35]	8501	1			T1	2		T2	4		T21	11
valid_sources[0x36]	8267	1			T1	7		T2	4		T22	10
valid_sources[0x37]	7909	1			T1	3		T2	4		T21	37
valid_sources[0x38]	9006	1			T1	6		T2	2		T21	13
valid_sources[0x39]	8411	1			T1	9		T2	2		T22	12
valid_sources[0x3a]	7572	1			T1	6		T2	1		T22	6
valid_sources[0x3b]	8308	1			T1	7		T2	1		T22	19
valid_sources[0x3c]	8077	1			T1	19		T2	2		T20	29
valid_sources[0x3d]	8885	1			T1	9		T2	4		T3	1
valid_sources[0x3e]	7660	1			T1	15		T22	5		T25	4
valid_sources[0x3f]	7326	1			T1	8		T2	1		T3	1
valid_sources[0x40]	7855	1			T1	6		T2	2		T3	1
valid_sources[0x41]	7997	1			T1	9		T2	2		T21	25
valid_sources[0x42]	7719	1			T1	6		T2	2		T21	29
valid_sources[0x43]	7816	1			T1	8		T2	3		T22	6
valid_sources[0x44]	8033	1			T1	5		T2	2		T24	9
valid_sources[0x45]	8734	1			T1	9		T3	1		T21	13
valid_sources[0x46]	8132	1			T1	13		T2	3		T22	1
valid_sources[0x47]	7717	1			T1	6		T2	1		T21	10
valid_sources[0x48]	8853	1			T1	10		T2	1		T21	5
valid_sources[0x49]	7594	1			T1	9		T2	8		T22	6
valid_sources[0x4a]	7374	1			T1	14		T2	2		T22	9
valid_sources[0x4b]	9044	1			T1	8		T2	3		T21	11
valid_sources[0x4c]	7984	1			T1	9		T2	2		T21	8
valid_sources[0x4d]	7562	1			T1	5		T2	6		T21	16
valid_sources[0x4e]	6880	1			T1	14		T2	1		T3	2
valid_sources[0x4f]	7480	1			T1	10		T2	1		T21	12
valid_sources[0x50]	7871	1			T1	9		T2	1		T21	7
valid_sources[0x51]	8177	1			T1	12		T2	7		T21	20
valid_sources[0x52]	7179	1			T1	7		T2	2		T3	1
valid_sources[0x53]	8574	1			T1	6		T2	4		T22	7
valid_sources[0x54]	8359	1			T1	7		T2	4		T21	7
valid_sources[0x55]	7927	1			T1	9		T2	3		T3	2
valid_sources[0x56]	8349	1			T1	10		T2	2		T3	1
valid_sources[0x57]	7359	1			T1	8		T2	2		T22	4
valid_sources[0x58]	7979	1			T1	16		T2	3		T3	1
valid_sources[0x59]	8084	1			T1	5		T2	3		T21	15
valid_sources[0x5a]	8178	1			T1	8		T2	4		T21	15
valid_sources[0x5b]	8778	1			T1	8		T2	2		T22	8
valid_sources[0x5c]	9222	1			T1	8		T2	3		T21	16
valid_sources[0x5d]	7449	1			T1	12		T2	2		T20	55
valid_sources[0x5e]	8986	1			T1	9		T2	2		T22	7
valid_sources[0x5f]	7323	1			T1	7		T2	4		T22	11
valid_sources[0x60]	8455	1			T1	1		T2	4		T22	11
valid_sources[0x61]	8402	1			T1	18		T2	6		T3	1
valid_sources[0x62]	9359	1			T1	10		T2	6		T22	10
valid_sources[0x63]	8163	1			T1	10		T2	1		T22	9
valid_sources[0x64]	8149	1			T1	5		T2	4		T21	19
valid_sources[0x65]	8257	1			T1	11		T2	1		T21	22
valid_sources[0x66]	7569	1			T1	5		T2	2		T21	9
valid_sources[0x67]	7660	1			T1	9		T2	2		T22	17
valid_sources[0x68]	8424	1			T1	5		T2	4		T21	18
valid_sources[0x69]	8595	1			T1	4		T2	1		T21	14
valid_sources[0x6a]	7463	1			T1	7		T2	3		T22	4
valid_sources[0x6b]	10616	1			T1	19		T2	1		T23	8
valid_sources[0x6c]	7953	1			T1	7		T2	1		T22	12
valid_sources[0x6d]	7379	1			T1	8		T2	1		T21	24
valid_sources[0x6e]	8444	1			T1	8		T2	2		T22	10
valid_sources[0x6f]	7547	1			T1	6		T2	2		T23	11
valid_sources[0x70]	7955	1			T1	6		T2	4		T20	121
valid_sources[0x71]	8087	1			T1	7		T2	3		T22	8
valid_sources[0x72]	8904	1			T1	8		T2	3		T3	1
valid_sources[0x73]	7428	1			T1	7		T2	4		T22	5
valid_sources[0x74]	8338	1			T1	11		T2	2		T24	29
valid_sources[0x75]	8193	1			T1	4		T22	11		T25	4
valid_sources[0x76]	8054	1			T1	4		T2	3		T20	50
valid_sources[0x77]	8252	1			T1	11		T2	3		T3	1
valid_sources[0x78]	8750	1			T1	2		T2	4		T22	9
valid_sources[0x79]	7729	1			T1	7		T2	4		T21	10
valid_sources[0x7a]	7313	1			T1	7		T2	1		T3	1
valid_sources[0x7b]	7325	1			T1	15		T2	2		T22	6
valid_sources[0x7c]	8585	1			T1	10		T24	1		T22	1
valid_sources[0x7d]	9157	1			T1	8		T2	1		T3	1
valid_sources[0x7e]	7054	1			T1	4		T2	5		T22	14
valid_sources[0x7f]	7879	1			T1	12		T2	5		T21	13
valid_sources[0x80]	8273	1			T1	8		T2	1		T22	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29508

1

T1

18

T2

12

T3

2

values[0x0]

all_enables

biggest_size

223728

1

T1

231

T2

66

T3

2

values[0x1]

all_enables

biggest_size

29734

1

T1

37

T2

8

T23

2