Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	339995202	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	339995202	0	0
T1	15202712	2352416	0	0
T2	37467472	1172772	0	0
T3	1850968	41253	0	0
T15	221704	3829	0	0
T17	0	30720	0	0
T20	5924240	1022002	0	0
T21	3316992	47551	0	0
T22	2137072	60074	0	0
T23	9769032	193552	0	0
T24	8904056	207584	0	0
T25	47788552	708394	0	0
T26	0	4182	0	0
T27	0	1637	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15202712	15202488	0	0
T2	37467472	37464280	0	0
T3	1850968	1850632	0	0
T15	221704	219072	0	0
T20	5924240	5923848	0	0
T21	3316992	3316208	0	0
T22	2137072	2133768	0	0
T23	9769032	9767744	0	0
T24	8904056	8903104	0	0
T25	47788552	47786760	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15202712	15202488	0	0
T2	37467472	37464280	0	0
T3	1850968	1850632	0	0
T15	221704	219072	0	0
T20	5924240	5923848	0	0
T21	3316992	3316208	0	0
T22	2137072	2133768	0	0
T23	9769032	9767744	0	0
T24	8904056	8903104	0	0
T25	47788552	47786760	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15202712	15202488	0	0
T2	37467472	37464280	0	0
T3	1850968	1850632	0	0
T15	221704	219072	0	0
T20	5924240	5923848	0	0
T21	3316992	3316208	0	0
T22	2137072	2133768	0	0
T23	9769032	9767744	0	0
T24	8904056	8903104	0	0
T25	47788552	47786760	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T15	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0
T24	56	56	0	0
T25	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	130096455	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	130096455	0	0
T1	271477	156004	0	0
T2	669062	660996	0	0
T3	33053	17154	0	0
T15	3959	1657	0	0
T20	105790	462398	0	0
T21	59232	11927	0	0
T22	38162	14106	0	0
T23	174447	92550	0	0
T24	159001	86361	0	0
T25	853367	4728	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	84378034	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	84378034	0	0
T1	271477	735686	0	0
T2	669062	254436	0	0
T3	33053	7481	0	0
T15	3959	526	0	0
T20	105790	115999	0	0
T21	59232	11858	0	0
T22	38162	15931	0	0
T23	174447	19856	0	0
T24	159001	39582	0	0
T25	853367	349469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1588919	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1588919	0	0
T1	271477	22324	0	0
T2	669062	113	0	0
T3	33053	280	0	0
T15	3959	19	0	0
T17	0	715	0	0
T20	105790	11136	0	0
T21	59232	583	0	0
T22	38162	0	0	0
T23	174447	2317	0	0
T24	159001	242	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2680876	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2680876	0	0
T1	271477	26876	0	0
T2	669062	7727	0	0
T3	33053	212	0	0
T15	3959	22	0	0
T17	0	715	0	0
T20	105790	3897	0	0
T21	59232	473	0	0
T22	38162	0	0	0
T23	174447	846	0	0
T24	159001	1039	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1560282	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1560282	0	0
T1	271477	24959	0	0
T2	669062	103	0	0
T3	33053	394	0	0
T15	3959	19	0	0
T17	0	878	0	0
T20	105790	14801	0	0
T21	59232	460	0	0
T22	38162	0	0	0
T23	174447	1508	0	0
T24	159001	1651	0	0
T25	853367	0	0	0
T26	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2970354	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2970354	0	0
T1	271477	28844	0	0
T2	669062	10305	0	0
T3	33053	313	0	0
T15	3959	23	0	0
T17	0	878	0	0
T20	105790	5514	0	0
T21	59232	411	0	0
T22	38162	0	0	0
T23	174447	752	0	0
T24	159001	1222	0	0
T25	853367	0	0	0
T26	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1547800	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1547800	0	0
T1	271477	25433	0	0
T2	669062	82	0	0
T3	33053	293	0	0
T15	3959	37	0	0
T20	105790	15710	0	0
T21	59232	495	0	0
T22	38162	2369	0	0
T23	174447	3493	0	0
T24	159001	1929	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3119113	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3119113	0	0
T1	271477	27206	0	0
T2	669062	6384	0	0
T3	33053	269	0	0
T15	3959	9	0	0
T20	105790	4818	0	0
T21	59232	512	0	0
T22	38162	2269	0	0
T23	174447	989	0	0
T24	159001	1131	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1539652	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1539652	0	0
T1	271477	27235	0	0
T2	669062	74	0	0
T3	33053	281	0	0
T15	3959	68	0	0
T20	105790	11429	0	0
T21	59232	384	0	0
T22	38162	2392	0	0
T23	174447	1795	0	0
T24	159001	4024	0	0
T25	853367	1089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3471149	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3471149	0	0
T1	271477	24277	0	0
T2	669062	8215	0	0
T3	33053	239	0	0
T15	3959	19	0	0
T20	105790	3516	0	0
T21	59232	497	0	0
T22	38162	2424	0	0
T23	174447	832	0	0
T24	159001	5231	0	0
T25	853367	84275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1522993	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1522993	0	0
T1	271477	29417	0	0
T2	669062	105	0	0
T3	33053	309	0	0
T15	3959	34	0	0
T17	0	865	0	0
T20	105790	10232	0	0
T21	59232	403	0	0
T22	38162	0	0	0
T23	174447	3381	0	0
T24	159001	2283	0	0
T25	853367	0	0	0
T26	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3038291	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3038291	0	0
T1	271477	30825	0	0
T2	669062	8571	0	0
T3	33053	285	0	0
T15	3959	21	0	0
T17	0	865	0	0
T20	105790	4649	0	0
T21	59232	345	0	0
T22	38162	0	0	0
T23	174447	177	0	0
T24	159001	2356	0	0
T25	853367	0	0	0
T26	0	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1521830	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1521830	0	0
T1	271477	24086	0	0
T2	669062	80	0	0
T3	33053	260	0	0
T15	3959	0	0	0
T17	0	728	0	0
T20	105790	14272	0	0
T21	59232	417	0	0
T22	38162	0	0	0
T23	174447	1442	0	0
T24	159001	1972	0	0
T25	853367	0	0	0
T26	0	93	0	0
T27	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3645309	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3645309	0	0
T1	271477	25285	0	0
T2	669062	8690	0	0
T3	33053	269	0	0
T15	3959	0	0	0
T17	0	728	0	0
T20	105790	5555	0	0
T21	59232	427	0	0
T22	38162	0	0	0
T23	174447	669	0	0
T24	159001	1269	0	0
T25	853367	0	0	0
T26	0	93	0	0
T27	0	1616	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1600591	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1600591	0	0
T1	271477	25004	0	0
T2	669062	159	0	0
T3	33053	400	0	0
T15	3959	74	0	0
T20	105790	13377	0	0
T21	59232	433	0	0
T22	38162	1844	0	0
T23	174447	2517	0	0
T24	159001	1815	0	0
T25	853367	1126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3659591	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3659591	0	0
T1	271477	22946	0	0
T2	669062	17370	0	0
T3	33053	318	0	0
T15	3959	42	0	0
T20	105790	3287	0	0
T21	59232	438	0	0
T22	38162	1893	0	0
T23	174447	264	0	0
T24	159001	834	0	0
T25	853367	83874	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1564247	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1564247	0	0
T1	271477	32609	0	0
T2	669062	131	0	0
T3	33053	221	0	0
T15	3959	59	0	0
T17	0	463	0	0
T20	105790	10195	0	0
T21	59232	367	0	0
T22	38162	0	0	0
T23	174447	101	0	0
T24	159001	1046	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2782707	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2782707	0	0
T1	271477	28523	0	0
T2	669062	14604	0	0
T3	33053	136	0	0
T15	3959	39	0	0
T17	0	463	0	0
T20	105790	3819	0	0
T21	59232	370	0	0
T22	38162	0	0	0
T23	174447	538	0	0
T24	159001	142	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1580268	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1580268	0	0
T1	271477	30544	0	0
T2	669062	121	0	0
T3	33053	268	0	0
T15	3959	3	0	0
T17	0	680	0	0
T20	105790	11030	0	0
T21	59232	499	0	0
T22	38162	0	0	0
T23	174447	1187	0	0
T24	159001	530	0	0
T25	853367	0	0	0
T26	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	4094153	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	4094153	0	0
T1	271477	27496	0	0
T2	669062	8794	0	0
T3	33053	300	0	0
T15	3959	1	0	0
T17	0	680	0	0
T20	105790	5895	0	0
T21	59232	424	0	0
T22	38162	0	0	0
T23	174447	554	0	0
T24	159001	1404	0	0
T25	853367	0	0	0
T26	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1575386	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1575386	0	0
T1	271477	27144	0	0
T2	669062	95	0	0
T3	33053	392	0	0
T15	3959	38	0	0
T17	0	749	0	0
T20	105790	9446	0	0
T21	59232	470	0	0
T22	38162	0	0	0
T23	174447	2502	0	0
T24	159001	833	0	0
T25	853367	0	0	0
T26	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3463398	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3463398	0	0
T1	271477	21809	0	0
T2	669062	6237	0	0
T3	33053	264	0	0
T15	3959	26	0	0
T17	0	749	0	0
T20	105790	2391	0	0
T21	59232	474	0	0
T22	38162	0	0	0
T23	174447	1100	0	0
T24	159001	864	0	0
T25	853367	0	0	0
T26	0	88	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1552626	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1552626	0	0
T1	271477	29261	0	0
T2	669062	116	0	0
T3	33053	288	0	0
T15	3959	22	0	0
T20	105790	13371	0	0
T21	59232	530	0	0
T22	38162	0	0	0
T23	174447	470	0	0
T24	159001	1206	0	0
T25	853367	1232	0	0
T26	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3523297	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3523297	0	0
T1	271477	26239	0	0
T2	669062	8209	0	0
T3	33053	224	0	0
T15	3959	2	0	0
T20	105790	4355	0	0
T21	59232	501	0	0
T22	38162	0	0	0
T23	174447	244	0	0
T24	159001	925	0	0
T25	853367	81477	0	0
T26	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1523833	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1523833	0	0
T1	271477	23347	0	0
T2	669062	89	0	0
T3	33053	380	0	0
T15	3959	4	0	0
T17	0	519	0	0
T20	105790	9637	0	0
T21	59232	359	0	0
T22	38162	0	0	0
T23	174447	2165	0	0
T24	159001	1812	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2312169	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2312169	0	0
T1	271477	20640	0	0
T2	669062	9815	0	0
T3	33053	325	0	0
T15	3959	3	0	0
T17	0	518	0	0
T20	105790	4993	0	0
T21	59232	448	0	0
T22	38162	0	0	0
T23	174447	354	0	0
T24	159001	2421	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1545759	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1545759	0	0
T1	271477	25727	0	0
T2	669062	140	0	0
T3	33053	418	0	0
T15	3959	65	0	0
T17	0	1476	0	0
T20	105790	11461	0	0
T21	59232	470	0	0
T22	38162	0	0	0
T23	174447	2287	0	0
T24	159001	1140	0	0
T25	853367	0	0	0
T26	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2572517	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2572517	0	0
T1	271477	30013	0	0
T2	669062	9900	0	0
T3	33053	250	0	0
T15	3959	28	0	0
T17	0	1476	0	0
T20	105790	4932	0	0
T21	59232	440	0	0
T22	38162	0	0	0
T23	174447	1159	0	0
T24	159001	644	0	0
T25	853367	0	0	0
T26	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1562563	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1562563	0	0
T1	271477	26834	0	0
T2	669062	91	0	0
T3	33053	273	0	0
T15	3959	43	0	0
T17	0	784	0	0
T20	105790	9953	0	0
T21	59232	377	0	0
T22	38162	0	0	0
T23	174447	2414	0	0
T24	159001	385	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3113057	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3113057	0	0
T1	271477	30402	0	0
T2	669062	7653	0	0
T3	33053	194	0	0
T15	3959	7	0	0
T17	0	784	0	0
T20	105790	3591	0	0
T21	59232	285	0	0
T22	38162	0	0	0
T23	174447	435	0	0
T24	159001	696	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1498068	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1498068	0	0
T1	271477	23443	0	0
T2	669062	137	0	0
T3	33053	404	0	0
T15	3959	24	0	0
T20	105790	13140	0	0
T21	59232	346	0	0
T22	38162	0	0	0
T23	174447	4434	0	0
T24	159001	1271	0	0
T25	853367	1281	0	0
T26	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2486198	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2486198	0	0
T1	271477	21897	0	0
T2	669062	11801	0	0
T3	33053	305	0	0
T15	3959	3	0	0
T20	105790	3746	0	0
T21	59232	377	0	0
T22	38162	0	0	0
T23	174447	1461	0	0
T24	159001	1685	0	0
T25	853367	99843	0	0
T26	0	87	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1528739	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1528739	0	0
T1	271477	31733	0	0
T2	669062	53	0	0
T3	33053	490	0	0
T15	3959	37	0	0
T20	105790	9798	0	0
T21	59232	493	0	0
T22	38162	2086	0	0
T23	174447	4002	0	0
T24	159001	629	0	0
T25	853367	0	0	0
T26	0	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3185795	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3185795	0	0
T1	271477	30433	0	0
T2	669062	4762	0	0
T3	33053	396	0	0
T15	3959	16	0	0
T20	105790	3067	0	0
T21	59232	525	0	0
T22	38162	2028	0	0
T23	174447	270	0	0
T24	159001	635	0	0
T25	853367	0	0	0
T26	0	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1543664	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1543664	0	0
T1	271477	24402	0	0
T2	669062	94	0	0
T3	33053	288	0	0
T15	3959	43	0	0
T17	0	579	0	0
T20	105790	11165	0	0
T21	59232	493	0	0
T22	38162	0	0	0
T23	174447	1175	0	0
T24	159001	2967	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2490053	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2490053	0	0
T1	271477	25371	0	0
T2	669062	8014	0	0
T3	33053	288	0	0
T15	3959	7	0	0
T17	0	578	0	0
T20	105790	3306	0	0
T21	59232	528	0	0
T22	38162	0	0	0
T23	174447	423	0	0
T24	159001	2057	0	0
T25	853367	0	0	0
T26	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1579816	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1579816	0	0
T1	271477	27749	0	0
T2	669062	97	0	0
T3	33053	293	0	0
T15	3959	35	0	0
T17	0	1512	0	0
T20	105790	12963	0	0
T21	59232	417	0	0
T22	38162	0	0	0
T23	174447	2986	0	0
T24	159001	1636	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2527372	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2527372	0	0
T1	271477	27011	0	0
T2	669062	7853	0	0
T3	33053	292	0	0
T15	3959	28	0	0
T17	0	1511	0	0
T20	105790	4760	0	0
T21	59232	421	0	0
T22	38162	0	0	0
T23	174447	1152	0	0
T24	159001	791	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1598153	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1598153	0	0
T1	271477	24882	0	0
T2	669062	117	0	0
T3	33053	365	0	0
T15	3959	37	0	0
T20	105790	17958	0	0
T21	59232	447	0	0
T22	38162	2923	0	0
T23	174447	1494	0	0
T24	159001	1716	0	0
T25	853367	0	0	0
T26	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3343278	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3343278	0	0
T1	271477	22288	0	0
T2	669062	9173	0	0
T3	33053	262	0	0
T15	3959	27	0	0
T20	105790	5677	0	0
T21	59232	466	0	0
T22	38162	3760	0	0
T23	174447	785	0	0
T24	159001	2227	0	0
T25	853367	0	0	0
T26	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1582917	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1582917	0	0
T1	271477	27248	0	0
T2	669062	113	0	0
T3	33053	261	0	0
T15	3959	69	0	0
T17	0	788	0	0
T20	105790	10200	0	0
T21	59232	553	0	0
T22	38162	0	0	0
T23	174447	2810	0	0
T24	159001	2380	0	0
T25	853367	0	0	0
T26	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3304058	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3304058	0	0
T1	271477	30455	0	0
T2	669062	9304	0	0
T3	33053	258	0	0
T15	3959	34	0	0
T17	0	787	0	0
T20	105790	2553	0	0
T21	59232	538	0	0
T22	38162	0	0	0
T23	174447	569	0	0
T24	159001	2780	0	0
T25	853367	0	0	0
T26	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1545740	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1545740	0	0
T1	271477	25371	0	0
T2	669062	128	0	0
T3	33053	410	0	0
T15	3959	67	0	0
T17	0	781	0	0
T20	105790	15263	0	0
T21	59232	349	0	0
T22	38162	0	0	0
T23	174447	2332	0	0
T24	159001	1295	0	0
T25	853367	0	0	0
T26	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3728624	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3728624	0	0
T1	271477	28349	0	0
T2	669062	10943	0	0
T3	33053	395	0	0
T15	3959	21	0	0
T17	0	781	0	0
T20	105790	5954	0	0
T21	59232	346	0	0
T22	38162	0	0	0
T23	174447	364	0	0
T24	159001	636	0	0
T25	853367	0	0	0
T26	0	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1590407	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1590407	0	0
T1	271477	29252	0	0
T2	669062	126	0	0
T3	33053	361	0	0
T15	3959	61	0	0
T20	105790	10939	0	0
T21	59232	231	0	0
T22	38162	2492	0	0
T23	174447	3369	0	0
T24	159001	2565	0	0
T25	853367	0	0	0
T26	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2444327	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2444327	0	0
T1	271477	33016	0	0
T2	669062	9558	0	0
T3	33053	250	0	0
T15	3959	10	0	0
T20	105790	2934	0	0
T21	59232	244	0	0
T22	38162	3557	0	0
T23	174447	1857	0	0
T24	159001	3147	0	0
T25	853367	0	0	0
T26	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1535903	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1535903	0	0
T1	271477	25426	0	0
T2	669062	141	0	0
T3	33053	371	0	0
T15	3959	37	0	0
T17	0	474	0	0
T20	105790	13308	0	0
T21	59232	557	0	0
T22	38162	0	0	0
T23	174447	2661	0	0
T24	159001	1523	0	0
T25	853367	0	0	0
T26	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3672251	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3672251	0	0
T1	271477	27242	0	0
T2	669062	12310	0	0
T3	33053	250	0	0
T15	3959	21	0	0
T17	0	474	0	0
T20	105790	3481	0	0
T21	59232	564	0	0
T22	38162	0	0	0
T23	174447	1004	0	0
T24	159001	854	0	0
T25	853367	0	0	0
T26	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1526109	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1526109	0	0
T1	271477	31247	0	0
T2	669062	94	0	0
T3	33053	338	0	0
T15	3959	57	0	0
T17	0	571	0	0
T20	105790	17573	0	0
T21	59232	392	0	0
T22	38162	0	0	0
T23	174447	1458	0	0
T24	159001	1251	0	0
T25	853367	0	0	0
T26	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3166817	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3166817	0	0
T1	271477	28522	0	0
T2	669062	8946	0	0
T3	33053	307	0	0
T15	3959	33	0	0
T17	0	571	0	0
T20	105790	7537	0	0
T21	59232	391	0	0
T22	38162	0	0	0
T23	174447	299	0	0
T24	159001	717	0	0
T25	853367	0	0	0
T26	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1549866	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1549866	0	0
T1	271477	23101	0	0
T2	669062	120	0	0
T3	33053	432	0	0
T15	3959	44	0	0
T17	0	751	0	0
T20	105790	9407	0	0
T21	59232	412	0	0
T22	38162	0	0	0
T23	174447	3486	0	0
T24	159001	3031	0	0
T25	853367	0	0	0
T26	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2759140	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2759140	0	0
T1	271477	24745	0	0
T2	669062	11731	0	0
T3	33053	332	0	0
T15	3959	30	0	0
T17	0	751	0	0
T20	105790	3311	0	0
T21	59232	419	0	0
T22	38162	0	0	0
T23	174447	1330	0	0
T24	159001	2622	0	0
T25	853367	0	0	0
T26	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1571005	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1571005	0	0
T1	271477	31659	0	0
T2	669062	91	0	0
T3	33053	373	0	0
T15	3959	79	0	0
T17	0	1073	0	0
T20	105790	9130	0	0
T21	59232	512	0	0
T22	38162	0	0	0
T23	174447	2385	0	0
T24	159001	310	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	2952401	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	2952401	0	0
T1	271477	33371	0	0
T2	669062	9931	0	0
T3	33053	312	0	0
T15	3959	39	0	0
T17	0	1073	0	0
T20	105790	5241	0	0
T21	59232	535	0	0
T22	38162	0	0	0
T23	174447	419	0	0
T24	159001	744	0	0
T25	853367	0	0	0
T26	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	1576914	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	1576914	0	0
T1	271477	25712	0	0
T2	669062	94	0	0
T3	33053	294	0	0
T15	3959	45	0	0
T17	0	976	0	0
T20	105790	10713	0	0
T21	59232	476	0	0
T22	38162	0	0	0
T23	174447	1119	0	0
T24	159001	617	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	311526219	3000368	0	0
DepthKnown_A	311526219	311406515	0	0
RvalidKnown_A	311526219	311406515	0	0
WreadyKnown_A	311526219	311406515	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	3000368	0	0
T1	271477	31496	0	0
T2	669062	7636	0	0
T3	33053	236	0	0
T15	3959	15	0	0
T17	0	976	0	0
T20	105790	3219	0	0
T21	59232	442	0	0
T22	38162	0	0	0
T23	174447	1010	0	0
T24	159001	509	0	0
T25	853367	0	0	0
T26	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311526219	311406515	0	0
T1	271477	271473	0	0
T2	669062	669005	0	0
T3	33053	33047	0	0
T15	3959	3912	0	0
T20	105790	105783	0	0
T21	59232	59218	0	0
T22	38162	38103	0	0
T23	174447	174424	0	0
T24	159001	158984	0	0
T25	853367	853335	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0