Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1599429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251235

1

T1

16

T2

7

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624743	1			T1	45		T2	29		T3	26
values[0x0]	600143	1			T1	37		T2	6		T3	9
values[0x1]	625778	1			T1	50		T2	51		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610830

1

T1

42

T2

36

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6669	1			T2	1		T4	4		T21	1
valid_sources[0x01]	7180	1			T4	3		T18	12		T22	3
valid_sources[0x02]	6970	1			T4	2		T22	3		T17	1
valid_sources[0x03]	7181	1			T4	5		T22	2		T17	1
valid_sources[0x04]	6577	1			T4	3		T18	11		T21	2
valid_sources[0x05]	7922	1			T2	6		T4	2		T18	18
valid_sources[0x06]	7232	1			T4	4		T22	3		T17	1
valid_sources[0x07]	7999	1			T4	8		T18	9		T19	1
valid_sources[0x08]	7596	1			T4	1		T18	16		T22	3
valid_sources[0x09]	7687	1			T1	2		T4	2		T21	1
valid_sources[0x0a]	6380	1			T4	2		T22	3		T24	19
valid_sources[0x0b]	7402	1			T4	1		T18	14		T22	2
valid_sources[0x0c]	8097	1			T3	2		T4	1		T22	3
valid_sources[0x0d]	8047	1			T4	5		T22	3		T17	3
valid_sources[0x0e]	7152	1			T2	5		T4	2		T21	2
valid_sources[0x0f]	6828	1			T1	1		T3	5		T4	3
valid_sources[0x10]	6991	1			T4	4		T22	3		T24	25
valid_sources[0x11]	8509	1			T4	5		T21	3		T22	3
valid_sources[0x12]	6761	1			T4	3		T22	3		T24	11
valid_sources[0x13]	7287	1			T4	1		T22	3		T24	27
valid_sources[0x14]	6901	1			T3	1		T4	1		T18	19
valid_sources[0x15]	7144	1			T1	7		T2	7		T4	7
valid_sources[0x16]	7522	1			T3	1		T4	2		T21	1
valid_sources[0x17]	6580	1			T1	2		T2	1		T4	2
valid_sources[0x18]	7376	1			T4	1		T18	9		T22	3
valid_sources[0x19]	7006	1			T1	1		T4	2		T18	14
valid_sources[0x1a]	6688	1			T3	3		T22	3		T24	8
valid_sources[0x1b]	6321	1			T3	1		T4	9		T21	1
valid_sources[0x1c]	6797	1			T1	3		T4	4		T21	1
valid_sources[0x1d]	7210	1			T4	1		T18	18		T22	3
valid_sources[0x1e]	7487	1			T4	5		T18	17		T22	3
valid_sources[0x1f]	7145	1			T4	1		T22	3		T26	11
valid_sources[0x20]	6494	1			T4	5		T21	3		T22	3
valid_sources[0x21]	7425	1			T4	3		T18	18		T22	3
valid_sources[0x22]	6866	1			T4	4		T22	2		T25	1
valid_sources[0x23]	7242	1			T4	2		T18	21		T21	1
valid_sources[0x24]	6459	1			T2	1		T4	3		T18	8
valid_sources[0x25]	6834	1			T4	2		T22	3		T24	15
valid_sources[0x26]	7342	1			T4	4		T18	38		T22	3
valid_sources[0x27]	6743	1			T3	6		T4	3		T21	1
valid_sources[0x28]	7351	1			T1	2		T4	2		T21	3
valid_sources[0x29]	7047	1			T4	2		T22	1		T24	12
valid_sources[0x2a]	7426	1			T4	4		T22	4		T26	2
valid_sources[0x2b]	8860	1			T4	2		T18	13		T21	6
valid_sources[0x2c]	6652	1			T4	2		T21	2		T22	3
valid_sources[0x2d]	7936	1			T2	3		T4	1		T18	16
valid_sources[0x2e]	7027	1			T2	2		T4	1		T19	9
valid_sources[0x2f]	7341	1			T4	5		T21	1		T22	2
valid_sources[0x30]	7130	1			T2	1		T4	2		T18	11
valid_sources[0x31]	6857	1			T4	3		T22	3		T25	1
valid_sources[0x32]	6512	1			T1	1		T3	1		T4	3
valid_sources[0x33]	7471	1			T2	1		T4	3		T18	16
valid_sources[0x34]	6576	1			T2	1		T4	5		T18	16
valid_sources[0x35]	8343	1			T1	5		T3	1		T4	1
valid_sources[0x36]	7036	1			T4	6		T21	1		T22	3
valid_sources[0x37]	7879	1			T1	1		T4	4		T22	3
valid_sources[0x38]	7840	1			T1	3		T4	2		T21	4
valid_sources[0x39]	7157	1			T4	8		T18	13		T19	8
valid_sources[0x3a]	7136	1			T4	2		T22	3		T26	5
valid_sources[0x3b]	6804	1			T4	5		T18	18		T19	7
valid_sources[0x3c]	7127	1			T3	1		T4	3		T22	2
valid_sources[0x3d]	7903	1			T4	3		T21	2		T22	2
valid_sources[0x3e]	6657	1			T1	1		T4	2		T18	15
valid_sources[0x3f]	7446	1			T4	3		T21	2		T22	2
valid_sources[0x40]	6463	1			T18	21		T22	3		T24	33
valid_sources[0x41]	6837	1			T4	3		T18	9		T21	1
valid_sources[0x42]	7217	1			T4	2		T22	3		T53	1
valid_sources[0x43]	6688	1			T4	1		T18	16		T19	5
valid_sources[0x44]	6479	1			T22	2		T24	8		T17	5
valid_sources[0x45]	7814	1			T4	4		T22	3		T24	10
valid_sources[0x46]	6925	1			T4	4		T18	17		T22	3
valid_sources[0x47]	7255	1			T22	3		T24	19		T25	1
valid_sources[0x48]	8241	1			T1	1		T2	2		T4	3
valid_sources[0x49]	7762	1			T1	1		T3	1		T4	6
valid_sources[0x4a]	6757	1			T4	6		T21	2		T22	3
valid_sources[0x4b]	7998	1			T4	3		T18	24		T22	3
valid_sources[0x4c]	7705	1			T2	2		T4	2		T21	2
valid_sources[0x4d]	6952	1			T4	10		T21	3		T22	3
valid_sources[0x4e]	6461	1			T4	5		T22	3		T24	10
valid_sources[0x4f]	6816	1			T4	1		T22	3		T17	1
valid_sources[0x50]	6435	1			T2	1		T3	2		T4	1
valid_sources[0x51]	7734	1			T4	2		T18	20		T20	100
valid_sources[0x52]	6225	1			T4	2		T22	2		T53	1
valid_sources[0x53]	6746	1			T2	1		T4	4		T19	7
valid_sources[0x54]	8725	1			T2	15		T3	2		T4	4
valid_sources[0x55]	7255	1			T1	1		T4	5		T21	1
valid_sources[0x56]	7132	1			T4	1		T21	2		T22	1
valid_sources[0x57]	7575	1			T4	1		T18	12		T22	3
valid_sources[0x58]	8243	1			T1	1		T4	2		T22	4
valid_sources[0x59]	7128	1			T4	3		T21	1		T22	2
valid_sources[0x5a]	8528	1			T4	1		T21	3		T22	3
valid_sources[0x5b]	6905	1			T3	1		T4	9		T22	3
valid_sources[0x5c]	6635	1			T4	3		T19	3		T22	5
valid_sources[0x5d]	7235	1			T1	2		T4	5		T21	1
valid_sources[0x5e]	8118	1			T4	2		T22	2		T24	10
valid_sources[0x5f]	7336	1			T3	4		T4	4		T18	20
valid_sources[0x60]	7384	1			T4	6		T18	6		T21	4
valid_sources[0x61]	6390	1			T4	5		T21	2		T22	3
valid_sources[0x62]	7092	1			T1	5		T4	2		T22	2
valid_sources[0x63]	8124	1			T4	2		T21	1		T22	3
valid_sources[0x64]	7103	1			T2	2		T4	1		T19	1
valid_sources[0x65]	7548	1			T4	2		T18	19		T22	2
valid_sources[0x66]	7530	1			T4	1		T18	9		T21	1
valid_sources[0x67]	8012	1			T4	5		T18	7		T21	1
valid_sources[0x68]	6721	1			T4	4		T21	2		T22	3
valid_sources[0x69]	7920	1			T1	5		T4	1		T18	30
valid_sources[0x6a]	7021	1			T1	2		T4	2		T18	11
valid_sources[0x6b]	6984	1			T4	7		T18	11		T19	6
valid_sources[0x6c]	6384	1			T1	4		T4	3		T19	1
valid_sources[0x6d]	6778	1			T4	6		T22	2		T24	26
valid_sources[0x6e]	7595	1			T1	4		T4	1		T21	2
valid_sources[0x6f]	6943	1			T4	5		T18	16		T22	4
valid_sources[0x70]	7347	1			T2	1		T4	5		T21	2
valid_sources[0x71]	8544	1			T4	1		T18	30		T19	6
valid_sources[0x72]	6848	1			T3	1		T4	7		T22	3
valid_sources[0x73]	7360	1			T1	1		T18	20		T22	2
valid_sources[0x74]	7313	1			T4	1		T21	2		T22	3
valid_sources[0x75]	6972	1			T4	3		T21	1		T22	3
valid_sources[0x76]	8042	1			T4	5		T22	3		T17	1
valid_sources[0x77]	6977	1			T4	4		T18	29		T22	2
valid_sources[0x78]	9498	1			T18	4		T22	3		T25	1
valid_sources[0x79]	7186	1			T1	1		T4	3		T21	1
valid_sources[0x7a]	6424	1			T3	2		T4	2		T18	14
valid_sources[0x7b]	8092	1			T4	4		T18	5		T21	1
valid_sources[0x7c]	7848	1			T4	3		T18	10		T21	1
valid_sources[0x7d]	7002	1			T2	3		T4	1		T18	9
valid_sources[0x7e]	6290	1			T1	1		T4	2		T22	3
valid_sources[0x7f]	7419	1			T3	2		T4	1		T18	6
valid_sources[0x80]	6416	1			T2	2		T3	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26505

1

T1

1

T2

3

T3

2

values[0x0]

all_enables

biggest_size

198315

1

T1

13

T2

3

T3

3

values[0x1]

all_enables

biggest_size

26415

1

T1

2

T2

1

T3

1