Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	354094486	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354094486	0	0
T1	21784	648	0	0
T2	2197440	30604	0	0
T3	1397816	36747	0	0
T4	28591360	662368	0	0
T17	0	4730	0	0
T18	3229352	47348	0	0
T19	44744	605	0	0
T20	35952	982	0	0
T21	10781400	202569	0	0
T22	37174480	544312	0	0
T23	5418392	168073	0	0
T24	0	3414	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21784	20888	0	0
T2	2197440	2195480	0	0
T3	1397816	1397200	0	0
T4	28591360	28587888	0	0
T18	3229352	3227616	0	0
T19	44744	39760	0	0
T20	35952	34384	0	0
T21	10781400	10778880	0	0
T22	37174480	37170840	0	0
T23	5418392	5415984	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21784	20888	0	0
T2	2197440	2195480	0	0
T3	1397816	1397200	0	0
T4	28591360	28587888	0	0
T18	3229352	3227616	0	0
T19	44744	39760	0	0
T20	35952	34384	0	0
T21	10781400	10778880	0	0
T22	37174480	37170840	0	0
T23	5418392	5415984	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21784	20888	0	0
T2	2197440	2195480	0	0
T3	1397816	1397200	0	0
T4	28591360	28587888	0	0
T18	3229352	3227616	0	0
T19	44744	39760	0	0
T20	35952	34384	0	0
T21	10781400	10778880	0	0
T22	37174480	37170840	0	0
T23	5418392	5415984	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	131444382	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	131444382	0	0
T1	389	252	0	0
T2	39240	14008	0	0
T3	24961	15019	0	0
T4	510560	264785	0	0
T18	57667	11665	0	0
T19	799	233	0	0
T20	642	382	0	0
T21	192525	100619	0	0
T22	663830	3294	0	0
T23	96757	95159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	92666353	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	92666353	0	0
T1	389	132	0	0
T2	39240	4673	0	0
T3	24961	7247	0	0
T4	510560	148919	0	0
T18	57667	12015	0	0
T19	799	124	0	0
T20	642	200	0	0
T21	192525	19318	0	0
T22	663830	268862	0	0
T23	96757	36226	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1404405	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1404405	0	0
T1	389	7	0	0
T2	39240	225	0	0
T3	24961	339	0	0
T4	510560	3746	0	0
T17	0	1644	0	0
T18	57667	426	0	0
T19	799	2	0	0
T20	642	5	0	0
T21	192525	4992	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2645251	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2645251	0	0
T1	389	7	0	0
T2	39240	145	0	0
T3	24961	292	0	0
T4	510560	4093	0	0
T17	0	625	0	0
T18	57667	438	0	0
T19	799	2	0	0
T20	642	5	0	0
T21	192525	242	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1418671	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1418671	0	0
T1	389	4	0	0
T2	39240	387	0	0
T3	24961	362	0	0
T4	510560	4374	0	0
T18	57667	319	0	0
T19	799	4	0	0
T20	642	6	0	0
T21	192525	2472	0	0
T22	663830	0	0	0
T23	96757	18	0	0
T24	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	4166516	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	4166516	0	0
T1	389	4	0	0
T2	39240	158	0	0
T3	24961	378	0	0
T4	510560	4523	0	0
T18	57667	287	0	0
T19	799	4	0	0
T20	642	6	0	0
T21	192525	1377	0	0
T22	663830	0	0	0
T23	96757	1024	0	0
T24	0	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1413962	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1413962	0	0
T1	389	5	0	0
T2	39240	301	0	0
T3	24961	269	0	0
T4	510560	4444	0	0
T18	57667	450	0	0
T19	799	2	0	0
T20	642	8	0	0
T21	192525	1868	0	0
T22	663830	0	0	0
T23	96757	8	0	0
T24	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2687870	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2687870	0	0
T1	389	5	0	0
T2	39240	107	0	0
T3	24961	279	0	0
T4	510560	4470	0	0
T18	57667	390	0	0
T19	799	2	0	0
T20	642	8	0	0
T21	192525	418	0	0
T22	663830	0	0	0
T23	96757	1503	0	0
T24	0	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1414245	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1414245	0	0
T1	389	3	0	0
T2	39240	301	0	0
T3	24961	289	0	0
T4	510560	6395	0	0
T18	57667	372	0	0
T19	799	3	0	0
T20	642	14	0	0
T21	192525	3466	0	0
T22	663830	0	0	0
T23	96757	11	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3184296	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3184296	0	0
T1	389	3	0	0
T2	39240	124	0	0
T3	24961	324	0	0
T4	510560	6778	0	0
T18	57667	416	0	0
T19	799	3	0	0
T20	642	14	0	0
T21	192525	1546	0	0
T22	663830	0	0	0
T23	96757	1331	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1378746	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1378746	0	0
T1	389	2	0	0
T2	39240	299	0	0
T3	24961	251	0	0
T4	510560	4244	0	0
T18	57667	517	0	0
T19	799	5	0	0
T20	642	3	0	0
T21	192525	1067	0	0
T22	663830	0	0	0
T23	96757	17	0	0
T24	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2880643	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2880643	0	0
T1	389	2	0	0
T2	39240	111	0	0
T3	24961	225	0	0
T4	510560	4512	0	0
T18	57667	535	0	0
T19	799	5	0	0
T20	642	3	0	0
T21	192525	5	0	0
T22	663830	0	0	0
T23	96757	2302	0	0
T24	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1428719	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1428719	0	0
T1	389	7	0	0
T2	39240	236	0	0
T3	24961	232	0	0
T4	510560	4652	0	0
T18	57667	329	0	0
T19	799	4	0	0
T20	642	6	0	0
T21	192525	929	0	0
T22	663830	0	0	0
T23	96757	17	0	0
T24	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3319809	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3319809	0	0
T1	389	7	0	0
T2	39240	103	0	0
T3	24961	271	0	0
T4	510560	4713	0	0
T18	57667	339	0	0
T19	799	4	0	0
T20	642	6	0	0
T21	192525	317	0	0
T22	663830	0	0	0
T23	96757	2400	0	0
T24	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1381692	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1381692	0	0
T1	389	7	0	0
T2	39240	246	0	0
T3	24961	242	0	0
T4	510560	4809	0	0
T18	57667	447	0	0
T19	799	5	0	0
T20	642	4	0	0
T21	192525	1508	0	0
T22	663830	0	0	0
T23	96757	4	0	0
T24	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3135507	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3135507	0	0
T1	389	7	0	0
T2	39240	147	0	0
T3	24961	235	0	0
T4	510560	5130	0	0
T18	57667	464	0	0
T19	799	5	0	0
T20	642	4	0	0
T21	192525	827	0	0
T22	663830	0	0	0
T23	96757	1633	0	0
T24	0	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1436508	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1436508	0	0
T1	389	3	0	0
T2	39240	335	0	0
T3	24961	296	0	0
T4	510560	4634	0	0
T18	57667	455	0	0
T19	799	5	0	0
T20	642	8	0	0
T21	192525	2232	0	0
T22	663830	0	0	0
T23	96757	18	0	0
T24	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3940568	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3940568	0	0
T1	389	3	0	0
T2	39240	149	0	0
T3	24961	273	0	0
T4	510560	4657	0	0
T18	57667	483	0	0
T19	799	5	0	0
T20	642	8	0	0
T21	192525	333	0	0
T22	663830	0	0	0
T23	96757	2637	0	0
T24	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1483525	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1483525	0	0
T1	389	3	0	0
T2	39240	280	0	0
T3	24961	309	0	0
T4	510560	4345	0	0
T18	57667	337	0	0
T19	799	8	0	0
T20	642	4	0	0
T21	192525	3946	0	0
T22	663830	943	0	0
T23	96757	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3656677	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3656677	0	0
T1	389	3	0	0
T2	39240	118	0	0
T3	24961	304	0	0
T4	510560	4645	0	0
T18	57667	499	0	0
T19	799	8	0	0
T20	642	4	0	0
T21	192525	1217	0	0
T22	663830	74525	0	0
T23	96757	1985	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1378116	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1378116	0	0
T1	389	4	0	0
T2	39240	476	0	0
T3	24961	238	0	0
T4	510560	4688	0	0
T18	57667	429	0	0
T19	799	4	0	0
T20	642	12	0	0
T21	192525	2047	0	0
T22	663830	1204	0	0
T23	96757	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3073940	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3073940	0	0
T1	389	4	0	0
T2	39240	213	0	0
T3	24961	264	0	0
T4	510560	4786	0	0
T18	57667	486	0	0
T19	799	4	0	0
T20	642	12	0	0
T21	192525	898	0	0
T22	663830	102064	0	0
T23	96757	1314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1418800	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1418800	0	0
T1	389	9	0	0
T2	39240	282	0	0
T3	24961	274	0	0
T4	510560	4291	0	0
T18	57667	484	0	0
T19	799	4	0	0
T20	642	7	0	0
T21	192525	1182	0	0
T22	663830	0	0	0
T23	96757	50	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3456593	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3456593	0	0
T1	389	9	0	0
T2	39240	83	0	0
T3	24961	270	0	0
T4	510560	4685	0	0
T18	57667	451	0	0
T19	799	4	0	0
T20	642	7	0	0
T21	192525	527	0	0
T22	663830	0	0	0
T23	96757	2928	0	0
T24	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1393719	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1393719	0	0
T1	389	9	0	0
T2	39240	304	0	0
T3	24961	255	0	0
T4	510560	4233	0	0
T18	57667	484	0	0
T19	799	4	0	0
T20	642	8	0	0
T21	192525	4023	0	0
T22	663830	0	0	0
T23	96757	42	0	0
T24	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3807535	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3807535	0	0
T1	389	9	0	0
T2	39240	142	0	0
T3	24961	269	0	0
T4	510560	4294	0	0
T18	57667	507	0	0
T19	799	4	0	0
T20	642	8	0	0
T21	192525	536	0	0
T22	663830	0	0	0
T23	96757	2080	0	0
T24	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1412719	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1412719	0	0
T1	389	4	0	0
T2	39240	312	0	0
T3	24961	289	0	0
T4	510560	4425	0	0
T18	57667	501	0	0
T19	799	4	0	0
T20	642	12	0	0
T21	192525	1588	0	0
T22	663830	0	0	0
T23	96757	20	0	0
T24	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2621173	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2621173	0	0
T1	389	4	0	0
T2	39240	153	0	0
T3	24961	268	0	0
T4	510560	4541	0	0
T18	57667	503	0	0
T19	799	4	0	0
T20	642	12	0	0
T21	192525	588	0	0
T22	663830	0	0	0
T23	96757	1468	0	0
T24	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1423600	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1423600	0	0
T1	389	6	0	0
T2	39240	310	0	0
T3	24961	345	0	0
T4	510560	4398	0	0
T18	57667	432	0	0
T19	799	4	0	0
T20	642	11	0	0
T21	192525	712	0	0
T22	663830	0	0	0
T23	96757	11	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3560263	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3560263	0	0
T1	389	6	0	0
T2	39240	142	0	0
T3	24961	344	0	0
T4	510560	4772	0	0
T18	57667	587	0	0
T19	799	4	0	0
T20	642	11	0	0
T21	192525	2	0	0
T22	663830	0	0	0
T23	96757	1125	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1417443	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1417443	0	0
T1	389	6	0	0
T2	39240	387	0	0
T3	24961	218	0	0
T4	510560	4279	0	0
T18	57667	421	0	0
T19	799	2	0	0
T20	642	7	0	0
T21	192525	1062	0	0
T22	663830	0	0	0
T23	96757	10	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3284546	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3284546	0	0
T1	389	6	0	0
T2	39240	220	0	0
T3	24961	198	0	0
T4	510560	4583	0	0
T18	57667	420	0	0
T19	799	2	0	0
T20	642	7	0	0
T21	192525	2	0	0
T22	663830	0	0	0
T23	96757	331	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1458622	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1458622	0	0
T1	389	5	0	0
T2	39240	258	0	0
T3	24961	242	0	0
T4	510560	4221	0	0
T17	0	873	0	0
T18	57667	372	0	0
T19	799	7	0	0
T20	642	9	0	0
T21	192525	2232	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	4304865	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	4304865	0	0
T1	389	5	0	0
T2	39240	137	0	0
T3	24961	193	0	0
T4	510560	4301	0	0
T17	0	383	0	0
T18	57667	505	0	0
T19	799	7	0	0
T20	642	9	0	0
T21	192525	676	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1473525	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1473525	0	0
T1	389	8	0	0
T2	39240	354	0	0
T3	24961	251	0	0
T4	510560	3973	0	0
T18	57667	379	0	0
T19	799	7	0	0
T20	642	6	0	0
T21	192525	2179	0	0
T22	663830	0	0	0
T23	96757	20	0	0
T24	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3107289	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3107289	0	0
T1	389	8	0	0
T2	39240	112	0	0
T3	24961	268	0	0
T4	510560	4111	0	0
T18	57667	362	0	0
T19	799	7	0	0
T20	642	6	0	0
T21	192525	398	0	0
T22	663830	0	0	0
T23	96757	1329	0	0
T24	0	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1404256	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1404256	0	0
T1	389	4	0	0
T2	39240	256	0	0
T3	24961	173	0	0
T4	510560	4721	0	0
T18	57667	458	0	0
T19	799	3	0	0
T20	642	6	0	0
T21	192525	2685	0	0
T22	663830	0	0	0
T23	96757	17	0	0
T24	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3070011	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3070011	0	0
T1	389	4	0	0
T2	39240	107	0	0
T3	24961	190	0	0
T4	510560	4821	0	0
T18	57667	429	0	0
T19	799	3	0	0
T20	642	6	0	0
T21	192525	619	0	0
T22	663830	0	0	0
T23	96757	1398	0	0
T24	0	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1399535	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1399535	0	0
T1	389	6	0	0
T2	39240	320	0	0
T3	24961	260	0	0
T4	510560	6027	0	0
T18	57667	358	0	0
T19	799	1	0	0
T20	642	5	0	0
T21	192525	2270	0	0
T22	663830	0	0	0
T23	96757	2	0	0
T24	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3629898	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3629898	0	0
T1	389	6	0	0
T2	39240	111	0	0
T3	24961	264	0	0
T4	510560	6023	0	0
T18	57667	396	0	0
T19	799	1	0	0
T20	642	5	0	0
T21	192525	1544	0	0
T22	663830	0	0	0
T23	96757	85	0	0
T24	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1387338	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1387338	0	0
T1	389	2	0	0
T2	39240	325	0	0
T3	24961	273	0	0
T4	510560	4494	0	0
T18	57667	463	0	0
T19	799	9	0	0
T20	642	3	0	0
T21	192525	2949	0	0
T22	663830	0	0	0
T23	96757	20	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3526280	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3526280	0	0
T1	389	2	0	0
T2	39240	152	0	0
T3	24961	277	0	0
T4	510560	4584	0	0
T18	57667	430	0	0
T19	799	9	0	0
T20	642	3	0	0
T21	192525	1277	0	0
T22	663830	0	0	0
T23	96757	2499	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1409044	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1409044	0	0
T1	389	5	0	0
T2	39240	333	0	0
T3	24961	293	0	0
T4	510560	4571	0	0
T18	57667	488	0	0
T19	799	5	0	0
T20	642	11	0	0
T21	192525	2759	0	0
T22	663830	0	0	0
T23	96757	30	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3641143	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3641143	0	0
T1	389	5	0	0
T2	39240	102	0	0
T3	24961	305	0	0
T4	510560	4763	0	0
T18	57667	443	0	0
T19	799	5	0	0
T20	642	11	0	0
T21	192525	596	0	0
T22	663830	0	0	0
T23	96757	698	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1398407	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1398407	0	0
T1	389	1	0	0
T2	39240	274	0	0
T3	24961	271	0	0
T4	510560	3963	0	0
T18	57667	531	0	0
T19	799	8	0	0
T20	642	5	0	0
T21	192525	3351	0	0
T22	663830	0	0	0
T23	96757	8	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2555452	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2555452	0	0
T1	389	1	0	0
T2	39240	90	0	0
T3	24961	289	0	0
T4	510560	4231	0	0
T18	57667	466	0	0
T19	799	8	0	0
T20	642	5	0	0
T21	192525	1174	0	0
T22	663830	0	0	0
T23	96757	534	0	0
T24	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1439118	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1439118	0	0
T1	389	4	0	0
T2	39240	272	0	0
T3	24961	339	0	0
T4	510560	4200	0	0
T18	57667	485	0	0
T19	799	9	0	0
T20	642	6	0	0
T21	192525	2179	0	0
T22	663830	0	0	0
T23	96757	18	0	0
T24	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3712603	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3712603	0	0
T1	389	4	0	0
T2	39240	136	0	0
T3	24961	304	0	0
T4	510560	4531	0	0
T18	57667	408	0	0
T19	799	9	0	0
T20	642	6	0	0
T21	192525	1182	0	0
T22	663830	0	0	0
T23	96757	1731	0	0
T24	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1400378	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1400378	0	0
T1	389	5	0	0
T2	39240	364	0	0
T3	24961	246	0	0
T4	510560	4844	0	0
T18	57667	467	0	0
T19	799	3	0	0
T20	642	8	0	0
T21	192525	1352	0	0
T22	663830	0	0	0
T23	96757	18	0	0
T24	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	2937081	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	2937081	0	0
T1	389	5	0	0
T2	39240	120	0	0
T3	24961	232	0	0
T4	510560	4960	0	0
T18	57667	503	0	0
T19	799	3	0	0
T20	642	8	0	0
T21	192525	1024	0	0
T22	663830	0	0	0
T23	96757	951	0	0
T24	0	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1412607	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1412607	0	0
T1	389	2	0	0
T2	39240	383	0	0
T3	24961	238	0	0
T4	510560	4272	0	0
T18	57667	317	0	0
T19	799	7	0	0
T20	642	7	0	0
T21	192525	2181	0	0
T22	663830	0	0	0
T23	96757	13	0	0
T24	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3692133	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3692133	0	0
T1	389	2	0	0
T2	39240	145	0	0
T3	24961	288	0	0
T4	510560	4491	0	0
T18	57667	355	0	0
T19	799	7	0	0
T20	642	7	0	0
T21	192525	1540	0	0
T22	663830	0	0	0
T23	96757	1147	0	0
T24	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1424705	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1424705	0	0
T1	389	3	0	0
T2	39240	294	0	0
T3	24961	241	0	0
T4	510560	4130	0	0
T17	0	852	0	0
T18	57667	488	0	0
T19	799	2	0	0
T20	642	9	0	0
T21	192525	3468	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	3690502	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	3690502	0	0
T1	389	3	0	0
T2	39240	99	0	0
T3	24961	194	0	0
T4	510560	4499	0	0
T17	0	353	0	0
T18	57667	538	0	0
T19	799	2	0	0
T20	642	9	0	0
T21	192525	262	0	0
T22	663830	0	0	0
T23	96757	0	0	0
T24	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	1445169	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	1445169	0	0
T1	389	8	0	0
T2	39240	260	0	0
T3	24961	199	0	0
T4	510560	4293	0	0
T18	57667	450	0	0
T19	799	3	0	0
T20	642	10	0	0
T21	192525	2615	0	0
T22	663830	1147	0	0
T23	96757	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315643326	4437733	0	0
DepthKnown_A	315643326	315524267	0	0
RvalidKnown_A	315643326	315524267	0	0
WreadyKnown_A	315643326	315524267	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	4437733	0	0
T1	389	8	0	0
T2	39240	123	0	0
T3	24961	249	0	0
T4	510560	4501	0	0
T18	57667	369	0	0
T19	799	3	0	0
T20	642	10	0	0
T21	192525	191	0	0
T22	663830	92273	0	0
T23	96757	1793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315643326	315524267	0	0
T1	389	373	0	0
T2	39240	39205	0	0
T3	24961	24950	0	0
T4	510560	510498	0	0
T18	57667	57636	0	0
T19	799	710	0	0
T20	642	614	0	0
T21	192525	192480	0	0
T22	663830	663765	0	0
T23	96757	96714	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0