Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1683786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264468

1

T1

176

T2

18

T3

260

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	658687	1			T1	376		T2	23		T3	650
values[0x0]	629680	1			T1	415		T2	41		T3	639
values[0x1]	659887	1			T1	392		T2	43		T3	637

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

644062

1

T1

404

T2

29

T3

648

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7080	1			T21	1		T16	15		T18	2
valid_sources[0x01]	8113	1			T1	2		T20	1		T16	2
valid_sources[0x02]	7194	1			T1	4		T2	13		T20	1
valid_sources[0x03]	8021	1			T1	4		T3	53		T20	3
valid_sources[0x04]	7233	1			T1	11		T3	31		T16	17
valid_sources[0x05]	7264	1			T1	8		T20	3		T16	6
valid_sources[0x06]	8512	1			T1	6		T21	1		T16	8
valid_sources[0x07]	7845	1			T1	5		T16	15		T27	12
valid_sources[0x08]	7873	1			T1	6		T20	1		T17	1
valid_sources[0x09]	7659	1			T1	5		T20	1		T16	3
valid_sources[0x0a]	6709	1			T1	2		T16	8		T22	2
valid_sources[0x0b]	7253	1			T1	3		T16	12		T18	3
valid_sources[0x0c]	7593	1			T1	3		T2	12		T16	19
valid_sources[0x0d]	8673	1			T1	9		T16	1		T18	4
valid_sources[0x0e]	6806	1			T1	11		T16	6		T18	1
valid_sources[0x0f]	7665	1			T1	3		T21	1		T16	9
valid_sources[0x10]	7639	1			T1	5		T16	13		T22	3
valid_sources[0x11]	8789	1			T1	5		T16	5		T22	1
valid_sources[0x12]	7482	1			T1	6		T16	18		T17	1
valid_sources[0x13]	8130	1			T1	4		T21	1		T16	21
valid_sources[0x14]	7118	1			T1	9		T16	12		T22	1
valid_sources[0x15]	8254	1			T1	6		T3	69		T16	7
valid_sources[0x16]	6902	1			T1	3		T16	4		T18	1
valid_sources[0x17]	7768	1			T1	1		T20	2		T16	17
valid_sources[0x18]	8001	1			T1	5		T16	44		T17	1
valid_sources[0x19]	8136	1			T1	2		T20	1		T21	1
valid_sources[0x1a]	7553	1			T1	1		T20	1		T16	10
valid_sources[0x1b]	8032	1			T1	3		T16	21		T17	1
valid_sources[0x1c]	8486	1			T1	2		T20	1		T21	1
valid_sources[0x1d]	7166	1			T1	3		T16	11		T22	1
valid_sources[0x1e]	8070	1			T1	5		T20	1		T16	6
valid_sources[0x1f]	7265	1			T1	8		T16	7		T22	1
valid_sources[0x20]	9324	1			T1	6		T20	1		T16	14
valid_sources[0x21]	7738	1			T1	5		T21	2		T16	8
valid_sources[0x22]	7492	1			T1	9		T21	1		T16	18
valid_sources[0x23]	7264	1			T1	5		T3	54		T16	25
valid_sources[0x24]	7178	1			T1	4		T20	1		T16	11
valid_sources[0x25]	7799	1			T1	13		T21	1		T16	12
valid_sources[0x26]	7764	1			T1	9		T16	4		T18	3
valid_sources[0x27]	6931	1			T1	4		T19	1		T26	1
valid_sources[0x28]	7592	1			T1	4		T3	27		T16	14
valid_sources[0x29]	8150	1			T1	8		T20	1		T16	10
valid_sources[0x2a]	8282	1			T1	6		T16	7		T18	1
valid_sources[0x2b]	8057	1			T1	1		T21	1		T16	22
valid_sources[0x2c]	7816	1			T1	2		T3	116		T20	2
valid_sources[0x2d]	7324	1			T1	1		T20	1		T16	19
valid_sources[0x2e]	7115	1			T1	2		T3	15		T21	2
valid_sources[0x2f]	7504	1			T1	2		T3	20		T16	4
valid_sources[0x30]	8500	1			T1	3		T3	108		T16	12
valid_sources[0x31]	7290	1			T1	2		T21	1		T16	17
valid_sources[0x32]	7412	1			T1	3		T16	2		T17	1
valid_sources[0x33]	7775	1			T1	7		T20	2		T16	14
valid_sources[0x34]	8022	1			T1	5		T3	9		T20	1
valid_sources[0x35]	7574	1			T1	3		T2	37		T21	1
valid_sources[0x36]	7300	1			T1	3		T20	2		T21	2
valid_sources[0x37]	6848	1			T1	5		T16	5		T18	3
valid_sources[0x38]	8141	1			T1	1		T16	10		T27	13
valid_sources[0x39]	6995	1			T1	5		T3	32		T20	2
valid_sources[0x3a]	6876	1			T1	5		T3	17		T20	2
valid_sources[0x3b]	7219	1			T1	5		T3	13		T16	7
valid_sources[0x3c]	7420	1			T1	1		T16	19		T22	1
valid_sources[0x3d]	7417	1			T1	3		T20	1		T21	1
valid_sources[0x3e]	6963	1			T16	11		T17	1		T18	5
valid_sources[0x3f]	7098	1			T1	2		T20	1		T19	1
valid_sources[0x40]	7304	1			T1	1		T16	12		T18	2
valid_sources[0x41]	8647	1			T1	3		T16	12		T18	4
valid_sources[0x42]	7515	1			T1	7		T16	4		T22	1
valid_sources[0x43]	6653	1			T1	1		T21	1		T16	23
valid_sources[0x44]	7199	1			T1	7		T20	1		T21	1
valid_sources[0x45]	7187	1			T1	4		T21	2		T16	4
valid_sources[0x46]	8263	1			T1	5		T2	10		T20	1
valid_sources[0x47]	8282	1			T1	1		T21	1		T16	16
valid_sources[0x48]	6971	1			T1	5		T20	2		T21	1
valid_sources[0x49]	6915	1			T1	6		T21	1		T16	4
valid_sources[0x4a]	8775	1			T1	6		T16	18		T27	10
valid_sources[0x4b]	7075	1			T1	1		T20	1		T16	14
valid_sources[0x4c]	8914	1			T1	3		T16	13		T18	5
valid_sources[0x4d]	8527	1			T16	2		T18	2		T19	1
valid_sources[0x4e]	7163	1			T1	11		T20	3		T21	1
valid_sources[0x4f]	7482	1			T1	5		T3	9		T21	1
valid_sources[0x50]	7590	1			T1	6		T3	5		T16	3
valid_sources[0x51]	9198	1			T1	9		T16	9		T17	1
valid_sources[0x52]	7209	1			T1	9		T20	2		T16	9
valid_sources[0x53]	7745	1			T1	7		T16	24		T17	1
valid_sources[0x54]	7238	1			T1	6		T16	16		T22	2
valid_sources[0x55]	7020	1			T1	6		T20	2		T16	5
valid_sources[0x56]	6836	1			T1	1		T3	21		T16	12
valid_sources[0x57]	7030	1			T1	1		T21	1		T16	21
valid_sources[0x58]	6901	1			T1	4		T16	7		T17	1
valid_sources[0x59]	7079	1			T1	8		T21	1		T16	14
valid_sources[0x5a]	7192	1			T1	8		T2	5		T3	11
valid_sources[0x5b]	7206	1			T1	2		T16	13		T17	1
valid_sources[0x5c]	8661	1			T1	5		T3	97		T20	2
valid_sources[0x5d]	8069	1			T1	3		T20	1		T16	5
valid_sources[0x5e]	6955	1			T1	2		T16	21		T17	1
valid_sources[0x5f]	7290	1			T1	4		T20	1		T16	5
valid_sources[0x60]	7448	1			T1	7		T21	1		T16	18
valid_sources[0x61]	7717	1			T1	6		T21	1		T16	16
valid_sources[0x62]	9148	1			T1	1		T20	3		T16	8
valid_sources[0x63]	7206	1			T1	3		T3	110		T16	12
valid_sources[0x64]	7800	1			T1	8		T21	2		T16	16
valid_sources[0x65]	7221	1			T1	3		T16	15		T18	4
valid_sources[0x66]	6352	1			T20	1		T16	29		T22	2
valid_sources[0x67]	6642	1			T1	7		T21	1		T16	2
valid_sources[0x68]	7780	1			T1	2		T20	1		T16	6
valid_sources[0x69]	7851	1			T1	4		T16	9		T26	3
valid_sources[0x6a]	7605	1			T1	5		T16	15		T17	1
valid_sources[0x6b]	7341	1			T1	3		T3	92		T20	2
valid_sources[0x6c]	7447	1			T1	5		T16	2		T19	1
valid_sources[0x6d]	7893	1			T1	5		T16	12		T17	1
valid_sources[0x6e]	8732	1			T1	2		T16	18		T18	2
valid_sources[0x6f]	8081	1			T1	1		T21	1		T16	9
valid_sources[0x70]	6932	1			T1	7		T16	10		T17	1
valid_sources[0x71]	6785	1			T20	1		T16	9		T18	3
valid_sources[0x72]	6898	1			T1	8		T16	6		T19	2
valid_sources[0x73]	7467	1			T1	7		T20	2		T16	9
valid_sources[0x74]	7463	1			T1	9		T21	2		T16	4
valid_sources[0x75]	7848	1			T1	8		T16	17		T17	1
valid_sources[0x76]	7077	1			T1	6		T20	1		T16	13
valid_sources[0x77]	8091	1			T1	3		T20	1		T16	2
valid_sources[0x78]	8372	1			T1	6		T16	14		T19	1
valid_sources[0x79]	7076	1			T1	1		T20	3		T16	20
valid_sources[0x7a]	8429	1			T1	7		T20	1		T16	13
valid_sources[0x7b]	6964	1			T1	3		T16	5		T63	1
valid_sources[0x7c]	8376	1			T1	6		T16	3		T22	2
valid_sources[0x7d]	6912	1			T1	9		T21	2		T16	8
valid_sources[0x7e]	7700	1			T1	9		T16	11		T17	1
valid_sources[0x7f]	7967	1			T1	5		T3	93		T20	1
valid_sources[0x80]	6958	1			T1	8		T16	8		T18	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27905

1

T1

19

T2

2

T3

32

values[0x0]

all_enables

biggest_size

208530

1

T1

139

T2

13

T3

191

values[0x1]

all_enables

biggest_size

28033

1

T1

18

T2

3

T3

37