Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	329226556	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	329226556	0	0
T1	5695984	976303	0	0
T2	15568	524	0	0
T3	1806056	25759	0	0
T16	8499960	184626	0	0
T17	2541784	63436	0	0
T18	1034376	44349	0	0
T19	305704	10919	0	0
T20	34160	641	0	0
T21	239680	9854	0	0
T22	11056976	209584	0	0
T23	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5695984	5695704	0	0
T2	15568	15232	0	0
T3	1806056	1802248	0	0
T16	8499960	8499624	0	0
T17	2541784	2538088	0	0
T18	1034376	996520	0	0
T19	305704	301952	0	0
T20	34160	32312	0	0
T21	239680	236600	0	0
T22	11056976	11052608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5695984	5695704	0	0
T2	15568	15232	0	0
T3	1806056	1802248	0	0
T16	8499960	8499624	0	0
T17	2541784	2538088	0	0
T18	1034376	996520	0	0
T19	305704	301952	0	0
T20	34160	32312	0	0
T21	239680	236600	0	0
T22	11056976	11052608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5695984	5695704	0	0
T2	15568	15232	0	0
T3	1806056	1802248	0	0
T16	8499960	8499624	0	0
T17	2541784	2538088	0	0
T18	1034376	996520	0	0
T19	305704	301952	0	0
T20	34160	32312	0	0
T21	239680	236600	0	0
T22	11056976	11052608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	123439778	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	123439778	0	0
T1	101714	100137	0	0
T2	278	205	0	0
T3	32251	11991	0	0
T16	151785	147800	0	0
T17	45389	28181	0	0
T18	18471	17149	0	0
T19	5459	5075	0	0
T20	610	251	0	0
T21	4280	3827	0	0
T22	197446	95208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	84801219	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	84801219	0	0
T1	101714	435461	0	0
T2	278	107	0	0
T3	32251	3792	0	0
T16	151785	11719	0	0
T17	45389	11429	0	0
T18	18471	10232	0	0
T19	5459	2582	0	0
T20	610	130	0	0
T21	4280	2009	0	0
T22	197446	23397	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1385752	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1385752	0	0
T1	101714	195	0	0
T2	278	3	0	0
T3	32251	216	0	0
T16	151785	384	0	0
T17	45389	533	0	0
T18	18471	159	0	0
T19	5459	64	0	0
T20	610	8	0	0
T21	4280	67	0	0
T22	197446	1506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3372674	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3372674	0	0
T1	101714	14039	0	0
T2	278	3	0	0
T3	32251	60	0	0
T16	151785	89	0	0
T17	45389	448	0	0
T18	18471	159	0	0
T19	5459	64	0	0
T20	610	8	0	0
T21	4280	67	0	0
T22	197446	1646	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1374850	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1374850	0	0
T1	101714	227	0	0
T2	278	3	0	0
T3	32251	216	0	0
T16	151785	496	0	0
T17	45389	523	0	0
T18	18471	173	0	0
T19	5459	71	0	0
T20	610	5	0	0
T21	4280	88	0	0
T22	197446	3404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3033195	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3033195	0	0
T1	101714	18770	0	0
T2	278	3	0	0
T3	32251	61	0	0
T16	151785	803	0	0
T17	45389	453	0	0
T18	18471	173	0	0
T19	5459	71	0	0
T20	610	5	0	0
T21	4280	88	0	0
T22	197446	2337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1420640	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1420640	0	0
T1	101714	290	0	0
T2	278	3	0	0
T3	32251	316	0	0
T16	151785	484	0	0
T17	45389	519	0	0
T18	18471	380	0	0
T19	5459	49	0	0
T20	610	1	0	0
T21	4280	97	0	0
T22	197446	6663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2516650	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2516650	0	0
T1	101714	19157	0	0
T2	278	3	0	0
T3	32251	124	0	0
T16	151785	2073	0	0
T17	45389	439	0	0
T18	18471	380	0	0
T19	5459	49	0	0
T20	610	1	0	0
T21	4280	97	0	0
T22	197446	956	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1362943	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1362943	0	0
T1	101714	215	0	0
T2	278	3	0	0
T3	32251	273	0	0
T16	151785	455	0	0
T17	45389	508	0	0
T18	18471	441	0	0
T19	5459	46	0	0
T20	610	5	0	0
T21	4280	84	0	0
T22	197446	0	0	0
T23	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2992261	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2992261	0	0
T1	101714	16729	0	0
T2	278	3	0	0
T3	32251	70	0	0
T16	151785	496	0	0
T17	45389	416	0	0
T18	18471	441	0	0
T19	5459	46	0	0
T20	610	5	0	0
T21	4280	84	0	0
T22	197446	0	0	0
T23	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1384356	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1384356	0	0
T1	101714	182	0	0
T2	278	1	0	0
T3	32251	280	0	0
T16	151785	507	0	0
T17	45389	476	0	0
T18	18471	383	0	0
T19	5459	67	0	0
T20	610	5	0	0
T21	4280	78	0	0
T22	197446	1422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2961486	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2961486	0	0
T1	101714	14554	0	0
T2	278	1	0	0
T3	32251	106	0	0
T16	151785	458	0	0
T17	45389	336	0	0
T18	18471	383	0	0
T19	5459	67	0	0
T20	610	5	0	0
T21	4280	78	0	0
T22	197446	250	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1372102	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1372102	0	0
T1	101714	213	0	0
T2	278	4	0	0
T3	32251	212	0	0
T16	151785	525	0	0
T17	45389	422	0	0
T18	18471	447	0	0
T19	5459	58	0	0
T20	610	7	0	0
T21	4280	70	0	0
T22	197446	4394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3032450	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3032450	0	0
T1	101714	17717	0	0
T2	278	4	0	0
T3	32251	59	0	0
T16	151785	117	0	0
T17	45389	466	0	0
T18	18471	446	0	0
T19	5459	58	0	0
T20	610	7	0	0
T21	4280	70	0	0
T22	197446	1638	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1345848	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1345848	0	0
T1	101714	208	0	0
T2	278	1	0	0
T3	32251	240	0	0
T16	151785	541	0	0
T17	45389	455	0	0
T18	18471	411	0	0
T19	5459	59	0	0
T20	610	6	0	0
T21	4280	65	0	0
T22	197446	3559	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2990634	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2990634	0	0
T1	101714	19256	0	0
T2	278	1	0	0
T3	32251	107	0	0
T16	151785	117	0	0
T17	45389	410	0	0
T18	18471	410	0	0
T19	5459	59	0	0
T20	610	6	0	0
T21	4280	65	0	0
T22	197446	1145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1387519	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1387519	0	0
T1	101714	174	0	0
T2	278	4	0	0
T3	32251	232	0	0
T16	151785	464	0	0
T17	45389	527	0	0
T18	18471	439	0	0
T19	5459	65	0	0
T20	610	2	0	0
T21	4280	75	0	0
T22	197446	3201	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2710998	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2710998	0	0
T1	101714	18295	0	0
T2	278	4	0	0
T3	32251	119	0	0
T16	151785	1953	0	0
T17	45389	412	0	0
T18	18471	439	0	0
T19	5459	65	0	0
T20	610	2	0	0
T21	4280	75	0	0
T22	197446	1002	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1434668	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1434668	0	0
T1	101714	196	0	0
T2	278	5	0	0
T3	32251	323	0	0
T16	151785	524	0	0
T17	45389	430	0	0
T18	18471	372	0	0
T19	5459	49	0	0
T20	610	5	0	0
T21	4280	59	0	0
T22	197446	4819	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2726662	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2726662	0	0
T1	101714	15016	0	0
T2	278	5	0	0
T3	32251	152	0	0
T16	151785	429	0	0
T17	45389	430	0	0
T18	18471	371	0	0
T19	5459	49	0	0
T20	610	5	0	0
T21	4280	59	0	0
T22	197446	1878	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1356825	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1356825	0	0
T1	101714	217	0	0
T2	278	3	0	0
T3	32251	275	0	0
T16	151785	552	0	0
T17	45389	524	0	0
T18	18471	303	0	0
T19	5459	49	0	0
T20	610	6	0	0
T21	4280	77	0	0
T22	197446	1190	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3648057	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3648057	0	0
T1	101714	20765	0	0
T2	278	3	0	0
T3	32251	108	0	0
T16	151785	848	0	0
T17	45389	476	0	0
T18	18471	303	0	0
T19	5459	49	0	0
T20	610	6	0	0
T21	4280	77	0	0
T22	197446	946	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1384401	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1384401	0	0
T1	101714	183	0	0
T2	278	5	0	0
T3	32251	284	0	0
T16	151785	435	0	0
T17	45389	463	0	0
T18	18471	156	0	0
T19	5459	49	0	0
T20	610	3	0	0
T21	4280	76	0	0
T22	197446	2106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3866011	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3866011	0	0
T1	101714	14513	0	0
T2	278	5	0	0
T3	32251	116	0	0
T16	151785	581	0	0
T17	45389	392	0	0
T18	18471	156	0	0
T19	5459	49	0	0
T20	610	3	0	0
T21	4280	76	0	0
T22	197446	978	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1376319	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1376319	0	0
T1	101714	150	0	0
T2	278	6	0	0
T3	32251	230	0	0
T16	151785	439	0	0
T17	45389	423	0	0
T18	18471	189	0	0
T19	5459	53	0	0
T20	610	8	0	0
T21	4280	66	0	0
T22	197446	2185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3246512	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3246512	0	0
T1	101714	15688	0	0
T2	278	6	0	0
T3	32251	138	0	0
T16	151785	98	0	0
T17	45389	451	0	0
T18	18471	189	0	0
T19	5459	53	0	0
T20	610	8	0	0
T21	4280	66	0	0
T22	197446	451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1383840	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1383840	0	0
T1	101714	139	0	0
T2	278	7	0	0
T3	32251	245	0	0
T16	151785	501	0	0
T17	45389	490	0	0
T18	18471	162	0	0
T19	5459	58	0	0
T20	610	4	0	0
T21	4280	79	0	0
T22	197446	1228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3371317	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3371317	0	0
T1	101714	11816	0	0
T2	278	7	0	0
T3	32251	121	0	0
T16	151785	121	0	0
T17	45389	480	0	0
T18	18471	162	0	0
T19	5459	58	0	0
T20	610	4	0	0
T21	4280	79	0	0
T22	197446	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1395689	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1395689	0	0
T1	101714	222	0	0
T2	278	5	0	0
T3	32251	247	0	0
T16	151785	546	0	0
T17	45389	373	0	0
T18	18471	408	0	0
T19	5459	64	0	0
T20	610	2	0	0
T21	4280	51	0	0
T22	197446	876	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2701384	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2701384	0	0
T1	101714	16276	0	0
T2	278	5	0	0
T3	32251	75	0	0
T16	151785	280	0	0
T17	45389	390	0	0
T18	18471	408	0	0
T19	5459	64	0	0
T20	610	2	0	0
T21	4280	51	0	0
T22	197446	893	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1337321	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1337321	0	0
T1	101714	144	0	0
T2	278	3	0	0
T3	32251	210	0	0
T16	151785	470	0	0
T17	45389	404	0	0
T18	18471	393	0	0
T19	5459	69	0	0
T20	610	6	0	0
T21	4280	56	0	0
T22	197446	1039	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3009024	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3009024	0	0
T1	101714	9557	0	0
T2	278	3	0	0
T3	32251	90	0	0
T16	151785	107	0	0
T17	45389	399	0	0
T18	18471	393	0	0
T19	5459	69	0	0
T20	610	6	0	0
T21	4280	56	0	0
T22	197446	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1338287	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1338287	0	0
T1	101714	157	0	0
T2	278	5	0	0
T3	32251	287	0	0
T16	151785	504	0	0
T17	45389	356	0	0
T18	18471	428	0	0
T19	5459	56	0	0
T20	610	3	0	0
T21	4280	90	0	0
T22	197446	4159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3070641	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3070641	0	0
T1	101714	15003	0	0
T2	278	5	0	0
T3	32251	103	0	0
T16	151785	120	0	0
T17	45389	354	0	0
T18	18471	428	0	0
T19	5459	56	0	0
T20	610	3	0	0
T21	4280	90	0	0
T22	197446	992	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1374632	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1374632	0	0
T1	101714	209	0	0
T2	278	3	0	0
T3	32251	263	0	0
T16	151785	489	0	0
T17	45389	325	0	0
T18	18471	149	0	0
T19	5459	58	0	0
T20	610	6	0	0
T21	4280	87	0	0
T22	197446	4930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3080710	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3080710	0	0
T1	101714	16804	0	0
T2	278	3	0	0
T3	32251	59	0	0
T16	151785	102	0	0
T17	45389	321	0	0
T18	18471	149	0	0
T19	5459	58	0	0
T20	610	6	0	0
T21	4280	87	0	0
T22	197446	1527	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1355349	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1355349	0	0
T1	101714	270	0	0
T2	278	5	0	0
T3	32251	248	0	0
T16	151785	503	0	0
T17	45389	440	0	0
T18	18471	171	0	0
T19	5459	77	0	0
T20	610	4	0	0
T21	4280	74	0	0
T22	197446	2181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3062964	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3062964	0	0
T1	101714	19385	0	0
T2	278	5	0	0
T3	32251	134	0	0
T16	151785	113	0	0
T17	45389	509	0	0
T18	18471	171	0	0
T19	5459	77	0	0
T20	610	4	0	0
T21	4280	74	0	0
T22	197446	685	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1367003	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1367003	0	0
T1	101714	169	0	0
T2	278	2	0	0
T3	32251	286	0	0
T16	151785	511	0	0
T17	45389	366	0	0
T18	18471	345	0	0
T19	5459	66	0	0
T20	610	2	0	0
T21	4280	65	0	0
T22	197446	1046	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3390129	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3390129	0	0
T1	101714	12650	0	0
T2	278	2	0	0
T3	32251	119	0	0
T16	151785	128	0	0
T17	45389	347	0	0
T18	18471	345	0	0
T19	5459	66	0	0
T20	610	2	0	0
T21	4280	65	0	0
T22	197446	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1386557	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1386557	0	0
T1	101714	184	0	0
T2	278	7	0	0
T3	32251	345	0	0
T16	151785	566	0	0
T17	45389	419	0	0
T18	18471	403	0	0
T19	5459	51	0	0
T20	610	10	0	0
T21	4280	84	0	0
T22	197446	3217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2936874	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2936874	0	0
T1	101714	17175	0	0
T2	278	7	0	0
T3	32251	111	0	0
T16	151785	730	0	0
T17	45389	339	0	0
T18	18471	402	0	0
T19	5459	51	0	0
T20	610	10	0	0
T21	4280	84	0	0
T22	197446	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1372809	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1372809	0	0
T1	101714	176	0	0
T2	278	3	0	0
T3	32251	133	0	0
T16	151785	539	0	0
T17	45389	411	0	0
T18	18471	353	0	0
T19	5459	65	0	0
T20	610	4	0	0
T21	4280	71	0	0
T22	197446	2394	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3024927	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3024927	0	0
T1	101714	15044	0	0
T2	278	3	0	0
T3	32251	58	0	0
T16	151785	120	0	0
T17	45389	387	0	0
T18	18471	353	0	0
T19	5459	65	0	0
T20	610	4	0	0
T21	4280	71	0	0
T22	197446	353	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1356564	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1356564	0	0
T1	101714	210	0	0
T2	278	4	0	0
T3	32251	241	0	0
T16	151785	483	0	0
T17	45389	415	0	0
T18	18471	593	0	0
T19	5459	66	0	0
T20	610	8	0	0
T21	4280	75	0	0
T22	197446	1652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3127605	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3127605	0	0
T1	101714	16503	0	0
T2	278	4	0	0
T3	32251	69	0	0
T16	151785	110	0	0
T17	45389	370	0	0
T18	18471	593	0	0
T19	5459	66	0	0
T20	610	8	0	0
T21	4280	75	0	0
T22	197446	328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1393092	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1393092	0	0
T1	101714	209	0	0
T2	278	8	0	0
T3	32251	302	0	0
T16	151785	482	0	0
T17	45389	560	0	0
T18	18471	164	0	0
T19	5459	60	0	0
T20	610	5	0	0
T21	4280	89	0	0
T22	197446	2188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3731532	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3731532	0	0
T1	101714	16469	0	0
T2	278	8	0	0
T3	32251	140	0	0
T16	151785	273	0	0
T17	45389	490	0	0
T18	18471	164	0	0
T19	5459	60	0	0
T20	610	5	0	0
T21	4280	89	0	0
T22	197446	749	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1361192	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1361192	0	0
T1	101714	179	0	0
T2	278	3	0	0
T3	32251	271	0	0
T16	151785	500	0	0
T17	45389	548	0	0
T18	18471	157	0	0
T19	5459	62	0	0
T20	610	1	0	0
T21	4280	60	0	0
T22	197446	1524	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3396096	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3396096	0	0
T1	101714	13271	0	0
T2	278	3	0	0
T3	32251	157	0	0
T16	151785	114	0	0
T17	45389	442	0	0
T18	18471	157	0	0
T19	5459	62	0	0
T20	610	1	0	0
T21	4280	60	0	0
T22	197446	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1394590	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1394590	0	0
T1	101714	204	0	0
T2	278	4	0	0
T3	32251	253	0	0
T16	151785	535	0	0
T17	45389	549	0	0
T18	18471	184	0	0
T19	5459	60	0	0
T20	610	5	0	0
T21	4280	84	0	0
T22	197446	2507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2408693	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2408693	0	0
T1	101714	17139	0	0
T2	278	4	0	0
T3	32251	106	0	0
T16	151785	787	0	0
T17	45389	484	0	0
T18	18471	184	0	0
T19	5459	60	0	0
T20	610	5	0	0
T21	4280	84	0	0
T22	197446	1536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1371417	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1371417	0	0
T1	101714	158	0	0
T2	278	1	0	0
T3	32251	382	0	0
T16	151785	474	0	0
T17	45389	494	0	0
T18	18471	161	0	0
T19	5459	71	0	0
T20	610	5	0	0
T21	4280	65	0	0
T22	197446	2019	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	2912726	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	2912726	0	0
T1	101714	14371	0	0
T2	278	1	0	0
T3	32251	109	0	0
T16	151785	436	0	0
T17	45389	513	0	0
T18	18471	161	0	0
T19	5459	71	0	0
T20	610	5	0	0
T21	4280	65	0	0
T22	197446	1476	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	1375595	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	1375595	0	0
T1	101714	164	0	0
T2	278	5	0	0
T3	32251	358	0	0
T16	151785	481	0	0
T17	45389	448	0	0
T18	18471	562	0	0
T19	5459	69	0	0
T20	610	4	0	0
T21	4280	77	0	0
T22	197446	2173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	292022820	3513187	0	0
DepthKnown_A	292022820	291901070	0	0
RvalidKnown_A	292022820	291901070	0	0
WreadyKnown_A	292022820	291901070	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	3513187	0	0
T1	101714	19499	0	0
T2	278	5	0	0
T3	32251	137	0	0
T16	151785	114	0	0
T17	45389	471	0	0
T18	18471	562	0	0
T19	5459	69	0	0
T20	610	4	0	0
T21	4280	77	0	0
T22	197446	402	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292022820	291901070	0	0
T1	101714	101709	0	0
T2	278	272	0	0
T3	32251	32183	0	0
T16	151785	151779	0	0
T17	45389	45323	0	0
T18	18471	17795	0	0
T19	5459	5392	0	0
T20	610	577	0	0
T21	4280	4225	0	0
T22	197446	197368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0