Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1555792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244212

1

T1

114

T2

2464

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	610035	1			T1	341		T2	5911		T3	56
values[0x0]	579622	1			T1	270		T2	5933		T3	61
values[0x1]	610347	1			T1	315		T2	5904		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

594888

1

T1

320

T2

5859

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6731	1			T2	87		T4	19		T13	1
valid_sources[0x01]	6486	1			T2	27		T4	10		T15	1
valid_sources[0x02]	7006	1			T2	39		T4	72		T13	1
valid_sources[0x03]	7016	1			T2	57		T3	1		T4	59
valid_sources[0x04]	7638	1			T2	78		T4	19		T15	9
valid_sources[0x05]	6598	1			T2	66		T3	2		T4	51
valid_sources[0x06]	6633	1			T2	47		T3	2		T4	10
valid_sources[0x07]	6703	1			T2	54		T3	1		T4	10
valid_sources[0x08]	6868	1			T2	60		T4	210		T15	2
valid_sources[0x09]	6842	1			T2	84		T4	66		T13	1
valid_sources[0x0a]	7050	1			T2	18		T4	74		T13	1
valid_sources[0x0b]	6914	1			T2	27		T3	1		T4	35
valid_sources[0x0c]	6594	1			T2	108		T3	1		T4	21
valid_sources[0x0d]	7310	1			T2	67		T4	39		T13	1
valid_sources[0x0e]	7386	1			T1	79		T2	90		T4	121
valid_sources[0x0f]	6817	1			T2	122		T4	42		T13	1
valid_sources[0x10]	6370	1			T2	50		T3	1		T4	32
valid_sources[0x11]	7031	1			T2	42		T4	60		T13	3
valid_sources[0x12]	6925	1			T2	60		T3	3		T4	57
valid_sources[0x13]	6684	1			T2	53		T3	1		T4	25
valid_sources[0x14]	6516	1			T2	82		T4	22		T15	5
valid_sources[0x15]	7698	1			T2	84		T4	49		T15	6
valid_sources[0x16]	6908	1			T2	37		T4	14		T15	1
valid_sources[0x17]	6569	1			T2	128		T4	136		T13	1
valid_sources[0x18]	7542	1			T2	85		T3	1		T4	79
valid_sources[0x19]	7126	1			T2	51		T4	80		T15	13
valid_sources[0x1a]	7343	1			T2	35		T4	56		T13	1
valid_sources[0x1b]	7043	1			T2	12		T4	52		T15	6
valid_sources[0x1c]	6269	1			T2	29		T3	1		T4	108
valid_sources[0x1d]	6453	1			T2	14		T3	1		T4	34
valid_sources[0x1e]	6853	1			T2	47		T3	2		T4	140
valid_sources[0x1f]	7301	1			T2	30		T3	2		T4	16
valid_sources[0x20]	6957	1			T2	81		T4	90		T15	6
valid_sources[0x21]	6667	1			T2	47		T3	3		T4	100
valid_sources[0x22]	6926	1			T2	47		T4	223		T15	12
valid_sources[0x23]	7243	1			T2	69		T4	10		T16	8
valid_sources[0x24]	6526	1			T2	54		T4	31		T15	16
valid_sources[0x25]	7400	1			T2	115		T3	3		T4	11
valid_sources[0x26]	7419	1			T2	192		T3	2		T4	42
valid_sources[0x27]	6405	1			T2	11		T4	48		T15	7
valid_sources[0x28]	7466	1			T2	50		T4	70		T15	6
valid_sources[0x29]	6675	1			T2	125		T4	50		T15	8
valid_sources[0x2a]	6746	1			T2	72		T4	54		T15	33
valid_sources[0x2b]	7234	1			T2	65		T4	104		T14	6
valid_sources[0x2c]	7337	1			T2	101		T4	20		T17	3
valid_sources[0x2d]	7140	1			T2	66		T4	77		T13	1
valid_sources[0x2e]	6427	1			T2	63		T4	80		T15	16
valid_sources[0x2f]	7374	1			T2	85		T3	3		T4	20
valid_sources[0x30]	8531	1			T2	77		T4	669		T15	5
valid_sources[0x31]	7348	1			T2	70		T4	47		T13	1
valid_sources[0x32]	7426	1			T2	124		T3	6		T4	9
valid_sources[0x33]	8082	1			T2	63		T3	1		T4	39
valid_sources[0x34]	6720	1			T2	94		T4	47		T15	4
valid_sources[0x35]	7101	1			T2	259		T4	10		T13	1
valid_sources[0x36]	7125	1			T2	112		T4	104		T13	1
valid_sources[0x37]	6838	1			T2	79		T4	56		T15	18
valid_sources[0x38]	6554	1			T2	52		T4	44		T13	1
valid_sources[0x39]	7121	1			T2	61		T3	6		T4	22
valid_sources[0x3a]	8181	1			T2	72		T3	1		T4	380
valid_sources[0x3b]	7486	1			T2	65		T4	42		T13	2
valid_sources[0x3c]	6701	1			T2	74		T4	45		T17	6
valid_sources[0x3d]	6638	1			T2	68		T3	2		T4	99
valid_sources[0x3e]	7412	1			T2	40		T4	94		T13	1
valid_sources[0x3f]	6264	1			T2	50		T3	1		T4	54
valid_sources[0x40]	7336	1			T2	47		T4	49		T15	5
valid_sources[0x41]	6262	1			T2	36		T3	1		T4	77
valid_sources[0x42]	6684	1			T2	55		T4	61		T17	11
valid_sources[0x43]	6907	1			T2	105		T4	87		T15	10
valid_sources[0x44]	7577	1			T2	62		T4	48		T15	1
valid_sources[0x45]	8494	1			T2	27		T3	1		T4	89
valid_sources[0x46]	6898	1			T2	47		T3	3		T4	31
valid_sources[0x47]	6329	1			T2	31		T4	29		T15	2
valid_sources[0x48]	6940	1			T2	129		T4	53		T15	4
valid_sources[0x49]	7156	1			T2	213		T4	9		T13	1
valid_sources[0x4a]	6646	1			T2	55		T4	27		T15	22
valid_sources[0x4b]	7224	1			T2	128		T3	3		T4	61
valid_sources[0x4c]	6511	1			T2	45		T4	214		T15	4
valid_sources[0x4d]	8447	1			T2	30		T4	45		T15	6
valid_sources[0x4e]	6130	1			T2	45		T4	49		T15	3
valid_sources[0x4f]	6474	1			T2	46		T4	36		T15	13
valid_sources[0x50]	6963	1			T2	93		T3	4		T4	8
valid_sources[0x51]	6765	1			T2	61		T4	475		T15	14
valid_sources[0x52]	6923	1			T2	98		T3	1		T4	257
valid_sources[0x53]	7661	1			T2	93		T3	1		T4	281
valid_sources[0x54]	7174	1			T2	49		T4	69		T15	31
valid_sources[0x55]	7944	1			T2	63		T3	1		T4	8
valid_sources[0x56]	7244	1			T2	97		T4	81		T13	1
valid_sources[0x57]	7692	1			T2	28		T3	1		T4	103
valid_sources[0x58]	6847	1			T2	55		T4	89		T15	1
valid_sources[0x59]	6989	1			T2	113		T4	32		T13	1
valid_sources[0x5a]	7160	1			T2	74		T4	158		T15	8
valid_sources[0x5b]	7264	1			T2	102		T4	48		T16	1
valid_sources[0x5c]	7289	1			T2	65		T4	48		T15	2
valid_sources[0x5d]	6723	1			T2	118		T4	70		T17	6
valid_sources[0x5e]	7239	1			T2	94		T3	1		T4	87
valid_sources[0x5f]	7279	1			T2	57		T4	24		T13	1
valid_sources[0x60]	7078	1			T2	65		T4	41		T13	3
valid_sources[0x61]	6856	1			T2	79		T4	40		T13	1
valid_sources[0x62]	6430	1			T2	44		T3	1		T4	172
valid_sources[0x63]	7219	1			T2	40		T4	74		T15	23
valid_sources[0x64]	6635	1			T2	75		T3	3		T4	13
valid_sources[0x65]	8113	1			T2	69		T3	2		T4	70
valid_sources[0x66]	6666	1			T2	23		T4	197		T15	12
valid_sources[0x67]	7801	1			T2	23		T4	26		T15	9
valid_sources[0x68]	7430	1			T2	75		T4	405		T15	6
valid_sources[0x69]	6582	1			T2	56		T4	14		T15	1
valid_sources[0x6a]	7237	1			T2	75		T4	162		T13	1
valid_sources[0x6b]	7423	1			T2	49		T4	324		T17	9
valid_sources[0x6c]	6544	1			T2	16		T3	1		T4	30
valid_sources[0x6d]	7086	1			T2	63		T4	51		T17	4
valid_sources[0x6e]	6627	1			T2	94		T3	1		T4	39
valid_sources[0x6f]	7442	1			T2	82		T4	53		T13	1
valid_sources[0x70]	7096	1			T2	49		T4	75		T17	9
valid_sources[0x71]	6614	1			T2	84		T4	82		T13	1
valid_sources[0x72]	7324	1			T2	81		T3	5		T4	47
valid_sources[0x73]	7268	1			T2	62		T3	1		T4	114
valid_sources[0x74]	7840	1			T2	22		T4	69		T15	7
valid_sources[0x75]	7220	1			T2	72		T3	1		T4	110
valid_sources[0x76]	7715	1			T2	84		T3	4		T4	23
valid_sources[0x77]	6570	1			T2	90		T4	46		T17	9
valid_sources[0x78]	6874	1			T2	29		T4	81		T13	1
valid_sources[0x79]	6702	1			T2	49		T4	56		T15	2
valid_sources[0x7a]	6906	1			T2	32		T4	51		T13	1
valid_sources[0x7b]	6767	1			T2	126		T4	20		T15	12
valid_sources[0x7c]	6815	1			T2	51		T3	2		T4	52
valid_sources[0x7d]	6809	1			T2	107		T4	76		T15	12
valid_sources[0x7e]	6923	1			T2	88		T3	2		T4	37
valid_sources[0x7f]	7014	1			T2	87		T4	123		T15	13
valid_sources[0x80]	6909	1			T2	35		T4	47		T15	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26195

1

T1

13

T2

258

T3

3

values[0x0]

all_enables

biggest_size

192033

1

T1

92

T2

1991

T3

19

values[0x1]

all_enables

biggest_size

25984

1

T1

9

T2

215

T3

2