Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	332183454	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332183454	0	0
T1	120176	4543	0	0
T2	28649600	665665	0	0
T3	37576	850	0	0
T4	24362632	424729	0	0
T13	2246888	30470	0	0
T14	274904	6167	0	0
T15	2148496	39334	0	0
T16	12407080	306618	0	0
T17	226856	9194	0	0
T18	12075840	317062	0	0
T19	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	120176	117208	0	0
T2	28649600	28647416	0	0
T3	37576	34664	0	0
T4	24362632	24256848	0	0
T13	2246888	2244144	0	0
T14	274904	273896	0	0
T15	2148496	2069536	0	0
T16	12407080	12403832	0	0
T17	226856	223832	0	0
T18	12075840	12074160	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	120176	117208	0	0
T2	28649600	28647416	0	0
T3	37576	34664	0	0
T4	24362632	24256848	0	0
T13	2246888	2244144	0	0
T14	274904	273896	0	0
T15	2148496	2069536	0	0
T16	12407080	12403832	0	0
T17	226856	223832	0	0
T18	12075840	12074160	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	120176	117208	0	0
T2	28649600	28647416	0	0
T3	37576	34664	0	0
T4	24362632	24256848	0	0
T13	2246888	2244144	0	0
T14	274904	273896	0	0
T15	2148496	2069536	0	0
T16	12407080	12403832	0	0
T17	226856	223832	0	0
T18	12075840	12074160	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	122443063	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	122443063	0	0
T1	2146	1765	0	0
T2	511600	244507	0	0
T3	671	333	0	0
T4	435047	173414	0	0
T13	40123	14048	0	0
T14	4909	2408	0	0
T15	38366	17601	0	0
T16	221555	134038	0	0
T17	4051	3568	0	0
T18	215640	128421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	85143751	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	85143751	0	0
T1	2146	926	0	0
T2	511600	141728	0	0
T3	671	173	0	0
T4	435047	64917	0	0
T13	40123	4602	0	0
T14	4909	1272	0	0
T15	38366	5228	0	0
T16	221555	56750	0	0
T17	4051	1876	0	0
T18	215640	63124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1455566	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1455566	0	0
T1	2146	36	0	0
T2	511600	5084	0	0
T3	671	4	0	0
T4	435047	2332	0	0
T13	40123	353	0	0
T14	4909	37	0	0
T15	38366	335	0	0
T16	221555	3787	0	0
T17	4051	62	0	0
T18	215640	994	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2371687	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2371687	0	0
T1	2146	36	0	0
T2	511600	5060	0	0
T3	671	4	0	0
T4	435047	1022	0	0
T13	40123	125	0	0
T14	4909	50	0	0
T15	38366	148	0	0
T16	221555	3797	0	0
T17	4051	62	0	0
T18	215640	523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1554266	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1554266	0	0
T1	2146	30	0	0
T2	511600	4318	0	0
T3	671	5	0	0
T4	435047	2670	0	0
T13	40123	219	0	0
T14	4909	33	0	0
T15	38366	355	0	0
T16	221555	4624	0	0
T17	4051	68	0	0
T18	215640	4488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3359824	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3359824	0	0
T1	2146	30	0	0
T2	511600	4400	0	0
T3	671	5	0	0
T4	435047	1121	0	0
T13	40123	84	0	0
T14	4909	18	0	0
T15	38366	133	0	0
T16	221555	4850	0	0
T17	4051	68	0	0
T18	215640	2822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1510176	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1510176	0	0
T1	2146	33	0	0
T2	511600	4675	0	0
T3	671	6	0	0
T4	435047	6211	0	0
T13	40123	265	0	0
T14	4909	22	0	0
T15	38366	307	0	0
T16	221555	3850	0	0
T17	4051	92	0	0
T18	215640	1903	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3062557	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3062557	0	0
T1	2146	33	0	0
T2	511600	4806	0	0
T3	671	6	0	0
T4	435047	3478	0	0
T13	40123	119	0	0
T14	4909	41	0	0
T15	38366	194	0	0
T16	221555	3553	0	0
T17	4051	92	0	0
T18	215640	1639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1505953	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1505953	0	0
T1	2146	34	0	0
T2	511600	4262	0	0
T3	671	5	0	0
T4	435047	4322	0	0
T13	40123	248	0	0
T14	4909	20	0	0
T15	38366	879	0	0
T16	221555	3035	0	0
T17	4051	85	0	0
T18	215640	1779	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3479699	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3479699	0	0
T1	2146	34	0	0
T2	511600	5008	0	0
T3	671	5	0	0
T4	435047	1855	0	0
T13	40123	101	0	0
T14	4909	41	0	0
T15	38366	641	0	0
T16	221555	2236	0	0
T17	4051	85	0	0
T18	215640	1400	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1553333	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1553333	0	0
T1	2146	32	0	0
T2	511600	6693	0	0
T3	671	6	0	0
T4	435047	4216	0	0
T13	40123	425	0	0
T14	4909	18	0	0
T15	38366	379	0	0
T16	221555	2263	0	0
T17	4051	55	0	0
T18	215640	4495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3272590	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3272590	0	0
T1	2146	32	0	0
T2	511600	6858	0	0
T3	671	6	0	0
T4	435047	2923	0	0
T13	40123	116	0	0
T14	4909	34	0	0
T15	38366	171	0	0
T16	221555	2774	0	0
T17	4051	55	0	0
T18	215640	3460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1507890	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1507890	0	0
T1	2146	29	0	0
T2	511600	4743	0	0
T3	671	9	0	0
T4	435047	6455	0	0
T13	40123	374	0	0
T14	4909	23	0	0
T15	38366	363	0	0
T16	221555	2084	0	0
T17	4051	61	0	0
T18	215640	2859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3495211	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3495211	0	0
T1	2146	29	0	0
T2	511600	4916	0	0
T3	671	9	0	0
T4	435047	3035	0	0
T13	40123	128	0	0
T14	4909	17	0	0
T15	38366	206	0	0
T16	221555	1264	0	0
T17	4051	61	0	0
T18	215640	3922	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1453791	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1453791	0	0
T1	2146	31	0	0
T2	511600	8571	0	0
T3	671	7	0	0
T4	435047	8779	0	0
T13	40123	254	0	0
T14	4909	56	0	0
T15	38366	322	0	0
T16	221555	1467	0	0
T17	4051	78	0	0
T18	215640	1266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3799476	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3799476	0	0
T1	2146	31	0	0
T2	511600	8978	0	0
T3	671	7	0	0
T4	435047	4646	0	0
T13	40123	158	0	0
T14	4909	48	0	0
T15	38366	103	0	0
T16	221555	2250	0	0
T17	4051	78	0	0
T18	215640	2157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1530044	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1530044	0	0
T1	2146	41	0	0
T2	511600	6967	0	0
T3	671	4	0	0
T4	435047	4298	0	0
T13	40123	317	0	0
T14	4909	30	0	0
T15	38366	358	0	0
T16	221555	709	0	0
T17	4051	69	0	0
T18	215640	609	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3499116	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3499116	0	0
T1	2146	41	0	0
T2	511600	6792	0	0
T3	671	4	0	0
T4	435047	1801	0	0
T13	40123	123	0	0
T14	4909	15	0	0
T15	38366	132	0	0
T16	221555	452	0	0
T17	4051	69	0	0
T18	215640	1651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1484644	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1484644	0	0
T1	2146	25	0	0
T2	511600	4703	0	0
T3	671	6	0	0
T4	435047	5655	0	0
T13	40123	338	0	0
T14	4909	94	0	0
T15	38366	402	0	0
T16	221555	865	0	0
T17	4051	74	0	0
T18	215640	1510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3028242	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3028242	0	0
T1	2146	25	0	0
T2	511600	5023	0	0
T3	671	6	0	0
T4	435047	3444	0	0
T13	40123	129	0	0
T14	4909	76	0	0
T15	38366	162	0	0
T16	221555	631	0	0
T17	4051	74	0	0
T18	215640	1680	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1450486	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1450486	0	0
T1	2146	44	0	0
T2	511600	5083	0	0
T3	671	7	0	0
T4	435047	7922	0	0
T13	40123	370	0	0
T14	4909	60	0	0
T15	38366	416	0	0
T16	221555	2290	0	0
T17	4051	63	0	0
T18	215640	2003	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2794996	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2794996	0	0
T1	2146	44	0	0
T2	511600	5363	0	0
T3	671	7	0	0
T4	435047	4703	0	0
T13	40123	139	0	0
T14	4909	28	0	0
T15	38366	167	0	0
T16	221555	3629	0	0
T17	4051	63	0	0
T18	215640	1521	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1487340	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1487340	0	0
T1	2146	29	0	0
T2	511600	3201	0	0
T3	671	7	0	0
T4	435047	2791	0	0
T13	40123	391	0	0
T14	4909	20	0	0
T15	38366	341	0	0
T16	221555	2423	0	0
T17	4051	84	0	0
T18	215640	967	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2884469	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2884469	0	0
T1	2146	29	0	0
T2	511600	3167	0	0
T3	671	7	0	0
T4	435047	1223	0	0
T13	40123	138	0	0
T14	4909	50	0	0
T15	38366	147	0	0
T16	221555	2852	0	0
T17	4051	84	0	0
T18	215640	2140	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1535500	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1535500	0	0
T1	2146	37	0	0
T2	511600	2892	0	0
T3	671	3	0	0
T4	435047	4966	0	0
T13	40123	384	0	0
T14	4909	97	0	0
T15	38366	372	0	0
T16	221555	3464	0	0
T17	4051	51	0	0
T18	215640	1915	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3239095	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3239095	0	0
T1	2146	37	0	0
T2	511600	2969	0	0
T3	671	3	0	0
T4	435047	3043	0	0
T13	40123	209	0	0
T14	4909	93	0	0
T15	38366	189	0	0
T16	221555	3326	0	0
T17	4051	51	0	0
T18	215640	2188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1517876	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1517876	0	0
T1	2146	26	0	0
T2	511600	6337	0	0
T3	671	5	0	0
T4	435047	2732	0	0
T13	40123	349	0	0
T14	4909	42	0	0
T15	38366	452	0	0
T16	221555	2179	0	0
T17	4051	58	0	0
T18	215640	2336	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2834611	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2834611	0	0
T1	2146	26	0	0
T2	511600	6258	0	0
T3	671	5	0	0
T4	435047	1199	0	0
T13	40123	126	0	0
T14	4909	37	0	0
T15	38366	106	0	0
T16	221555	2382	0	0
T17	4051	58	0	0
T18	215640	1576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1438832	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1438832	0	0
T1	2146	43	0	0
T2	511600	8811	0	0
T3	671	7	0	0
T4	435047	4042	0	0
T13	40123	173	0	0
T14	4909	51	0	0
T15	38366	339	0	0
T16	221555	1380	0	0
T17	4051	58	0	0
T18	215640	2303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3187825	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3187825	0	0
T1	2146	43	0	0
T2	511600	8933	0	0
T3	671	7	0	0
T4	435047	1596	0	0
T13	40123	69	0	0
T14	4909	54	0	0
T15	38366	145	0	0
T16	221555	1755	0	0
T17	4051	58	0	0
T18	215640	2973	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1490051	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1490051	0	0
T1	2146	30	0	0
T2	511600	4895	0	0
T3	671	7	0	0
T4	435047	8022	0	0
T13	40123	295	0	0
T14	4909	47	0	0
T15	38366	434	0	0
T16	221555	2149	0	0
T17	4051	71	0	0
T18	215640	3359	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3347690	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3347690	0	0
T1	2146	30	0	0
T2	511600	4755	0	0
T3	671	7	0	0
T4	435047	3732	0	0
T13	40123	116	0	0
T14	4909	56	0	0
T15	38366	197	0	0
T16	221555	813	0	0
T17	4051	71	0	0
T18	215640	3700	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1475871	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1475871	0	0
T1	2146	39	0	0
T2	511600	5022	0	0
T3	671	4	0	0
T4	435047	3864	0	0
T13	40123	289	0	0
T14	4909	21	0	0
T15	38366	360	0	0
T16	221555	670	0	0
T17	4051	65	0	0
T18	215640	2624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3076985	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3076985	0	0
T1	2146	39	0	0
T2	511600	5580	0	0
T3	671	4	0	0
T4	435047	1974	0	0
T13	40123	116	0	0
T14	4909	34	0	0
T15	38366	160	0	0
T16	221555	1602	0	0
T17	4051	65	0	0
T18	215640	534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1456223	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1456223	0	0
T1	2146	32	0	0
T2	511600	4444	0	0
T3	671	5	0	0
T4	435047	4770	0	0
T13	40123	245	0	0
T14	4909	36	0	0
T15	38366	293	0	0
T16	221555	0	0	0
T17	4051	52	0	0
T18	215640	2889	0	0
T19	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3296312	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3296312	0	0
T1	2146	32	0	0
T2	511600	4661	0	0
T3	671	5	0	0
T4	435047	2262	0	0
T13	40123	133	0	0
T14	4909	38	0	0
T15	38366	130	0	0
T16	221555	0	0	0
T17	4051	52	0	0
T18	215640	3905	0	0
T19	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1461215	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1461215	0	0
T1	2146	35	0	0
T2	511600	5643	0	0
T3	671	8	0	0
T4	435047	6919	0	0
T13	40123	183	0	0
T14	4909	37	0	0
T15	38366	657	0	0
T16	221555	3524	0	0
T17	4051	72	0	0
T18	215640	3374	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2909522	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2909522	0	0
T1	2146	35	0	0
T2	511600	5549	0	0
T3	671	8	0	0
T4	435047	3148	0	0
T13	40123	89	0	0
T14	4909	38	0	0
T15	38366	286	0	0
T16	221555	2124	0	0
T17	4051	72	0	0
T18	215640	2817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1530041	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1530041	0	0
T1	2146	36	0	0
T2	511600	4759	0	0
T3	671	7	0	0
T4	435047	4056	0	0
T13	40123	320	0	0
T14	4909	66	0	0
T15	38366	308	0	0
T16	221555	1312	0	0
T17	4051	65	0	0
T18	215640	2506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3538361	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3538361	0	0
T1	2146	36	0	0
T2	511600	4651	0	0
T3	671	7	0	0
T4	435047	1795	0	0
T13	40123	140	0	0
T14	4909	65	0	0
T15	38366	165	0	0
T16	221555	1304	0	0
T17	4051	65	0	0
T18	215640	1677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1523925	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1523925	0	0
T1	2146	39	0	0
T2	511600	2956	0	0
T3	671	8	0	0
T4	435047	2677	0	0
T13	40123	238	0	0
T14	4909	39	0	0
T15	38366	365	0	0
T16	221555	1898	0	0
T17	4051	68	0	0
T18	215640	2270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2652233	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2652233	0	0
T1	2146	39	0	0
T2	511600	3000	0	0
T3	671	8	0	0
T4	435047	1238	0	0
T13	40123	102	0	0
T14	4909	58	0	0
T15	38366	109	0	0
T16	221555	2566	0	0
T17	4051	68	0	0
T18	215640	2094	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1492367	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1492367	0	0
T1	2146	33	0	0
T2	511600	5032	0	0
T3	671	11	0	0
T4	435047	4905	0	0
T13	40123	508	0	0
T14	4909	54	0	0
T15	38366	269	0	0
T16	221555	1466	0	0
T17	4051	72	0	0
T18	215640	3951	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2582557	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2582557	0	0
T1	2146	33	0	0
T2	511600	5170	0	0
T3	671	11	0	0
T4	435047	2048	0	0
T13	40123	218	0	0
T14	4909	44	0	0
T15	38366	79	0	0
T16	221555	1060	0	0
T17	4051	72	0	0
T18	215640	3774	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1535194	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1535194	0	0
T1	2146	24	0	0
T2	511600	3313	0	0
T3	671	4	0	0
T4	435047	2318	0	0
T13	40123	365	0	0
T14	4909	48	0	0
T15	38366	402	0	0
T16	221555	2265	0	0
T17	4051	86	0	0
T18	215640	1101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2818714	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2818714	0	0
T1	2146	24	0	0
T2	511600	3379	0	0
T3	671	4	0	0
T4	435047	990	0	0
T13	40123	145	0	0
T14	4909	71	0	0
T15	38366	118	0	0
T16	221555	2045	0	0
T17	4051	86	0	0
T18	215640	1411	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1458227	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1458227	0	0
T1	2146	33	0	0
T2	511600	5170	0	0
T3	671	6	0	0
T4	435047	5864	0	0
T13	40123	223	0	0
T14	4909	39	0	0
T15	38366	363	0	0
T16	221555	1768	0	0
T17	4051	65	0	0
T18	215640	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2892240	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2892240	0	0
T1	2146	33	0	0
T2	511600	5267	0	0
T3	671	6	0	0
T4	435047	2303	0	0
T13	40123	101	0	0
T14	4909	66	0	0
T15	38366	127	0	0
T16	221555	3687	0	0
T17	4051	65	0	0
T18	215640	4349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1494492	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1494492	0	0
T1	2146	37	0	0
T2	511600	4811	0	0
T3	671	10	0	0
T4	435047	4116	0	0
T13	40123	353	0	0
T14	4909	52	0	0
T15	38366	294	0	0
T16	221555	1578	0	0
T17	4051	77	0	0
T18	215640	4915	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3213941	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3213941	0	0
T1	2146	37	0	0
T2	511600	5343	0	0
T3	671	10	0	0
T4	435047	2120	0	0
T13	40123	123	0	0
T14	4909	50	0	0
T15	38366	128	0	0
T16	221555	787	0	0
T17	4051	77	0	0
T18	215640	4953	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1515095	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1515095	0	0
T1	2146	43	0	0
T2	511600	5296	0	0
T3	671	8	0	0
T4	435047	2386	0	0
T13	40123	250	0	0
T14	4909	96	0	0
T15	38366	1028	0	0
T16	221555	1711	0	0
T17	4051	71	0	0
T18	215640	910	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3280848	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3280848	0	0
T1	2146	43	0	0
T2	511600	5421	0	0
T3	671	8	0	0
T4	435047	962	0	0
T13	40123	104	0	0
T14	4909	41	0	0
T15	38366	463	0	0
T16	221555	1540	0	0
T17	4051	71	0	0
T18	215640	2263	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1515002	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1515002	0	0
T1	2146	37	0	0
T2	511600	5230	0	0
T3	671	4	0	0
T4	435047	4783	0	0
T13	40123	389	0	0
T14	4909	42	0	0
T15	38366	689	0	0
T16	221555	3672	0	0
T17	4051	79	0	0
T18	215640	884	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	3310749	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	3310749	0	0
T1	2146	37	0	0
T2	511600	5218	0	0
T3	671	4	0	0
T4	435047	2043	0	0
T13	40123	130	0	0
T14	4909	60	0	0
T15	38366	288	0	0
T16	221555	2848	0	0
T17	4051	79	0	0
T18	215640	326	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	1484910	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	1484910	0	0
T1	2146	38	0	0
T2	511600	5067	0	0
T3	671	9	0	0
T4	435047	3125	0	0
T13	40123	243	0	0
T14	4909	35	0	0
T15	38366	419	0	0
T16	221555	2647	0	0
T17	4051	74	0	0
T18	215640	479	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	301402714	2948780	0	0
DepthKnown_A	301402714	301279846	0	0
RvalidKnown_A	301402714	301279846	0	0
WreadyKnown_A	301402714	301279846	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	2948780	0	0
T1	2146	38	0	0
T2	511600	4927	0	0
T3	671	9	0	0
T4	435047	1498	0	0
T13	40123	178	0	0
T14	4909	49	0	0
T15	38366	110	0	0
T16	221555	623	0	0
T17	4051	74	0	0
T18	215640	1669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	301402714	301279846	0	0
T1	2146	2093	0	0
T2	511600	511561	0	0
T3	671	619	0	0
T4	435047	433158	0	0
T13	40123	40074	0	0
T14	4909	4891	0	0
T15	38366	36956	0	0
T16	221555	221497	0	0
T17	4051	3997	0	0
T18	215640	215610	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0