Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1652064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259909

1

T1

21

T2

1647

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647243	1			T1	83		T2	3988		T3	12
values[0x0]	617651	1			T1	61		T2	3964		T3	3
values[0x1]	647079	1			T1	78		T2	4016		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

631235

1

T1

63

T2

3914

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6807	1			T2	1		T14	3		T15	1
valid_sources[0x01]	7485	1			T14	13		T15	1		T17	6
valid_sources[0x02]	7737	1			T2	89		T14	10		T15	1
valid_sources[0x03]	6960	1			T2	100		T14	4		T15	1
valid_sources[0x04]	7381	1			T2	24		T16	41		T14	7
valid_sources[0x05]	6221	1			T2	35		T14	6		T17	6
valid_sources[0x06]	7580	1			T2	29		T3	1		T14	5
valid_sources[0x07]	7829	1			T2	19		T14	3		T15	1
valid_sources[0x08]	7778	1			T2	38		T16	48		T14	6
valid_sources[0x09]	7715	1			T2	4		T14	6		T17	3
valid_sources[0x0a]	7311	1			T2	459		T14	16		T15	4
valid_sources[0x0b]	7638	1			T1	3		T2	49		T14	17
valid_sources[0x0c]	6778	1			T2	50		T14	6		T15	2
valid_sources[0x0d]	7460	1			T2	17		T14	23		T17	3
valid_sources[0x0e]	7683	1			T2	276		T14	11		T15	1
valid_sources[0x0f]	7870	1			T2	313		T14	18		T15	1
valid_sources[0x10]	7629	1			T2	59		T17	1		T20	4
valid_sources[0x11]	6900	1			T2	44		T14	16		T15	2
valid_sources[0x12]	7277	1			T2	17		T3	2		T14	8
valid_sources[0x13]	7221	1			T2	20		T14	8		T15	2
valid_sources[0x14]	8811	1			T2	48		T14	4		T15	1
valid_sources[0x15]	6025	1			T2	7		T14	12		T15	2
valid_sources[0x16]	9046	1			T2	19		T14	25		T15	2
valid_sources[0x17]	7229	1			T2	64		T14	3		T17	8
valid_sources[0x18]	6865	1			T2	13		T14	31		T15	5
valid_sources[0x19]	7364	1			T2	26		T14	17		T15	4
valid_sources[0x1a]	9236	1			T2	7		T14	15		T15	5
valid_sources[0x1b]	7228	1			T2	6		T14	16		T17	4
valid_sources[0x1c]	7231	1			T2	24		T14	12		T15	2
valid_sources[0x1d]	6552	1			T2	1		T14	12		T15	3
valid_sources[0x1e]	7101	1			T2	28		T14	10		T15	1
valid_sources[0x1f]	8378	1			T2	5		T14	8		T15	4
valid_sources[0x20]	7326	1			T1	16		T2	3		T14	6
valid_sources[0x21]	8098	1			T2	28		T14	2		T15	2
valid_sources[0x22]	7679	1			T2	34		T14	20		T15	1
valid_sources[0x23]	10428	1			T2	15		T14	19		T15	3
valid_sources[0x24]	7094	1			T2	56		T17	4		T20	5
valid_sources[0x25]	7161	1			T2	24		T14	5		T15	4
valid_sources[0x26]	6837	1			T2	106		T14	12		T15	2
valid_sources[0x27]	7645	1			T2	2		T14	17		T15	1
valid_sources[0x28]	7331	1			T2	6		T16	12		T14	2
valid_sources[0x29]	7300	1			T2	13		T14	25		T15	1
valid_sources[0x2a]	9026	1			T2	114		T14	6		T15	4
valid_sources[0x2b]	8552	1			T2	35		T14	10		T15	3
valid_sources[0x2c]	8083	1			T2	33		T14	16		T15	1
valid_sources[0x2d]	7409	1			T2	45		T14	1		T15	3
valid_sources[0x2e]	8346	1			T2	20		T14	6		T15	2
valid_sources[0x2f]	6836	1			T2	82		T16	105		T14	8
valid_sources[0x30]	7058	1			T2	43		T14	21		T17	3
valid_sources[0x31]	7466	1			T2	6		T14	19		T15	3
valid_sources[0x32]	6951	1			T2	59		T14	5		T15	2
valid_sources[0x33]	7453	1			T2	588		T15	1		T17	4
valid_sources[0x34]	8647	1			T2	4		T16	12		T14	2
valid_sources[0x35]	8237	1			T2	4		T14	17		T15	1
valid_sources[0x36]	6971	1			T2	7		T14	11		T15	2
valid_sources[0x37]	7104	1			T2	11		T17	6		T20	5
valid_sources[0x38]	7989	1			T2	80		T3	3		T14	15
valid_sources[0x39]	8007	1			T1	32		T2	1		T14	1
valid_sources[0x3a]	7353	1			T2	32		T14	1		T15	2
valid_sources[0x3b]	7842	1			T2	65		T14	5		T15	1
valid_sources[0x3c]	7663	1			T2	48		T14	9		T15	1
valid_sources[0x3d]	6432	1			T2	6		T14	24		T15	2
valid_sources[0x3e]	7576	1			T2	16		T14	15		T15	1
valid_sources[0x3f]	7531	1			T2	56		T14	35		T15	2
valid_sources[0x40]	7233	1			T2	50		T14	17		T15	1
valid_sources[0x41]	7712	1			T2	39		T14	3		T17	2
valid_sources[0x42]	6353	1			T2	16		T14	14		T17	5
valid_sources[0x43]	7975	1			T2	60		T3	1		T14	27
valid_sources[0x44]	6671	1			T2	17		T14	8		T17	6
valid_sources[0x45]	7180	1			T2	26		T14	17		T15	4
valid_sources[0x46]	8328	1			T2	57		T14	12		T17	3
valid_sources[0x47]	7571	1			T2	65		T14	6		T17	6
valid_sources[0x48]	6605	1			T2	5		T15	1		T17	2
valid_sources[0x49]	7615	1			T2	24		T14	11		T17	3
valid_sources[0x4a]	7184	1			T2	156		T14	8		T15	1
valid_sources[0x4b]	6677	1			T2	15		T14	4		T15	1
valid_sources[0x4c]	6812	1			T1	3		T2	3		T14	5
valid_sources[0x4d]	6769	1			T2	39		T14	15		T15	3
valid_sources[0x4e]	7246	1			T2	43		T14	4		T15	3
valid_sources[0x4f]	7192	1			T2	16		T14	10		T15	4
valid_sources[0x50]	6438	1			T2	6		T14	4		T15	3
valid_sources[0x51]	9034	1			T2	28		T14	3		T15	2
valid_sources[0x52]	7418	1			T2	6		T14	24		T15	2
valid_sources[0x53]	7383	1			T2	43		T14	11		T17	4
valid_sources[0x54]	8640	1			T2	23		T3	3		T14	11
valid_sources[0x55]	7309	1			T2	60		T14	27		T15	2
valid_sources[0x56]	6680	1			T2	32		T14	7		T15	1
valid_sources[0x57]	6785	1			T1	15		T2	60		T14	2
valid_sources[0x58]	6779	1			T2	6		T14	12		T15	1
valid_sources[0x59]	7604	1			T2	4		T14	3		T15	2
valid_sources[0x5a]	7815	1			T2	6		T3	1		T14	3
valid_sources[0x5b]	7199	1			T2	13		T14	16		T15	4
valid_sources[0x5c]	7215	1			T2	4		T3	3		T14	9
valid_sources[0x5d]	6998	1			T2	38		T14	22		T15	1
valid_sources[0x5e]	6853	1			T2	2		T15	2		T17	10
valid_sources[0x5f]	7326	1			T2	68		T14	3		T15	1
valid_sources[0x60]	7746	1			T2	17		T14	19		T15	5
valid_sources[0x61]	6442	1			T2	3		T14	3		T15	6
valid_sources[0x62]	7522	1			T1	21		T2	4		T14	3
valid_sources[0x63]	8503	1			T2	310		T14	6		T17	4
valid_sources[0x64]	8663	1			T2	2		T14	3		T15	1
valid_sources[0x65]	7190	1			T2	5		T14	2		T15	2
valid_sources[0x66]	7631	1			T1	1		T2	5		T14	18
valid_sources[0x67]	7950	1			T2	27		T14	9		T17	4
valid_sources[0x68]	7848	1			T2	51		T14	9		T15	2
valid_sources[0x69]	6811	1			T2	62		T14	17		T15	2
valid_sources[0x6a]	7751	1			T14	9		T15	2		T17	2
valid_sources[0x6b]	6805	1			T2	62		T14	3		T15	1
valid_sources[0x6c]	7071	1			T2	58		T14	17		T15	3
valid_sources[0x6d]	8183	1			T2	25		T14	22		T17	8
valid_sources[0x6e]	7633	1			T2	11		T14	2		T15	1
valid_sources[0x6f]	6916	1			T2	2		T3	1		T14	18
valid_sources[0x70]	7095	1			T2	49		T14	9		T15	3
valid_sources[0x71]	7093	1			T2	7		T14	9		T15	3
valid_sources[0x72]	7006	1			T1	4		T2	38		T14	10
valid_sources[0x73]	7131	1			T2	9		T14	3		T15	1
valid_sources[0x74]	7370	1			T2	5		T14	10		T15	1
valid_sources[0x75]	9580	1			T2	13		T14	2		T15	2
valid_sources[0x76]	8018	1			T2	28		T14	8		T15	3
valid_sources[0x77]	9020	1			T2	3		T14	2		T15	1
valid_sources[0x78]	6802	1			T1	21		T2	209		T14	8
valid_sources[0x79]	7275	1			T2	6		T14	10		T15	1
valid_sources[0x7a]	7007	1			T1	3		T2	17		T16	9
valid_sources[0x7b]	8203	1			T2	23		T14	7		T15	2
valid_sources[0x7c]	6790	1			T2	4		T14	2		T15	2
valid_sources[0x7d]	7416	1			T2	8		T14	9		T15	2
valid_sources[0x7e]	6996	1			T2	149		T3	1		T14	32
valid_sources[0x7f]	9027	1			T2	4		T14	20		T15	1
valid_sources[0x80]	7634	1			T2	3		T14	25		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27299

1

T1

6

T2

151

T3

1

values[0x0]

all_enables

biggest_size

205435

1

T1

14

T2

1328

T3

2

values[0x1]

all_enables

biggest_size

27175

1

T1

1

T2

168

T3

2