Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328557832	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328557832	0	0
T1	16355192	384801	0	0
T2	1281672	53427	0	0
T3	1424080	35251	0	0
T14	292824	10349	0	0
T15	979216	39912	0	0
T16	28996072	607869	0	0
T17	6368376	1086522	0	0
T18	529088	12159	0	0
T19	5042296	156024	0	0
T20	45310272	1484658	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16355192	16354128	0	0
T2	1281672	1273160	0	0
T3	1424080	1419992	0	0
T14	292824	292040	0	0
T15	979216	974904	0	0
T16	28996072	28993664	0	0
T17	6368376	6368264	0	0
T18	529088	526736	0	0
T19	5042296	5040728	0	0
T20	45310272	45306912	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16355192	16354128	0	0
T2	1281672	1273160	0	0
T3	1424080	1419992	0	0
T14	292824	292040	0	0
T15	979216	974904	0	0
T16	28996072	28993664	0	0
T17	6368376	6368264	0	0
T18	529088	526736	0	0
T19	5042296	5040728	0	0
T20	45310272	45306912	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16355192	16354128	0	0
T2	1281672	1273160	0	0
T3	1424080	1419992	0	0
T14	292824	292040	0	0
T15	979216	974904	0	0
T16	28996072	28993664	0	0
T17	6368376	6368264	0	0
T18	529088	526736	0	0
T19	5042296	5040728	0	0
T20	45310272	45306912	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	117889983	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	117889983	0	0
T1	292057	158811	0	0
T2	22887	21461	0	0
T3	25430	15004	0	0
T14	5229	5092	0	0
T15	17486	15705	0	0
T16	517787	245149	0	0
T17	113721	504645	0	0
T18	9448	4865	0	0
T19	90041	88188	0	0
T20	809112	797941	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	86623721	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	86623721	0	0
T1	292057	76601	0	0
T2	22887	11968	0	0
T3	25430	6469	0	0
T14	5229	2603	0	0
T15	17486	8671	0	0
T16	517787	117914	0	0
T17	113721	120184	0	0
T18	9448	2403	0	0
T19	90041	33752	0	0
T20	809112	341301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1417680	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1417680	0	0
T1	292057	5773	0	0
T2	22887	293	0	0
T3	25430	266	0	0
T14	5229	51	0	0
T15	17486	259	0	0
T16	517787	2977	0	0
T17	113721	15077	0	0
T18	9448	190	0	0
T19	90041	9	0	0
T20	809112	154	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3697786	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3697786	0	0
T1	292057	3115	0	0
T2	22887	293	0	0
T3	25430	184	0	0
T14	5229	51	0	0
T15	17486	259	0	0
T16	517787	3862	0	0
T17	113721	3557	0	0
T18	9448	179	0	0
T19	90041	507	0	0
T20	809112	13272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1414014	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1414014	0	0
T1	292057	1569	0	0
T2	22887	307	0	0
T3	25430	262	0	0
T14	5229	55	0	0
T15	17486	257	0	0
T16	517787	4815	0	0
T17	113721	10584	0	0
T18	9448	57	0	0
T19	90041	21	0	0
T20	809112	171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3074214	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3074214	0	0
T1	292057	1545	0	0
T2	22887	307	0	0
T3	25430	222	0	0
T14	5229	55	0	0
T15	17486	257	0	0
T16	517787	4460	0	0
T17	113721	3296	0	0
T18	9448	76	0	0
T19	90041	2351	0	0
T20	809112	17068	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1432987	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1432987	0	0
T1	292057	2922	0	0
T2	22887	292	0	0
T3	25430	241	0	0
T14	5229	54	0	0
T15	17486	232	0	0
T16	517787	4662	0	0
T17	113721	9955	0	0
T18	9448	105	0	0
T19	90041	8	0	0
T20	809112	184	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3336979	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3336979	0	0
T1	292057	2995	0	0
T2	22887	292	0	0
T3	25430	212	0	0
T14	5229	54	0	0
T15	17486	232	0	0
T16	517787	6696	0	0
T17	113721	3166	0	0
T18	9448	65	0	0
T19	90041	1034	0	0
T20	809112	11076	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1420356	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1420356	0	0
T1	292057	2466	0	0
T2	22887	493	0	0
T3	25430	317	0	0
T14	5229	46	0	0
T15	17486	226	0	0
T16	517787	6460	0	0
T17	113721	5887	0	0
T18	9448	151	0	0
T19	90041	19	0	0
T20	809112	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3359089	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3359089	0	0
T1	292057	5150	0	0
T2	22887	493	0	0
T3	25430	313	0	0
T14	5229	46	0	0
T15	17486	226	0	0
T16	517787	6493	0	0
T17	113721	3214	0	0
T18	9448	135	0	0
T19	90041	1353	0	0
T20	809112	15655	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1447117	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1447117	0	0
T1	292057	5370	0	0
T2	22887	279	0	0
T3	25430	294	0	0
T14	5229	61	0	0
T15	17486	250	0	0
T16	517787	2502	0	0
T17	113721	15910	0	0
T18	9448	71	0	0
T19	90041	12	0	0
T20	809112	134	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3250880	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3250880	0	0
T1	292057	3367	0	0
T2	22887	279	0	0
T3	25430	266	0	0
T14	5229	61	0	0
T15	17486	250	0	0
T16	517787	2641	0	0
T17	113721	4453	0	0
T18	9448	44	0	0
T19	90041	1205	0	0
T20	809112	11407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1399806	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1399806	0	0
T1	292057	1607	0	0
T2	22887	321	0	0
T3	25430	340	0	0
T14	5229	44	0	0
T15	17486	241	0	0
T16	517787	4188	0	0
T17	113721	10630	0	0
T18	9448	88	0	0
T19	90041	25	0	0
T20	809112	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2932920	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2932920	0	0
T1	292057	2323	0	0
T2	22887	321	0	0
T3	25430	275	0	0
T14	5229	44	0	0
T15	17486	241	0	0
T16	517787	3366	0	0
T17	113721	4421	0	0
T18	9448	104	0	0
T19	90041	2160	0	0
T20	809112	10915	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1378582	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1378582	0	0
T1	292057	1955	0	0
T2	22887	288	0	0
T3	25430	337	0	0
T14	5229	50	0	0
T15	17486	249	0	0
T16	517787	4864	0	0
T17	113721	10038	0	0
T18	9448	160	0	0
T19	90041	2	0	0
T20	809112	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3071777	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3071777	0	0
T1	292057	1939	0	0
T2	22887	288	0	0
T3	25430	246	0	0
T14	5229	50	0	0
T15	17486	249	0	0
T16	517787	5667	0	0
T17	113721	4036	0	0
T18	9448	159	0	0
T19	90041	796	0	0
T20	809112	16193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1404474	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1404474	0	0
T1	292057	1411	0	0
T2	22887	313	0	0
T3	25430	205	0	0
T14	5229	38	0	0
T15	17486	551	0	0
T16	517787	4067	0	0
T17	113721	12708	0	0
T18	9448	103	0	0
T19	90041	10	0	0
T20	809112	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2631141	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2631141	0	0
T1	292057	2308	0	0
T2	22887	313	0	0
T3	25430	157	0	0
T14	5229	38	0	0
T15	17486	551	0	0
T16	517787	3519	0	0
T17	113721	5571	0	0
T18	9448	134	0	0
T19	90041	489	0	0
T20	809112	12245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1463317	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1463317	0	0
T1	292057	2602	0	0
T2	22887	306	0	0
T3	25430	334	0	0
T14	5229	59	0	0
T15	17486	523	0	0
T16	517787	2765	0	0
T17	113721	10472	0	0
T18	9448	65	0	0
T19	90041	24	0	0
T20	809112	119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2988124	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2988124	0	0
T1	292057	1436	0	0
T2	22887	306	0	0
T3	25430	276	0	0
T14	5229	59	0	0
T15	17486	523	0	0
T16	517787	4032	0	0
T17	113721	3952	0	0
T18	9448	103	0	0
T19	90041	2156	0	0
T20	809112	12035	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1416386	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1416386	0	0
T1	292057	3043	0	0
T2	22887	283	0	0
T3	25430	209	0	0
T14	5229	58	0	0
T15	17486	241	0	0
T16	517787	5544	0	0
T17	113721	12602	0	0
T18	9448	89	0	0
T19	90041	3	0	0
T20	809112	145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3118737	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3118737	0	0
T1	292057	2922	0	0
T2	22887	283	0	0
T3	25430	146	0	0
T14	5229	58	0	0
T15	17486	241	0	0
T16	517787	5298	0	0
T17	113721	5393	0	0
T18	9448	114	0	0
T19	90041	517	0	0
T20	809112	12781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1444032	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1444032	0	0
T1	292057	1977	0	0
T2	22887	323	0	0
T3	25430	196	0	0
T14	5229	53	0	0
T15	17486	228	0	0
T16	517787	5926	0	0
T17	113721	14169	0	0
T18	9448	76	0	0
T19	90041	8	0	0
T20	809112	149	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2923977	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2923977	0	0
T1	292057	2982	0	0
T2	22887	323	0	0
T3	25430	227	0	0
T14	5229	53	0	0
T15	17486	228	0	0
T16	517787	4285	0	0
T17	113721	5541	0	0
T18	9448	54	0	0
T19	90041	282	0	0
T20	809112	12675	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1440764	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1440764	0	0
T1	292057	1554	0	0
T2	22887	285	0	0
T3	25430	264	0	0
T14	5229	48	0	0
T15	17486	200	0	0
T16	517787	4857	0	0
T17	113721	13299	0	0
T18	9448	107	0	0
T19	90041	14	0	0
T20	809112	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	4090538	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	4090538	0	0
T1	292057	3559	0	0
T2	22887	285	0	0
T3	25430	230	0	0
T14	5229	48	0	0
T15	17486	200	0	0
T16	517787	3361	0	0
T17	113721	4007	0	0
T18	9448	86	0	0
T19	90041	1472	0	0
T20	809112	15628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1454864	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1454864	0	0
T1	292057	1244	0	0
T2	22887	297	0	0
T3	25430	269	0	0
T14	5229	42	0	0
T15	17486	234	0	0
T16	517787	3483	0	0
T17	113721	14221	0	0
T18	9448	28	0	0
T19	90041	12	0	0
T20	809112	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2753601	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2753601	0	0
T1	292057	1803	0	0
T2	22887	297	0	0
T3	25430	180	0	0
T14	5229	42	0	0
T15	17486	234	0	0
T16	517787	2828	0	0
T17	113721	2168	0	0
T18	9448	49	0	0
T19	90041	1401	0	0
T20	809112	10855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1398907	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1398907	0	0
T1	292057	3619	0	0
T2	22887	526	0	0
T3	25430	401	0	0
T14	5229	61	0	0
T15	17486	267	0	0
T16	517787	2520	0	0
T17	113721	16103	0	0
T18	9448	81	0	0
T19	90041	8	0	0
T20	809112	122	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3622040	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3622040	0	0
T1	292057	2649	0	0
T2	22887	526	0	0
T3	25430	357	0	0
T14	5229	61	0	0
T15	17486	267	0	0
T16	517787	2984	0	0
T17	113721	8059	0	0
T18	9448	67	0	0
T19	90041	364	0	0
T20	809112	10089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1405436	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1405436	0	0
T1	292057	5436	0	0
T2	22887	274	0	0
T3	25430	235	0	0
T14	5229	42	0	0
T15	17486	241	0	0
T16	517787	5389	0	0
T17	113721	12545	0	0
T18	9448	113	0	0
T19	90041	18	0	0
T20	809112	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3075891	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3075891	0	0
T1	292057	6377	0	0
T2	22887	274	0	0
T3	25430	264	0	0
T14	5229	42	0	0
T15	17486	241	0	0
T16	517787	4844	0	0
T17	113721	5064	0	0
T18	9448	77	0	0
T19	90041	985	0	0
T20	809112	10951	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1454781	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1454781	0	0
T1	292057	1245	0	0
T2	22887	599	0	0
T3	25430	243	0	0
T14	5229	42	0	0
T15	17486	282	0	0
T16	517787	5660	0	0
T17	113721	16443	0	0
T18	9448	51	0	0
T19	90041	9	0	0
T20	809112	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3250577	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3250577	0	0
T1	292057	1277	0	0
T2	22887	599	0	0
T3	25430	215	0	0
T14	5229	42	0	0
T15	17486	282	0	0
T16	517787	3660	0	0
T17	113721	3857	0	0
T18	9448	81	0	0
T19	90041	966	0	0
T20	809112	10432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1398540	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1398540	0	0
T1	292057	3222	0	0
T2	22887	282	0	0
T3	25430	226	0	0
T14	5229	50	0	0
T15	17486	511	0	0
T16	517787	4407	0	0
T17	113721	8238	0	0
T18	9448	39	0	0
T19	90041	12	0	0
T20	809112	223	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2672894	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2672894	0	0
T1	292057	2221	0	0
T2	22887	282	0	0
T3	25430	135	0	0
T14	5229	50	0	0
T15	17486	511	0	0
T16	517787	4081	0	0
T17	113721	4029	0	0
T18	9448	39	0	0
T19	90041	1041	0	0
T20	809112	13399	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1393475	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1393475	0	0
T1	292057	1258	0	0
T2	22887	261	0	0
T3	25430	303	0	0
T14	5229	41	0	0
T15	17486	276	0	0
T16	517787	6613	0	0
T17	113721	10413	0	0
T18	9448	69	0	0
T19	90041	4	0	0
T20	809112	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2585154	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2585154	0	0
T1	292057	3250	0	0
T2	22887	261	0	0
T3	25430	260	0	0
T14	5229	41	0	0
T15	17486	276	0	0
T16	517787	5964	0	0
T17	113721	4145	0	0
T18	9448	23	0	0
T19	90041	495	0	0
T20	809112	13760	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1409849	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1409849	0	0
T1	292057	1432	0	0
T2	22887	587	0	0
T3	25430	291	0	0
T14	5229	37	0	0
T15	17486	266	0	0
T16	517787	4733	0	0
T17	113721	14414	0	0
T18	9448	81	0	0
T19	90041	11	0	0
T20	809112	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3092542	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3092542	0	0
T1	292057	1660	0	0
T2	22887	587	0	0
T3	25430	263	0	0
T14	5229	37	0	0
T15	17486	266	0	0
T16	517787	4551	0	0
T17	113721	5074	0	0
T18	9448	70	0	0
T19	90041	1217	0	0
T20	809112	11706	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1391040	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1391040	0	0
T1	292057	3521	0	0
T2	22887	278	0	0
T3	25430	223	0	0
T14	5229	42	0	0
T15	17486	258	0	0
T16	517787	4849	0	0
T17	113721	12745	0	0
T18	9448	57	0	0
T19	90041	11	0	0
T20	809112	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2916233	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2916233	0	0
T1	292057	4020	0	0
T2	22887	278	0	0
T3	25430	255	0	0
T14	5229	42	0	0
T15	17486	258	0	0
T16	517787	4493	0	0
T17	113721	4963	0	0
T18	9448	74	0	0
T19	90041	633	0	0
T20	809112	14138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1440312	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1440312	0	0
T1	292057	3341	0	0
T2	22887	318	0	0
T3	25430	180	0	0
T14	5229	54	0	0
T15	17486	264	0	0
T16	517787	8638	0	0
T17	113721	15081	0	0
T18	9448	121	0	0
T19	90041	19	0	0
T20	809112	143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3272289	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3272289	0	0
T1	292057	4605	0	0
T2	22887	318	0	0
T3	25430	181	0	0
T14	5229	54	0	0
T15	17486	264	0	0
T16	517787	7276	0	0
T17	113721	4254	0	0
T18	9448	111	0	0
T19	90041	1196	0	0
T20	809112	13065	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1398016	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1398016	0	0
T1	292057	4989	0	0
T2	22887	289	0	0
T3	25430	266	0	0
T14	5229	47	0	0
T15	17486	278	0	0
T16	517787	5124	0	0
T17	113721	13461	0	0
T18	9448	48	0	0
T19	90041	20	0	0
T20	809112	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2881068	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2881068	0	0
T1	292057	5334	0	0
T2	22887	289	0	0
T3	25430	295	0	0
T14	5229	47	0	0
T15	17486	278	0	0
T16	517787	3647	0	0
T17	113721	3956	0	0
T18	9448	54	0	0
T19	90041	1788	0	0
T20	809112	13850	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1364662	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1364662	0	0
T1	292057	3323	0	0
T2	22887	292	0	0
T3	25430	289	0	0
T14	5229	49	0	0
T15	17486	230	0	0
T16	517787	4166	0	0
T17	113721	11805	0	0
T18	9448	103	0	0
T19	90041	1	0	0
T20	809112	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	2817565	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	2817565	0	0
T1	292057	2045	0	0
T2	22887	292	0	0
T3	25430	263	0	0
T14	5229	49	0	0
T15	17486	230	0	0
T16	517787	4204	0	0
T17	113721	3230	0	0
T18	9448	84	0	0
T19	90041	163	0	0
T20	809112	13915	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1456710	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1456710	0	0
T1	292057	1263	0	0
T2	22887	283	0	0
T3	25430	259	0	0
T14	5229	48	0	0
T15	17486	226	0	0
T16	517787	4328	0	0
T17	113721	14572	0	0
T18	9448	95	0	0
T19	90041	7	0	0
T20	809112	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3168473	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3168473	0	0
T1	292057	2232	0	0
T2	22887	283	0	0
T3	25430	233	0	0
T14	5229	48	0	0
T15	17486	226	0	0
T16	517787	2069	0	0
T17	113721	6881	0	0
T18	9448	65	0	0
T19	90041	889	0	0
T20	809112	10960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1433715	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1433715	0	0
T1	292057	1417	0	0
T2	22887	325	0	0
T3	25430	344	0	0
T14	5229	53	0	0
T15	17486	234	0	0
T16	517787	3924	0	0
T17	113721	15144	0	0
T18	9448	73	0	0
T19	90041	21	0	0
T20	809112	161	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	4444208	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	4444208	0	0
T1	292057	2340	0	0
T2	22887	325	0	0
T3	25430	280	0	0
T14	5229	53	0	0
T15	17486	234	0	0
T16	517787	3922	0	0
T17	113721	6372	0	0
T18	9448	93	0	0
T19	90041	3974	0	0
T20	809112	12958	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1414631	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1414631	0	0
T1	292057	2045	0	0
T2	22887	1300	0	0
T3	25430	255	0	0
T14	5229	51	0	0
T15	17486	480	0	0
T16	517787	4006	0	0
T17	113721	12795	0	0
T18	9448	120	0	0
T19	90041	9	0	0
T20	809112	131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3193270	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3193270	0	0
T1	292057	779	0	0
T2	22887	1300	0	0
T3	25430	308	0	0
T14	5229	51	0	0
T15	17486	480	0	0
T16	517787	5155	0	0
T17	113721	4007	0	0
T18	9448	120	0	0
T19	90041	1757	0	0
T20	809112	10648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	1450754	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	1450754	0	0
T1	292057	3512	0	0
T2	22887	305	0	0
T3	25430	261	0	0
T14	5229	51	0	0
T15	17486	264	0	0
T16	517787	5425	0	0
T17	113721	12198	0	0
T18	9448	147	0	0
T19	90041	15	0	0
T20	809112	118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304377921	3476954	0	0
DepthKnown_A	304377921	304243228	0	0
RvalidKnown_A	304377921	304243228	0	0
WreadyKnown_A	304377921	304243228	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	3476954	0	0
T1	292057	2040	0	0
T2	22887	305	0	0
T3	25430	225	0	0
T14	5229	51	0	0
T15	17486	264	0	0
T16	517787	4556	0	0
T17	113721	3518	0	0
T18	9448	143	0	0
T19	90041	2561	0	0
T20	809112	9625	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304377921	304243228	0	0
T1	292057	292038	0	0
T2	22887	22735	0	0
T3	25430	25357	0	0
T14	5229	5215	0	0
T15	17486	17409	0	0
T16	517787	517744	0	0
T17	113721	113719	0	0
T18	9448	9406	0	0
T19	90041	90013	0	0
T20	809112	809052	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0