Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245835

1

T1

26

T2

19

T3

215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	610125	1			T1	73		T2	50		T3	570
values[0x0]	584621	1			T1	59		T2	52		T3	561
values[0x1]	609795	1			T1	64		T2	46		T3	576

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207605	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596936

1

T1

62

T2

48

T3

524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6820	1			T3	5		T14	14		T17	4
valid_sources[0x01]	6777	1			T11	1		T10	26		T8	8
valid_sources[0x02]	7103	1			T1	1		T2	2		T3	18
valid_sources[0x03]	6908	1			T3	10		T4	3		T10	1
valid_sources[0x04]	6494	1			T4	1		T10	5		T14	15
valid_sources[0x05]	7448	1			T1	3		T3	7		T4	1
valid_sources[0x06]	6918	1			T1	2		T4	1		T10	3
valid_sources[0x07]	7039	1			T1	1		T10	19		T8	8
valid_sources[0x08]	7468	1			T2	3		T3	5		T4	1
valid_sources[0x09]	6746	1			T12	1		T10	1		T14	13
valid_sources[0x0a]	7934	1			T10	2		T14	11		T51	5
valid_sources[0x0b]	6493	1			T3	14		T4	1		T11	1
valid_sources[0x0c]	7065	1			T3	45		T12	3		T10	4
valid_sources[0x0d]	6775	1			T1	2		T12	1		T10	1
valid_sources[0x0e]	7583	1			T2	3		T3	41		T4	1
valid_sources[0x0f]	7316	1			T2	1		T3	27		T4	1
valid_sources[0x10]	6996	1			T3	10		T11	1		T14	12
valid_sources[0x11]	6567	1			T3	26		T4	1		T11	1
valid_sources[0x12]	6593	1			T3	16		T10	5		T8	13
valid_sources[0x13]	7240	1			T1	2		T10	1		T14	7
valid_sources[0x14]	6681	1			T3	8		T10	1		T14	15
valid_sources[0x15]	7360	1			T3	18		T10	4		T14	12
valid_sources[0x16]	7072	1			T2	1		T10	2		T8	20
valid_sources[0x17]	7213	1			T4	1		T8	28		T13	7
valid_sources[0x18]	7313	1			T2	3		T3	15		T8	12
valid_sources[0x19]	6428	1			T3	13		T11	1		T10	2
valid_sources[0x1a]	7356	1			T3	8		T10	5		T14	13
valid_sources[0x1b]	7134	1			T1	1		T10	15		T8	6
valid_sources[0x1c]	6916	1			T1	1		T12	1		T10	3
valid_sources[0x1d]	6975	1			T1	1		T4	1		T10	5
valid_sources[0x1e]	7743	1			T1	3		T3	10		T4	2
valid_sources[0x1f]	6690	1			T11	1		T8	29		T14	16
valid_sources[0x20]	7082	1			T1	3		T3	8		T14	9
valid_sources[0x21]	7076	1			T1	2		T3	20		T4	3
valid_sources[0x22]	7215	1			T4	1		T11	1		T10	3
valid_sources[0x23]	6631	1			T2	1		T12	7		T10	1
valid_sources[0x24]	6863	1			T1	3		T10	1		T14	10
valid_sources[0x25]	6793	1			T1	2		T10	3		T14	10
valid_sources[0x26]	7215	1			T11	1		T14	10		T17	3
valid_sources[0x27]	6819	1			T3	18		T10	2		T14	11
valid_sources[0x28]	7456	1			T1	2		T4	1		T11	3
valid_sources[0x29]	6764	1			T3	19		T12	1		T10	1
valid_sources[0x2a]	7114	1			T2	3		T10	10		T8	6
valid_sources[0x2b]	7008	1			T2	3		T8	14		T14	11
valid_sources[0x2c]	6367	1			T2	1		T4	1		T11	1
valid_sources[0x2d]	6865	1			T2	1		T14	13		T51	1
valid_sources[0x2e]	6151	1			T1	4		T3	20		T11	1
valid_sources[0x2f]	6643	1			T4	1		T12	2		T10	4
valid_sources[0x30]	6904	1			T3	24		T12	1		T10	7
valid_sources[0x31]	7090	1			T1	2		T2	5		T11	1
valid_sources[0x32]	6915	1			T3	10		T11	2		T10	6
valid_sources[0x33]	6516	1			T1	7		T10	2		T8	11
valid_sources[0x34]	6681	1			T1	3		T2	1		T3	31
valid_sources[0x35]	7008	1			T1	1		T12	9		T10	12
valid_sources[0x36]	6726	1			T12	3		T10	1		T14	19
valid_sources[0x37]	7243	1			T3	14		T11	1		T10	2
valid_sources[0x38]	6799	1			T4	1		T11	1		T12	1
valid_sources[0x39]	6485	1			T1	3		T2	4		T11	1
valid_sources[0x3a]	6368	1			T1	6		T3	11		T14	4
valid_sources[0x3b]	6711	1			T4	1		T12	1		T10	19
valid_sources[0x3c]	7731	1			T10	4		T8	6		T14	10
valid_sources[0x3d]	7381	1			T3	17		T10	3		T14	11
valid_sources[0x3e]	7052	1			T2	2		T4	1		T11	1
valid_sources[0x3f]	6559	1			T4	1		T11	1		T12	7
valid_sources[0x40]	6923	1			T3	10		T11	1		T12	2
valid_sources[0x41]	6956	1			T1	1		T11	2		T10	1
valid_sources[0x42]	7069	1			T3	7		T4	1		T9	1
valid_sources[0x43]	6939	1			T1	2		T3	16		T12	2
valid_sources[0x44]	6510	1			T1	1		T2	2		T3	33
valid_sources[0x45]	7487	1			T4	1		T11	1		T12	2
valid_sources[0x46]	7458	1			T3	20		T10	1		T14	14
valid_sources[0x47]	6810	1			T2	2		T4	1		T8	14
valid_sources[0x48]	6476	1			T1	1		T2	3		T3	8
valid_sources[0x49]	6871	1			T3	32		T10	3		T8	5
valid_sources[0x4a]	7312	1			T1	3		T2	1		T11	1
valid_sources[0x4b]	7113	1			T3	3		T11	1		T9	5
valid_sources[0x4c]	6822	1			T2	3		T3	5		T14	8
valid_sources[0x4d]	7850	1			T12	8		T14	6		T51	3
valid_sources[0x4e]	7755	1			T1	2		T10	4		T14	8
valid_sources[0x4f]	6583	1			T1	3		T2	3		T3	17
valid_sources[0x50]	7240	1			T1	1		T14	9		T51	2
valid_sources[0x51]	7263	1			T1	1		T4	1		T10	2
valid_sources[0x52]	6927	1			T10	2		T8	15		T14	8
valid_sources[0x53]	6564	1			T1	2		T2	4		T4	1
valid_sources[0x54]	7305	1			T3	9		T11	1		T14	11
valid_sources[0x55]	6886	1			T3	17		T4	1		T11	1
valid_sources[0x56]	6814	1			T10	5		T14	7		T17	7
valid_sources[0x57]	7197	1			T2	2		T12	8		T10	1
valid_sources[0x58]	6952	1			T1	1		T4	1		T10	5
valid_sources[0x59]	6940	1			T12	4		T10	1		T13	1
valid_sources[0x5a]	6930	1			T2	1		T3	5		T4	1
valid_sources[0x5b]	7247	1			T1	5		T2	1		T4	1
valid_sources[0x5c]	7709	1			T11	2		T8	36		T14	10
valid_sources[0x5d]	6664	1			T3	25		T4	1		T12	2
valid_sources[0x5e]	6962	1			T13	6		T14	10		T51	1
valid_sources[0x5f]	6834	1			T3	7		T14	12		T51	4
valid_sources[0x60]	7040	1			T10	1		T8	19		T14	15
valid_sources[0x61]	6868	1			T1	1		T8	19		T14	7
valid_sources[0x62]	7026	1			T1	1		T10	4		T14	10
valid_sources[0x63]	6750	1			T3	13		T14	8		T51	4
valid_sources[0x64]	6925	1			T1	1		T10	1		T8	14
valid_sources[0x65]	6720	1			T1	1		T3	8		T4	1
valid_sources[0x66]	7145	1			T2	1		T4	1		T11	2
valid_sources[0x67]	7372	1			T2	4		T3	12		T10	5
valid_sources[0x68]	6867	1			T4	1		T10	7		T14	9
valid_sources[0x69]	7685	1			T1	6		T3	14		T10	1
valid_sources[0x6a]	7678	1			T1	1		T4	1		T12	1
valid_sources[0x6b]	6785	1			T2	1		T3	20		T11	2
valid_sources[0x6c]	6997	1			T4	1		T11	1		T12	8
valid_sources[0x6d]	6617	1			T2	1		T4	1		T12	3
valid_sources[0x6e]	7602	1			T3	22		T4	1		T14	4
valid_sources[0x6f]	7067	1			T1	2		T2	5		T4	1
valid_sources[0x70]	6804	1			T2	1		T3	15		T10	9
valid_sources[0x71]	6557	1			T4	1		T14	14		T51	1
valid_sources[0x72]	7515	1			T1	6		T11	2		T10	3
valid_sources[0x73]	6735	1			T3	17		T4	1		T10	9
valid_sources[0x74]	6801	1			T3	8		T10	4		T8	13
valid_sources[0x75]	6606	1			T4	1		T8	19		T14	6
valid_sources[0x76]	6849	1			T4	1		T10	5		T14	7
valid_sources[0x77]	6152	1			T11	1		T10	1		T8	14
valid_sources[0x78]	7244	1			T11	1		T14	15		T51	1
valid_sources[0x79]	6593	1			T1	1		T2	1		T3	11
valid_sources[0x7a]	6918	1			T1	1		T3	12		T10	2
valid_sources[0x7b]	7080	1			T1	3		T11	1		T10	1
valid_sources[0x7c]	6346	1			T1	1		T3	8		T4	1
valid_sources[0x7d]	7510	1			T1	6		T2	4		T3	9
valid_sources[0x7e]	6602	1			T10	1		T14	9		T51	1
valid_sources[0x7f]	7290	1			T1	4		T3	7		T4	1
valid_sources[0x80]	7814	1			T2	2		T3	14		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25833

1

T1

3

T2

2

T3

26

values[0x0]

all_enables

biggest_size

194307

1

T1

20

T2

16

T3

166

values[0x1]

all_enables

biggest_size

25695

1

T1

3

T2

1

T3

23