Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	338914294	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	338914294	0	0
T1	12609968	225338	0	0
T2	19208	722	0	0
T3	3663352	50365	0	0
T4	2260440	51639	0	0
T8	163072	5468	0	0
T9	381808	8525	0	0
T10	18217080	337606	0	0
T11	37800	515	0	0
T12	5189632	92142	0	0
T13	10249848	187373	0	0
T14	0	3793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12609968	12607896	0	0
T2	19208	18760	0	0
T3	3663352	3659264	0	0
T4	2260440	2258704	0	0
T8	163072	161672	0	0
T9	381808	378056	0	0
T10	18217080	18203248	0	0
T11	37800	33712	0	0
T12	5189632	5187112	0	0
T13	10249848	10246208	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12609968	12607896	0	0
T2	19208	18760	0	0
T3	3663352	3659264	0	0
T4	2260440	2258704	0	0
T8	163072	161672	0	0
T9	381808	378056	0	0
T10	18217080	18203248	0	0
T11	37800	33712	0	0
T12	5189632	5187112	0	0
T13	10249848	10246208	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12609968	12607896	0	0
T2	19208	18760	0	0
T3	3663352	3659264	0	0
T4	2260440	2258704	0	0
T8	163072	161672	0	0
T9	381808	378056	0	0
T10	18217080	18203248	0	0
T11	37800	33712	0	0
T12	5189632	5187112	0	0
T13	10249848	10246208	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T8	56	56	0	0
T9	56	56	0	0
T10	56	56	0	0
T11	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	122662212	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	122662212	0	0
T1	225178	102184	0	0
T2	343	278	0	0
T3	65417	13332	0	0
T4	40365	19873	0	0
T8	2912	1371	0	0
T9	6818	3397	0	0
T10	325305	148098	0	0
T11	675	200	0	0
T12	92672	90821	0	0
T13	183033	83943	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	88621915	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	88621915	0	0
T1	225178	25937	0	0
T2	343	148	0	0
T3	65417	11863	0	0
T4	40365	16757	0	0
T8	2912	1371	0	0
T9	6818	2550	0	0
T10	325305	44113	0	0
T11	675	105	0	0
T12	92672	294	0	0
T13	183033	22746	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1482784	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1482784	0	0
T1	225178	4325	0	0
T2	343	5	0	0
T3	65417	501	0	0
T4	40365	279	0	0
T8	2912	49	0	0
T9	6818	46	0	0
T10	325305	7058	0	0
T11	675	3	0	0
T12	92672	28	0	0
T13	183033	1517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2846545	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2846545	0	0
T1	225178	1763	0	0
T2	343	5	0	0
T3	65417	408	0	0
T4	40365	314	0	0
T8	2912	49	0	0
T9	6818	51	0	0
T10	325305	2825	0	0
T11	675	3	0	0
T12	92672	8	0	0
T13	183033	1145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1459294	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1459294	0	0
T1	225178	2473	0	0
T2	343	10	0	0
T3	65417	466	0	0
T4	40365	342	0	0
T8	2912	38	0	0
T9	6818	22	0	0
T10	325305	3008	0	0
T11	675	5	0	0
T12	92672	34	0	0
T13	183033	2243	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2972724	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2972724	0	0
T1	225178	76	0	0
T2	343	10	0	0
T3	65417	406	0	0
T4	40365	321	0	0
T8	2912	38	0	0
T9	6818	37	0	0
T10	325305	1179	0	0
T11	675	5	0	0
T12	92672	8	0	0
T13	183033	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1484271	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1484271	0	0
T1	225178	877	0	0
T2	343	3	0	0
T3	65417	412	0	0
T4	40365	225	0	0
T8	2912	57	0	0
T9	6818	79	0	0
T10	325305	8066	0	0
T11	675	4	0	0
T12	92672	31	0	0
T13	183033	1650	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3219163	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3219163	0	0
T1	225178	119	0	0
T2	343	3	0	0
T3	65417	451	0	0
T4	40365	246	0	0
T8	2912	57	0	0
T9	6818	72	0	0
T10	325305	3561	0	0
T11	675	4	0	0
T12	92672	5	0	0
T13	183033	861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1489724	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1489724	0	0
T1	225178	965	0	0
T2	343	4	0	0
T3	65417	459	0	0
T4	40365	237	0	0
T8	2912	46	0	0
T9	6818	56	0	0
T10	325305	2658	0	0
T11	675	4	0	0
T12	92672	28	0	0
T13	183033	887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3766694	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3766694	0	0
T1	225178	521	0	0
T2	343	4	0	0
T3	65417	412	0	0
T4	40365	199	0	0
T8	2912	46	0	0
T9	6818	52	0	0
T10	325305	979	0	0
T11	675	4	0	0
T12	92672	7	0	0
T13	183033	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1515428	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1515428	0	0
T1	225178	2378	0	0
T2	343	5	0	0
T3	65417	389	0	0
T4	40365	246	0	0
T8	2912	53	0	0
T9	6818	80	0	0
T10	325305	4711	0	0
T11	675	6	0	0
T12	92672	49	0	0
T13	183033	2993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3293826	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3293826	0	0
T1	225178	1074	0	0
T2	343	5	0	0
T3	65417	469	0	0
T4	40365	237	0	0
T8	2912	53	0	0
T9	6818	71	0	0
T10	325305	2006	0	0
T11	675	6	0	0
T12	92672	9	0	0
T13	183033	2131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1479253	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1479253	0	0
T1	225178	2356	0	0
T2	343	2	0	0
T3	65417	405	0	0
T4	40365	294	0	0
T8	2912	50	0	0
T9	6818	37	0	0
T10	325305	2825	0	0
T11	675	4	0	0
T12	92672	43	0	0
T13	183033	2428	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3075429	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3075429	0	0
T1	225178	1424	0	0
T2	343	2	0	0
T3	65417	411	0	0
T4	40365	229	0	0
T8	2912	50	0	0
T9	6818	38	0	0
T10	325305	1164	0	0
T11	675	4	0	0
T12	92672	9	0	0
T13	183033	144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1492433	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1492433	0	0
T1	225178	5634	0	0
T2	343	8	0	0
T3	65417	398	0	0
T4	40365	231	0	0
T8	2912	60	0	0
T9	6818	16	0	0
T10	325305	2705	0	0
T11	675	4	0	0
T12	92672	28	0	0
T13	183033	1957	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2877256	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2877256	0	0
T1	225178	2025	0	0
T2	343	8	0	0
T3	65417	365	0	0
T4	40365	233	0	0
T8	2912	60	0	0
T9	6818	19	0	0
T10	325305	1173	0	0
T11	675	4	0	0
T12	92672	7	0	0
T13	183033	431	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1453351	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1453351	0	0
T1	225178	2013	0	0
T2	343	4	0	0
T3	65417	507	0	0
T4	40365	284	0	0
T8	2912	49	0	0
T9	6818	39	0	0
T10	325305	2491	0	0
T11	675	5	0	0
T12	92672	34	0	0
T13	183033	1446	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3739710	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3739710	0	0
T1	225178	1322	0	0
T2	343	4	0	0
T3	65417	397	0	0
T4	40365	288	0	0
T8	2912	49	0	0
T9	6818	42	0	0
T10	325305	967	0	0
T11	675	5	0	0
T12	92672	8	0	0
T13	183033	1536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1500848	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1500848	0	0
T1	225178	2507	0	0
T2	343	7	0	0
T3	65417	295	0	0
T4	40365	244	0	0
T8	2912	56	0	0
T9	6818	48	0	0
T10	325305	2616	0	0
T11	675	4	0	0
T12	92672	20	0	0
T13	183033	4785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3294791	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3294791	0	0
T1	225178	270	0	0
T2	343	7	0	0
T3	65417	378	0	0
T4	40365	258	0	0
T8	2912	56	0	0
T9	6818	49	0	0
T10	325305	1048	0	0
T11	675	4	0	0
T12	92672	7	0	0
T13	183033	1932	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1462685	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1462685	0	0
T1	225178	4071	0	0
T2	343	3	0	0
T3	65417	447	0	0
T4	40365	259	0	0
T8	2912	41	0	0
T9	6818	51	0	0
T10	325305	2527	0	0
T11	675	2	0	0
T12	92672	5	0	0
T13	183033	1221	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3251988	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3251988	0	0
T1	225178	1619	0	0
T2	343	3	0	0
T3	65417	395	0	0
T4	40365	250	0	0
T8	2912	41	0	0
T9	6818	49	0	0
T10	325305	950	0	0
T11	675	2	0	0
T12	92672	1	0	0
T13	183033	1349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1421420	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1421420	0	0
T1	225178	1173	0	0
T2	343	1	0	0
T3	65417	466	0	0
T4	40365	320	0	0
T8	2912	61	0	0
T9	6818	24	0	0
T10	325305	2922	0	0
T11	675	5	0	0
T12	92672	31	0	0
T13	183033	1804	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3413458	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3413458	0	0
T1	225178	329	0	0
T2	343	1	0	0
T3	65417	515	0	0
T4	40365	400	0	0
T8	2912	61	0	0
T9	6818	24	0	0
T10	325305	1132	0	0
T11	675	5	0	0
T12	92672	124	0	0
T13	183033	1831	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1434630	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1434630	0	0
T1	225178	2077	0	0
T2	343	8	0	0
T3	65417	515	0	0
T4	40365	358	0	0
T8	2912	55	0	0
T9	6818	36	0	0
T10	325305	4547	0	0
T11	675	0	0	0
T12	92672	37	0	0
T13	183033	1826	0	0
T14	0	1591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3338809	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3338809	0	0
T1	225178	619	0	0
T2	343	8	0	0
T3	65417	409	0	0
T4	40365	362	0	0
T8	2912	55	0	0
T9	6818	14	0	0
T10	325305	1814	0	0
T11	675	0	0	0
T12	92672	10	0	0
T13	183033	592	0	0
T14	0	2202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1519764	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1519764	0	0
T1	225178	2143	0	0
T2	343	2	0	0
T3	65417	551	0	0
T4	40365	262	0	0
T8	2912	30	0	0
T9	6818	48	0	0
T10	325305	3069	0	0
T11	675	3	0	0
T12	92672	45	0	0
T13	183033	3597	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3624597	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3624597	0	0
T1	225178	2028	0	0
T2	343	2	0	0
T3	65417	429	0	0
T4	40365	322	0	0
T8	2912	30	0	0
T9	6818	41	0	0
T10	325305	1286	0	0
T11	675	3	0	0
T12	92672	9	0	0
T13	183033	1375	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1513416	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1513416	0	0
T1	225178	5560	0	0
T2	343	10	0	0
T3	65417	514	0	0
T4	40365	284	0	0
T8	2912	56	0	0
T9	6818	15	0	0
T10	325305	4503	0	0
T11	675	3	0	0
T12	92672	30	0	0
T13	183033	2023	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3148691	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3148691	0	0
T1	225178	822	0	0
T2	343	10	0	0
T3	65417	533	0	0
T4	40365	233	0	0
T8	2912	56	0	0
T9	6818	49	0	0
T10	325305	2032	0	0
T11	675	3	0	0
T12	92672	6	0	0
T13	183033	837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1415365	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1415365	0	0
T1	225178	352	0	0
T2	343	5	0	0
T3	65417	581	0	0
T4	40365	261	0	0
T8	2912	45	0	0
T9	6818	41	0	0
T10	325305	4447	0	0
T11	675	2	0	0
T12	92672	42	0	0
T13	183033	1154	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3097508	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3097508	0	0
T1	225178	512	0	0
T2	343	5	0	0
T3	65417	338	0	0
T4	40365	227	0	0
T8	2912	45	0	0
T9	6818	28	0	0
T10	325305	1853	0	0
T11	675	2	0	0
T12	92672	6	0	0
T13	183033	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1499411	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1499411	0	0
T1	225178	3756	0	0
T2	343	8	0	0
T3	65417	614	0	0
T4	40365	331	0	0
T8	2912	48	0	0
T9	6818	66	0	0
T10	325305	2579	0	0
T11	675	1	0	0
T12	92672	22	0	0
T13	183033	2490	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3016186	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3016186	0	0
T1	225178	1184	0	0
T2	343	8	0	0
T3	65417	591	0	0
T4	40365	279	0	0
T8	2912	48	0	0
T9	6818	81	0	0
T10	325305	1157	0	0
T11	675	1	0	0
T12	92672	7	0	0
T13	183033	1217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1458189	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1458189	0	0
T1	225178	2361	0	0
T2	343	6	0	0
T3	65417	464	0	0
T4	40365	416	0	0
T8	2912	40	0	0
T9	6818	50	0	0
T10	325305	2759	0	0
T11	675	3	0	0
T12	92672	14	0	0
T13	183033	2198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2374602	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2374602	0	0
T1	225178	326	0	0
T2	343	6	0	0
T3	65417	351	0	0
T4	40365	384	0	0
T8	2912	40	0	0
T9	6818	56	0	0
T10	325305	1328	0	0
T11	675	3	0	0
T12	92672	5	0	0
T13	183033	248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1463957	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1463957	0	0
T1	225178	1528	0	0
T2	343	3	0	0
T3	65417	560	0	0
T4	40365	318	0	0
T8	2912	51	0	0
T9	6818	48	0	0
T10	325305	4692	0	0
T11	675	4	0	0
T12	92672	32	0	0
T13	183033	2253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3056021	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3056021	0	0
T1	225178	241	0	0
T2	343	3	0	0
T3	65417	431	0	0
T4	40365	276	0	0
T8	2912	51	0	0
T9	6818	55	0	0
T10	325305	2087	0	0
T11	675	4	0	0
T12	92672	8	0	0
T13	183033	911	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1515640	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1515640	0	0
T1	225178	5548	0	0
T2	343	7	0	0
T3	65417	540	0	0
T4	40365	308	0	0
T8	2912	46	0	0
T9	6818	52	0	0
T10	325305	2428	0	0
T11	675	4	0	0
T12	92672	1	0	0
T13	183033	1586	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2806955	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2806955	0	0
T1	225178	1075	0	0
T2	343	7	0	0
T3	65417	390	0	0
T4	40365	244	0	0
T8	2912	46	0	0
T9	6818	51	0	0
T10	325305	1018	0	0
T11	675	4	0	0
T12	92672	1	0	0
T13	183033	325	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1529974	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1529974	0	0
T1	225178	2429	0	0
T2	343	5	0	0
T3	65417	492	0	0
T4	40365	180	0	0
T8	2912	53	0	0
T9	6818	82	0	0
T10	325305	2998	0	0
T11	675	3	0	0
T12	92672	15	0	0
T13	183033	1381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	4102035	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	4102035	0	0
T1	225178	1101	0	0
T2	343	5	0	0
T3	65417	444	0	0
T4	40365	172	0	0
T8	2912	53	0	0
T9	6818	64	0	0
T10	325305	1113	0	0
T11	675	3	0	0
T12	92672	4	0	0
T13	183033	315	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1500641	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1500641	0	0
T1	225178	1068	0	0
T2	343	1	0	0
T3	65417	356	0	0
T4	40365	270	0	0
T8	2912	63	0	0
T9	6818	43	0	0
T10	325305	4837	0	0
T11	675	4	0	0
T12	92672	11	0	0
T13	183033	3827	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3109187	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3109187	0	0
T1	225178	705	0	0
T2	343	1	0	0
T3	65417	383	0	0
T4	40365	206	0	0
T8	2912	63	0	0
T9	6818	39	0	0
T10	325305	1995	0	0
T11	675	4	0	0
T12	92672	3	0	0
T13	183033	383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1531051	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1531051	0	0
T1	225178	1696	0	0
T2	343	6	0	0
T3	65417	517	0	0
T4	40365	403	0	0
T8	2912	58	0	0
T9	6818	44	0	0
T10	325305	2633	0	0
T11	675	6	0	0
T12	92672	45	0	0
T13	183033	2260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3833255	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3833255	0	0
T1	225178	715	0	0
T2	343	6	0	0
T3	65417	383	0	0
T4	40365	343	0	0
T8	2912	58	0	0
T9	6818	28	0	0
T10	325305	1023	0	0
T11	675	6	0	0
T12	92672	10	0	0
T13	183033	284	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1445088	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1445088	0	0
T1	225178	1976	0	0
T2	343	8	0	0
T3	65417	504	0	0
T4	40365	349	0	0
T8	2912	57	0	0
T9	6818	21	0	0
T10	325305	4551	0	0
T11	675	7	0	0
T12	92672	18	0	0
T13	183033	2000	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3208145	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3208145	0	0
T1	225178	1358	0	0
T2	343	8	0	0
T3	65417	410	0	0
T4	40365	305	0	0
T8	2912	57	0	0
T9	6818	44	0	0
T10	325305	1989	0	0
T11	675	7	0	0
T12	92672	6	0	0
T13	183033	471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1464750	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1464750	0	0
T1	225178	3772	0	0
T2	343	3	0	0
T3	65417	417	0	0
T4	40365	202	0	0
T8	2912	48	0	0
T9	6818	46	0	0
T10	325305	2420	0	0
T11	675	3	0	0
T12	92672	14	0	0
T13	183033	1923	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2789547	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2789547	0	0
T1	225178	1304	0	0
T2	343	3	0	0
T3	65417	365	0	0
T4	40365	229	0	0
T8	2912	48	0	0
T9	6818	81	0	0
T10	325305	916	0	0
T11	675	3	0	0
T12	92672	6	0	0
T13	183033	1106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1479194	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1479194	0	0
T1	225178	3314	0	0
T2	343	7	0	0
T3	65417	582	0	0
T4	40365	274	0	0
T8	2912	49	0	0
T9	6818	27	0	0
T10	325305	5007	0	0
T11	675	6	0	0
T12	92672	19	0	0
T13	183033	2102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	2904197	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	2904197	0	0
T1	225178	2359	0	0
T2	343	7	0	0
T3	65417	499	0	0
T4	40365	227	0	0
T8	2912	49	0	0
T9	6818	40	0	0
T10	325305	2140	0	0
T11	675	6	0	0
T12	92672	3	0	0
T13	183033	801	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1498434	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1498434	0	0
T1	225178	2532	0	0
T2	343	8	0	0
T3	65417	696	0	0
T4	40365	249	0	0
T8	2912	48	0	0
T9	6818	93	0	0
T10	325305	2723	0	0
T11	675	6	0	0
T12	92672	39	0	0
T13	183033	1815	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	3473942	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	3473942	0	0
T1	225178	557	0	0
T2	343	8	0	0
T3	65417	692	0	0
T4	40365	210	0	0
T8	2912	48	0	0
T9	6818	105	0	0
T10	325305	1107	0	0
T11	675	6	0	0
T12	92672	10	0	0
T13	183033	1456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	1460696	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	1460696	0	0
T1	225178	2396	0	0
T2	343	9	0	0
T3	65417	679	0	0
T4	40365	300	0	0
T8	2912	56	0	0
T9	6818	34	0	0
T10	325305	6831	0	0
T11	675	4	0	0
T12	92672	18	0	0
T13	183033	2572	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	312043920	4023215	0	0
DepthKnown_A	312043920	311929561	0	0
RvalidKnown_A	312043920	311929561	0	0
WreadyKnown_A	312043920	311929561	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	4023215	0	0
T1	225178	489	0	0
T2	343	9	0	0
T3	65417	588	0	0
T4	40365	289	0	0
T8	2912	56	0	0
T9	6818	54	0	0
T10	325305	2942	0	0
T11	675	4	0	0
T12	92672	7	0	0
T13	183033	380	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312043920	311929561	0	0
T1	225178	225141	0	0
T2	343	335	0	0
T3	65417	65344	0	0
T4	40365	40334	0	0
T8	2912	2887	0	0
T9	6818	6751	0	0
T10	325305	325058	0	0
T11	675	602	0	0
T12	92672	92627	0	0
T13	183033	182968	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0