Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1657550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261054

1

T1

30

T2

375

T3

264

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	648599	1			T1	51		T2	858		T3	639
values[0x0]	620634	1			T1	68		T2	851		T3	630
values[0x1]	649371	1			T1	43		T2	819		T3	668

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1285222	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

633382

1

T1

57

T2

858

T3

641

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6950	1			T1	10		T2	10		T3	20
valid_sources[0x01]	7796	1			T2	5		T3	9		T17	11
valid_sources[0x02]	7187	1			T2	1		T3	6		T17	9
valid_sources[0x03]	7167	1			T2	11		T17	11		T5	7
valid_sources[0x04]	7188	1			T2	4		T17	8		T5	2
valid_sources[0x05]	7128	1			T3	7		T4	2		T17	10
valid_sources[0x06]	7301	1			T2	3		T3	5		T17	10
valid_sources[0x07]	7454	1			T2	15		T3	18		T17	11
valid_sources[0x08]	7480	1			T2	5		T3	22		T17	9
valid_sources[0x09]	7183	1			T2	4		T3	10		T4	2
valid_sources[0x0a]	6957	1			T2	9		T3	6		T17	10
valid_sources[0x0b]	7069	1			T2	14		T3	12		T17	11
valid_sources[0x0c]	7650	1			T2	17		T3	18		T17	9
valid_sources[0x0d]	8837	1			T2	33		T3	20		T17	12
valid_sources[0x0e]	7169	1			T2	10		T17	9		T22	5
valid_sources[0x0f]	7467	1			T2	9		T3	9		T17	10
valid_sources[0x10]	7826	1			T2	24		T17	10		T22	6
valid_sources[0x11]	7700	1			T2	9		T17	11		T5	18
valid_sources[0x12]	7542	1			T2	7		T4	1		T17	11
valid_sources[0x13]	6942	1			T2	12		T17	10		T22	5
valid_sources[0x14]	7281	1			T2	23		T4	1		T17	11
valid_sources[0x15]	7183	1			T2	8		T17	11		T22	5
valid_sources[0x16]	7106	1			T2	4		T4	1		T17	10
valid_sources[0x17]	7149	1			T1	8		T2	26		T3	20
valid_sources[0x18]	7471	1			T2	7		T3	14		T17	8
valid_sources[0x19]	7627	1			T2	12		T3	7		T17	10
valid_sources[0x1a]	7221	1			T2	14		T3	7		T4	2
valid_sources[0x1b]	8183	1			T2	9		T3	8		T4	1
valid_sources[0x1c]	6772	1			T2	7		T3	12		T17	11
valid_sources[0x1d]	7263	1			T2	19		T3	15		T17	10
valid_sources[0x1e]	7732	1			T2	9		T17	8		T22	8
valid_sources[0x1f]	7482	1			T1	3		T2	6		T4	1
valid_sources[0x20]	7835	1			T2	4		T3	10		T17	9
valid_sources[0x21]	6743	1			T1	1		T2	3		T17	11
valid_sources[0x22]	7207	1			T2	6		T17	11		T22	5
valid_sources[0x23]	7458	1			T2	1		T17	10		T22	5
valid_sources[0x24]	8374	1			T2	10		T3	17		T4	1
valid_sources[0x25]	7362	1			T2	8		T17	10		T22	5
valid_sources[0x26]	7637	1			T2	11		T4	3		T17	10
valid_sources[0x27]	8712	1			T2	5		T17	9		T5	24
valid_sources[0x28]	7015	1			T2	18		T3	20		T17	13
valid_sources[0x29]	7676	1			T2	11		T17	11		T22	6
valid_sources[0x2a]	7091	1			T2	17		T17	10		T5	5
valid_sources[0x2b]	6647	1			T2	2		T17	9		T22	5
valid_sources[0x2c]	7383	1			T2	7		T17	11		T22	5
valid_sources[0x2d]	7747	1			T2	20		T17	13		T22	5
valid_sources[0x2e]	7678	1			T2	8		T4	1		T17	12
valid_sources[0x2f]	7717	1			T2	5		T3	27		T17	12
valid_sources[0x30]	8204	1			T2	6		T3	14		T17	11
valid_sources[0x31]	6940	1			T2	20		T17	10		T22	5
valid_sources[0x32]	7519	1			T2	1		T17	9		T22	7
valid_sources[0x33]	7361	1			T1	2		T17	10		T22	5
valid_sources[0x34]	6796	1			T1	8		T2	16		T3	6
valid_sources[0x35]	8021	1			T2	1		T3	11		T17	9
valid_sources[0x36]	7163	1			T2	7		T4	1		T17	9
valid_sources[0x37]	6966	1			T2	13		T17	10		T22	5
valid_sources[0x38]	7719	1			T2	14		T17	12		T22	5
valid_sources[0x39]	7202	1			T2	5		T3	6		T17	11
valid_sources[0x3a]	6943	1			T2	14		T17	11		T22	6
valid_sources[0x3b]	7903	1			T2	12		T17	10		T22	5
valid_sources[0x3c]	7540	1			T2	5		T17	9		T22	5
valid_sources[0x3d]	7433	1			T2	1		T4	2		T17	11
valid_sources[0x3e]	8083	1			T2	8		T3	21		T4	1
valid_sources[0x3f]	7176	1			T1	3		T2	8		T3	13
valid_sources[0x40]	8237	1			T2	2		T4	1		T17	11
valid_sources[0x41]	8659	1			T2	7		T17	12		T22	5
valid_sources[0x42]	8451	1			T2	8		T3	9		T17	10
valid_sources[0x43]	8390	1			T1	14		T2	7		T3	6
valid_sources[0x44]	7719	1			T2	11		T17	11		T22	5
valid_sources[0x45]	6258	1			T2	13		T3	9		T4	2
valid_sources[0x46]	6863	1			T2	20		T4	1		T17	12
valid_sources[0x47]	7717	1			T2	23		T3	37		T17	11
valid_sources[0x48]	7250	1			T2	12		T17	10		T22	6
valid_sources[0x49]	7434	1			T2	6		T17	11		T5	5
valid_sources[0x4a]	7463	1			T2	9		T3	21		T4	1
valid_sources[0x4b]	7367	1			T2	24		T3	27		T17	10
valid_sources[0x4c]	7265	1			T2	18		T17	10		T5	5
valid_sources[0x4d]	7569	1			T4	1		T17	9		T22	5
valid_sources[0x4e]	6994	1			T2	8		T3	11		T17	10
valid_sources[0x4f]	7586	1			T2	12		T17	10		T22	5
valid_sources[0x50]	7631	1			T2	12		T4	2		T17	8
valid_sources[0x51]	6889	1			T2	15		T17	10		T22	5
valid_sources[0x52]	7956	1			T2	2		T4	1		T17	9
valid_sources[0x53]	7545	1			T3	15		T17	11		T22	6
valid_sources[0x54]	7208	1			T3	6		T17	9		T22	5
valid_sources[0x55]	7225	1			T2	5		T17	11		T22	5
valid_sources[0x56]	8597	1			T2	4		T3	19		T17	11
valid_sources[0x57]	7456	1			T2	34		T17	12		T22	6
valid_sources[0x58]	7455	1			T1	4		T2	8		T3	17
valid_sources[0x59]	7185	1			T2	14		T3	18		T17	11
valid_sources[0x5a]	7628	1			T3	9		T4	1		T17	11
valid_sources[0x5b]	7063	1			T2	3		T3	12		T4	2
valid_sources[0x5c]	7418	1			T2	9		T3	5		T4	1
valid_sources[0x5d]	7069	1			T2	6		T17	11		T5	19
valid_sources[0x5e]	7753	1			T3	17		T4	1		T17	11
valid_sources[0x5f]	7374	1			T2	28		T3	17		T4	1
valid_sources[0x60]	7562	1			T2	9		T3	11		T4	2
valid_sources[0x61]	6992	1			T2	7		T3	28		T17	10
valid_sources[0x62]	7351	1			T2	11		T4	2		T17	8
valid_sources[0x63]	7535	1			T2	18		T3	18		T4	1
valid_sources[0x64]	8525	1			T2	13		T17	10		T22	5
valid_sources[0x65]	7346	1			T2	18		T3	33		T4	1
valid_sources[0x66]	6722	1			T2	4		T17	10		T22	6
valid_sources[0x67]	7703	1			T2	13		T3	9		T17	10
valid_sources[0x68]	7736	1			T2	2		T17	10		T22	5
valid_sources[0x69]	7362	1			T2	3		T3	13		T17	10
valid_sources[0x6a]	7456	1			T2	7		T3	14		T17	11
valid_sources[0x6b]	7550	1			T2	21		T17	9		T5	2
valid_sources[0x6c]	7811	1			T2	15		T3	10		T17	10
valid_sources[0x6d]	7910	1			T17	13		T22	6		T20	1
valid_sources[0x6e]	7151	1			T2	1		T17	10		T5	7
valid_sources[0x6f]	7974	1			T2	3		T3	11		T4	1
valid_sources[0x70]	7557	1			T2	23		T17	9		T22	6
valid_sources[0x71]	6897	1			T2	23		T3	5		T17	12
valid_sources[0x72]	6859	1			T2	33		T3	19		T17	10
valid_sources[0x73]	7442	1			T2	6		T4	1		T17	9
valid_sources[0x74]	7766	1			T2	17		T17	10		T22	5
valid_sources[0x75]	7132	1			T2	10		T17	13		T22	6
valid_sources[0x76]	7130	1			T2	14		T17	11		T22	5
valid_sources[0x77]	7370	1			T2	16		T17	10		T22	8
valid_sources[0x78]	7710	1			T2	11		T17	9		T5	10
valid_sources[0x79]	8360	1			T2	4		T4	1		T17	10
valid_sources[0x7a]	6648	1			T2	5		T17	9		T22	5
valid_sources[0x7b]	7658	1			T2	2		T4	2		T17	11
valid_sources[0x7c]	6489	1			T2	6		T4	3		T17	9
valid_sources[0x7d]	7328	1			T2	3		T17	10		T22	5
valid_sources[0x7e]	7691	1			T2	10		T3	13		T17	11
valid_sources[0x7f]	8339	1			T2	19		T3	10		T17	10
valid_sources[0x80]	6942	1			T2	13		T3	5		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27251

1

T1

4

T2

41

T3

26

values[0x0]

all_enables

biggest_size

206547

1

T1

23

T2

293

T3

208

values[0x1]

all_enables

biggest_size

27256

1

T1

3

T2

41

T3

30