Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	334946953	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334946953	0	0
T1	4715256	83629	0	0
T2	274064	12379	0	0
T3	4151280	61027	0	0
T4	158200	2423	0	0
T5	1492400	37539	0	0
T17	12514824	1872697	0	0
T18	0	1219	0	0
T20	40264	811	0	0
T21	0	125554	0	0
T22	6522040	966204	0	0
T23	273448	11889	0	0
T24	12041904	1859304	0	0
T25	0	20089	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4715256	4712512	0	0
T2	274064	273336	0	0
T3	4151280	4150888	0	0
T4	158200	154728	0	0
T5	1492400	1490552	0	0
T17	12514824	12514712	0	0
T20	40264	38416	0	0
T22	6522040	6521816	0	0
T23	273448	270200	0	0
T24	12041904	12041512	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4715256	4712512	0	0
T2	274064	273336	0	0
T3	4151280	4150888	0	0
T4	158200	154728	0	0
T5	1492400	1490552	0	0
T17	12514824	12514712	0	0
T20	40264	38416	0	0
T22	6522040	6521816	0	0
T23	273448	270200	0	0
T24	12041904	12041512	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4715256	4712512	0	0
T2	274064	273336	0	0
T3	4151280	4150888	0	0
T4	158200	154728	0	0
T5	1492400	1490552	0	0
T17	12514824	12514712	0	0
T20	40264	38416	0	0
T22	6522040	6521816	0	0
T23	273448	270200	0	0
T24	12041904	12041512	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T17	56	56	0	0
T20	56	56	0	0
T22	56	56	0	0
T23	56	56	0	0
T24	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	126603913	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	126603913	0	0
T1	84201	81268	0	0
T2	4894	4797	0	0
T3	74130	15713	0	0
T4	2825	1011	0	0
T5	26650	15268	0	0
T17	223479	12973	0	0
T20	719	414	0	0
T22	116465	6311	0	0
T23	4883	4629	0	0
T24	215034	121502	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	83741723	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	83741723	0	0
T1	84201	813	0	0
T2	4894	2528	0	0
T3	74130	14876	0	0
T4	2825	367	0	0
T5	26650	8313	0	0
T17	223479	924283	0	0
T20	719	211	0	0
T22	116465	476792	0	0
T23	4883	2420	0	0
T24	215034	574396	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1563061	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1563061	0	0
T1	84201	46	0	0
T2	4894	102	0	0
T3	74130	602	0	0
T4	2825	26	0	0
T5	26650	318	0	0
T17	223479	0	0	0
T20	719	1	0	0
T21	0	6045	0	0
T22	116465	0	0	0
T23	4883	84	0	0
T24	215034	26613	0	0
T25	0	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2760965	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2760965	0	0
T1	84201	11	0	0
T2	4894	102	0	0
T3	74130	519	0	0
T4	2825	3	0	0
T5	26650	410	0	0
T17	223479	0	0	0
T20	719	1	0	0
T21	0	2699	0	0
T22	116465	0	0	0
T23	4883	84	0	0
T24	215034	23864	0	0
T25	0	1127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1536996	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1536996	0	0
T1	84201	27	0	0
T2	4894	82	0	0
T3	74130	579	0	0
T4	2825	50	0	0
T5	26650	193	0	0
T17	223479	980	0	0
T20	719	4	0	0
T22	116465	0	0	0
T23	4883	80	0	0
T24	215034	21907	0	0
T25	0	387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3002288	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3002288	0	0
T1	84201	6	0	0
T2	4894	82	0	0
T3	74130	589	0	0
T4	2825	9	0	0
T5	26650	145	0	0
T17	223479	77274	0	0
T20	719	4	0	0
T22	116465	0	0	0
T23	4883	80	0	0
T24	215034	19812	0	0
T25	0	155	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1589402	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1589402	0	0
T1	84201	5	0	0
T2	4894	111	0	0
T3	74130	566	0	0
T4	2825	53	0	0
T5	26650	309	0	0
T17	223479	1267	0	0
T20	719	1	0	0
T22	116465	1158	0	0
T23	4883	93	0	0
T24	215034	14307	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3048332	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3048332	0	0
T1	84201	3	0	0
T2	4894	111	0	0
T3	74130	557	0	0
T4	2825	32	0	0
T5	26650	223	0	0
T17	223479	101935	0	0
T20	719	1	0	0
T22	116465	90760	0	0
T23	4883	93	0	0
T24	215034	19364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1553768	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1553768	0	0
T1	84201	38	0	0
T2	4894	100	0	0
T3	74130	509	0	0
T4	2825	21	0	0
T5	26650	243	0	0
T17	223479	1261	0	0
T20	719	5	0	0
T22	116465	1315	0	0
T23	4883	84	0	0
T24	215034	26840	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3143541	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3143541	0	0
T1	84201	6	0	0
T2	4894	100	0	0
T3	74130	486	0	0
T4	2825	33	0	0
T5	26650	287	0	0
T17	223479	95526	0	0
T20	719	5	0	0
T22	116465	105925	0	0
T23	4883	84	0	0
T24	215034	25611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1517255	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1517255	0	0
T1	84201	31	0	0
T2	4894	103	0	0
T3	74130	573	0	0
T4	2825	0	0	0
T5	26650	203	0	0
T17	223479	0	0	0
T18	0	611	0	0
T20	719	3	0	0
T21	0	4917	0	0
T22	116465	0	0	0
T23	4883	104	0	0
T24	215034	16078	0	0
T25	0	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2667820	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2667820	0	0
T1	84201	6	0	0
T2	4894	103	0	0
T3	74130	563	0	0
T4	2825	0	0	0
T5	26650	273	0	0
T17	223479	0	0	0
T18	0	608	0	0
T20	719	3	0	0
T21	0	2332	0	0
T22	116465	0	0	0
T23	4883	104	0	0
T24	215034	17340	0	0
T25	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1568338	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1568338	0	0
T1	84201	28	0	0
T2	4894	92	0	0
T3	74130	644	0	0
T4	2825	18	0	0
T5	26650	330	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	5855	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	25194	0	0
T25	0	416	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3114209	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3114209	0	0
T1	84201	5	0	0
T2	4894	92	0	0
T3	74130	644	0	0
T4	2825	9	0	0
T5	26650	368	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	2440	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	23539	0	0
T25	0	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1505341	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1505341	0	0
T1	84201	52	0	0
T2	4894	85	0	0
T3	74130	472	0	0
T4	2825	24	0	0
T5	26650	252	0	0
T17	223479	0	0	0
T20	719	6	0	0
T21	0	7206	0	0
T22	116465	0	0	0
T23	4883	108	0	0
T24	215034	23849	0	0
T25	0	374	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2847464	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2847464	0	0
T1	84201	8	0	0
T2	4894	85	0	0
T3	74130	458	0	0
T4	2825	5	0	0
T5	26650	288	0	0
T17	223479	0	0	0
T20	719	6	0	0
T21	0	3429	0	0
T22	116465	0	0	0
T23	4883	108	0	0
T24	215034	17651	0	0
T25	0	80	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1608863	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1608863	0	0
T1	84201	11	0	0
T2	4894	82	0	0
T3	74130	574	0	0
T4	2825	12	0	0
T5	26650	314	0	0
T17	223479	0	0	0
T20	719	1	0	0
T21	0	6079	0	0
T22	116465	0	0	0
T23	4883	91	0	0
T24	215034	31630	0	0
T25	0	355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3026627	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3026627	0	0
T1	84201	3	0	0
T2	4894	82	0	0
T3	74130	598	0	0
T4	2825	9	0	0
T5	26650	206	0	0
T17	223479	0	0	0
T20	719	1	0	0
T21	0	2661	0	0
T22	116465	0	0	0
T23	4883	91	0	0
T24	215034	28179	0	0
T25	0	458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1545388	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1545388	0	0
T1	84201	12	0	0
T2	4894	95	0	0
T3	74130	670	0	0
T4	2825	5	0	0
T5	26650	260	0	0
T17	223479	0	0	0
T20	719	5	0	0
T22	116465	1245	0	0
T23	4883	89	0	0
T24	215034	14895	0	0
T25	0	454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2668002	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2668002	0	0
T1	84201	4	0	0
T2	4894	95	0	0
T3	74130	602	0	0
T4	2825	7	0	0
T5	26650	197	0	0
T17	223479	0	0	0
T20	719	5	0	0
T22	116465	92204	0	0
T23	4883	89	0	0
T24	215034	18477	0	0
T25	0	972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1538683	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1538683	0	0
T1	84201	32	0	0
T2	4894	99	0	0
T3	74130	559	0	0
T4	2825	12	0	0
T5	26650	182	0	0
T17	223479	1172	0	0
T20	719	8	0	0
T22	116465	0	0	0
T23	4883	76	0	0
T24	215034	28114	0	0
T25	0	393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2724967	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2724967	0	0
T1	84201	6	0	0
T2	4894	99	0	0
T3	74130	564	0	0
T4	2825	13	0	0
T5	26650	126	0	0
T17	223479	86877	0	0
T20	719	8	0	0
T22	116465	0	0	0
T23	4883	76	0	0
T24	215034	27519	0	0
T25	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1573684	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1573684	0	0
T1	84201	24	0	0
T2	4894	70	0	0
T3	74130	397	0	0
T4	2825	29	0	0
T5	26650	317	0	0
T17	223479	1320	0	0
T20	719	7	0	0
T22	116465	1256	0	0
T23	4883	75	0	0
T24	215034	18996	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2909592	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2909592	0	0
T1	84201	4	0	0
T2	4894	70	0	0
T3	74130	487	0	0
T4	2825	22	0	0
T5	26650	344	0	0
T17	223479	105906	0	0
T20	719	7	0	0
T22	116465	93583	0	0
T23	4883	75	0	0
T24	215034	15647	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1615536	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1615536	0	0
T1	84201	24	0	0
T2	4894	93	0	0
T3	74130	678	0	0
T4	2825	25	0	0
T5	26650	282	0	0
T17	223479	0	0	0
T20	719	4	0	0
T21	0	3829	0	0
T22	116465	0	0	0
T23	4883	89	0	0
T24	215034	19889	0	0
T25	0	435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2880877	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2880877	0	0
T1	84201	5	0	0
T2	4894	93	0	0
T3	74130	548	0	0
T4	2825	9	0	0
T5	26650	290	0	0
T17	223479	0	0	0
T20	719	4	0	0
T21	0	1551	0	0
T22	116465	0	0	0
T23	4883	89	0	0
T24	215034	20002	0	0
T25	0	1244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1526647	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1526647	0	0
T1	84201	25	0	0
T2	4894	121	0	0
T3	74130	591	0	0
T4	2825	49	0	0
T5	26650	176	0	0
T17	223479	1269	0	0
T20	719	3	0	0
T22	116465	0	0	0
T23	4883	80	0	0
T24	215034	25121	0	0
T25	0	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2553456	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2553456	0	0
T1	84201	6	0	0
T2	4894	121	0	0
T3	74130	678	0	0
T4	2825	26	0	0
T5	26650	171	0	0
T17	223479	89850	0	0
T20	719	3	0	0
T22	116465	0	0	0
T23	4883	80	0	0
T24	215034	26746	0	0
T25	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1543444	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1543444	0	0
T1	84201	15	0	0
T2	4894	101	0	0
T3	74130	678	0	0
T4	2825	39	0	0
T5	26650	284	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	5463	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	19922	0	0
T25	0	418	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2737887	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2737887	0	0
T1	84201	5	0	0
T2	4894	101	0	0
T3	74130	517	0	0
T4	2825	22	0	0
T5	26650	218	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	2105	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	20885	0	0
T25	0	643	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1621129	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1621129	0	0
T1	84201	26	0	0
T2	4894	79	0	0
T3	74130	579	0	0
T4	2825	5	0	0
T5	26650	250	0	0
T17	223479	2387	0	0
T20	719	6	0	0
T22	116465	0	0	0
T23	4883	122	0	0
T24	215034	18357	0	0
T25	0	421	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2761521	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2761521	0	0
T1	84201	656	0	0
T2	4894	79	0	0
T3	74130	593	0	0
T4	2825	5	0	0
T5	26650	284	0	0
T17	223479	182151	0	0
T20	719	6	0	0
T22	116465	0	0	0
T23	4883	122	0	0
T24	215034	18878	0	0
T25	0	167	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1535045	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1535045	0	0
T1	84201	5	0	0
T2	4894	112	0	0
T3	74130	660	0	0
T4	2825	9	0	0
T5	26650	305	0	0
T17	223479	0	0	0
T20	719	4	0	0
T21	0	9345	0	0
T22	116465	0	0	0
T23	4883	98	0	0
T24	215034	22810	0	0
T25	0	401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3322973	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3322973	0	0
T1	84201	2	0	0
T2	4894	112	0	0
T3	74130	588	0	0
T4	2825	15	0	0
T5	26650	255	0	0
T17	223479	0	0	0
T20	719	4	0	0
T21	0	3918	0	0
T22	116465	0	0	0
T23	4883	98	0	0
T24	215034	18335	0	0
T25	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1542688	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1542688	0	0
T1	84201	20	0	0
T2	4894	94	0	0
T3	74130	601	0	0
T4	2825	33	0	0
T5	26650	298	0	0
T17	223479	1172	0	0
T20	719	2	0	0
T22	116465	0	0	0
T23	4883	92	0	0
T24	215034	14780	0	0
T25	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3312264	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3312264	0	0
T1	84201	7	0	0
T2	4894	94	0	0
T3	74130	471	0	0
T4	2825	37	0	0
T5	26650	306	0	0
T17	223479	91080	0	0
T20	719	2	0	0
T22	116465	0	0	0
T23	4883	92	0	0
T24	215034	17017	0	0
T25	0	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1563221	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1563221	0	0
T1	84201	51	0	0
T2	4894	78	0	0
T3	74130	678	0	0
T4	2825	15	0	0
T5	26650	334	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	3809	0	0
T22	116465	0	0	0
T23	4883	75	0	0
T24	215034	25485	0	0
T25	0	576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3582530	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3582530	0	0
T1	84201	8	0	0
T2	4894	78	0	0
T3	74130	681	0	0
T4	2825	8	0	0
T5	26650	253	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	1640	0	0
T22	116465	0	0	0
T23	4883	75	0	0
T24	215034	24813	0	0
T25	0	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1572790	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1572790	0	0
T1	84201	35	0	0
T2	4894	84	0	0
T3	74130	709	0	0
T4	2825	17	0	0
T5	26650	258	0	0
T17	223479	0	0	0
T20	719	5	0	0
T21	0	5592	0	0
T22	116465	0	0	0
T23	4883	79	0	0
T24	215034	12990	0	0
T25	0	538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3155525	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3155525	0	0
T1	84201	8	0	0
T2	4894	84	0	0
T3	74130	678	0	0
T4	2825	3	0	0
T5	26650	279	0	0
T17	223479	0	0	0
T20	719	5	0	0
T21	0	2553	0	0
T22	116465	0	0	0
T23	4883	79	0	0
T24	215034	12972	0	0
T25	0	124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1586105	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1586105	0	0
T1	84201	47	0	0
T2	4894	94	0	0
T3	74130	505	0	0
T4	2825	37	0	0
T5	26650	351	0	0
T17	223479	0	0	0
T20	719	5	0	0
T21	0	3648	0	0
T22	116465	0	0	0
T23	4883	87	0	0
T24	215034	24267	0	0
T25	0	499	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	4580220	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	4580220	0	0
T1	84201	11	0	0
T2	4894	94	0	0
T3	74130	530	0	0
T4	2825	7	0	0
T5	26650	264	0	0
T17	223479	0	0	0
T20	719	5	0	0
T21	0	1538	0	0
T22	116465	0	0	0
T23	4883	87	0	0
T24	215034	21212	0	0
T25	0	621	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1536796	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1536796	0	0
T1	84201	37	0	0
T2	4894	98	0	0
T3	74130	447	0	0
T4	2825	37	0	0
T5	26650	235	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	3637	0	0
T22	116465	0	0	0
T23	4883	76	0	0
T24	215034	17730	0	0
T25	0	407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3473992	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3473992	0	0
T1	84201	9	0	0
T2	4894	98	0	0
T3	74130	388	0	0
T4	2825	28	0	0
T5	26650	229	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	1471	0	0
T22	116465	0	0	0
T23	4883	76	0	0
T24	215034	19080	0	0
T25	0	212	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1525733	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1525733	0	0
T1	84201	32	0	0
T2	4894	97	0	0
T3	74130	477	0	0
T4	2825	50	0	0
T5	26650	224	0	0
T17	223479	1242	0	0
T20	719	0	0	0
T21	0	3724	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	22986	0	0
T25	0	460	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3090499	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3090499	0	0
T1	84201	8	0	0
T2	4894	97	0	0
T3	74130	325	0	0
T4	2825	15	0	0
T5	26650	186	0	0
T17	223479	92772	0	0
T20	719	0	0	0
T21	0	1607	0	0
T22	116465	0	0	0
T23	4883	90	0	0
T24	215034	23428	0	0
T25	0	506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1544796	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1544796	0	0
T1	84201	20	0	0
T2	4894	95	0	0
T3	74130	613	0	0
T4	2825	41	0	0
T5	26650	207	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	5830	0	0
T22	116465	0	0	0
T23	4883	95	0	0
T24	215034	20903	0	0
T25	0	457	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2876622	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2876622	0	0
T1	84201	6	0	0
T2	4894	95	0	0
T3	74130	604	0	0
T4	2825	20	0	0
T5	26650	209	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	2506	0	0
T22	116465	0	0	0
T23	4883	95	0	0
T24	215034	23515	0	0
T25	0	763	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1569971	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1569971	0	0
T1	84201	27	0	0
T2	4894	88	0	0
T3	74130	581	0	0
T4	2825	3	0	0
T5	26650	276	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	3999	0	0
T22	116465	0	0	0
T23	4883	79	0	0
T24	215034	23451	0	0
T25	0	437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3023268	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3023268	0	0
T1	84201	5	0	0
T2	4894	88	0	0
T3	74130	411	0	0
T4	2825	10	0	0
T5	26650	256	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	1530	0	0
T22	116465	0	0	0
T23	4883	79	0	0
T24	215034	20124	0	0
T25	0	891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1560243	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1560243	0	0
T1	84201	28	0	0
T2	4894	90	0	0
T3	74130	640	0	0
T4	2825	26	0	0
T5	26650	231	0	0
T17	223479	0	0	0
T20	719	3	0	0
T22	116465	1336	0	0
T23	4883	86	0	0
T24	215034	25979	0	0
T25	0	410	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2911014	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2911014	0	0
T1	84201	5	0	0
T2	4894	90	0	0
T3	74130	640	0	0
T4	2825	13	0	0
T5	26650	249	0	0
T17	223479	0	0	0
T20	719	3	0	0
T22	116465	94319	0	0
T23	4883	86	0	0
T24	215034	21105	0	0
T25	0	576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1490822	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1490822	0	0
T1	84201	27	0	0
T2	4894	99	0	0
T3	74130	553	0	0
T4	2825	12	0	0
T5	26650	309	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	4841	0	0
T22	116465	0	0	0
T23	4883	91	0	0
T24	215034	19589	0	0
T25	0	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	2824645	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	2824645	0	0
T1	84201	5	0	0
T2	4894	99	0	0
T3	74130	511	0	0
T4	2825	5	0	0
T5	26650	234	0	0
T17	223479	0	0	0
T20	719	3	0	0
T21	0	2423	0	0
T22	116465	0	0	0
T23	4883	91	0	0
T24	215034	20580	0	0
T25	0	439	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	1608849	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	1608849	0	0
T1	84201	10	0	0
T2	4894	83	0	0
T3	74130	567	0	0
T4	2825	30	0	0
T5	26650	250	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	3780	0	0
T22	116465	0	0	0
T23	4883	117	0	0
T24	215034	26910	0	0
T25	0	422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	300967993	3555623	0	0
DepthKnown_A	300967993	300842821	0	0
RvalidKnown_A	300967993	300842821	0	0
WreadyKnown_A	300967993	300842821	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	3555623	0	0
T1	84201	5	0	0
T2	4894	83	0	0
T3	74130	506	0	0
T4	2825	2	0	0
T5	26650	217	0	0
T17	223479	0	0	0
T20	719	2	0	0
T21	0	1552	0	0
T22	116465	0	0	0
T23	4883	117	0	0
T24	215034	28119	0	0
T25	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300967993	300842821	0	0
T1	84201	84152	0	0
T2	4894	4881	0	0
T3	74130	74123	0	0
T4	2825	2763	0	0
T5	26650	26617	0	0
T17	223479	223477	0	0
T20	719	686	0	0
T22	116465	116461	0	0
T23	4883	4825	0	0
T24	215034	215027	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0