Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1620882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254433

1

T1

55

T2

172

T3

157

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	636265	1			T1	116		T2	372		T3	373
values[0x0]	603305	1			T1	103		T2	419		T3	382
values[0x1]	635745	1			T1	92		T2	405		T3	366

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1254752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

620563

1

T1

123

T2

406

T3

356

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6723	1			T2	5		T20	8		T18	2
valid_sources[0x01]	7488	1			T2	4		T20	9		T19	4
valid_sources[0x02]	7444	1			T2	5		T20	7		T18	2
valid_sources[0x03]	7748	1			T2	4		T20	7		T18	1
valid_sources[0x04]	7041	1			T2	4		T20	8		T18	2
valid_sources[0x05]	6819	1			T2	5		T20	9		T18	3
valid_sources[0x06]	7584	1			T2	5		T20	8		T22	2
valid_sources[0x07]	8236	1			T2	5		T20	9		T18	1
valid_sources[0x08]	7360	1			T2	5		T20	9		T19	56
valid_sources[0x09]	7942	1			T2	5		T20	8		T18	2
valid_sources[0x0a]	6412	1			T2	5		T20	10		T22	1
valid_sources[0x0b]	6989	1			T2	4		T20	9		T19	31
valid_sources[0x0c]	7150	1			T2	2		T20	8		T18	2
valid_sources[0x0d]	7065	1			T2	4		T20	9		T22	1
valid_sources[0x0e]	7139	1			T2	5		T20	9		T18	3
valid_sources[0x0f]	7787	1			T2	5		T20	8		T18	1
valid_sources[0x10]	6689	1			T2	4		T20	9		T22	1
valid_sources[0x11]	7413	1			T2	4		T20	8		T18	1
valid_sources[0x12]	10040	1			T2	5		T20	10		T18	2
valid_sources[0x13]	8746	1			T2	4		T20	9		T21	3
valid_sources[0x14]	7613	1			T2	4		T20	10		T18	1
valid_sources[0x15]	7385	1			T2	6		T16	114		T20	10
valid_sources[0x16]	7447	1			T2	5		T20	8		T18	1
valid_sources[0x17]	6607	1			T2	5		T20	5		T18	1
valid_sources[0x18]	6828	1			T2	5		T20	9		T22	2
valid_sources[0x19]	6900	1			T2	5		T20	8		T18	2
valid_sources[0x1a]	6888	1			T2	4		T20	8		T18	1
valid_sources[0x1b]	7205	1			T1	72		T2	3		T20	9
valid_sources[0x1c]	6631	1			T2	4		T4	19		T20	9
valid_sources[0x1d]	7639	1			T2	5		T20	8		T18	1
valid_sources[0x1e]	7147	1			T2	5		T16	58		T20	9
valid_sources[0x1f]	7009	1			T2	4		T20	9		T18	1
valid_sources[0x20]	8207	1			T2	5		T20	9		T19	81
valid_sources[0x21]	7141	1			T2	4		T20	8		T18	1
valid_sources[0x22]	6742	1			T2	5		T20	7		T18	3
valid_sources[0x23]	7110	1			T2	5		T20	9		T21	1
valid_sources[0x24]	7721	1			T2	5		T20	9		T22	1
valid_sources[0x25]	7045	1			T2	5		T20	9		T19	16
valid_sources[0x26]	6878	1			T2	5		T20	8		T21	1
valid_sources[0x27]	7950	1			T1	4		T2	5		T20	10
valid_sources[0x28]	7482	1			T2	5		T20	9		T22	1
valid_sources[0x29]	7312	1			T2	5		T20	8		T18	3
valid_sources[0x2a]	6245	1			T2	5		T20	6		T18	2
valid_sources[0x2b]	7458	1			T2	4		T20	9		T21	10
valid_sources[0x2c]	6634	1			T2	6		T20	7		T18	2
valid_sources[0x2d]	6656	1			T2	4		T20	8		T21	1
valid_sources[0x2e]	8482	1			T2	6		T20	8		T18	1
valid_sources[0x2f]	7113	1			T2	5		T16	96		T20	9
valid_sources[0x30]	6836	1			T2	4		T20	8		T18	2
valid_sources[0x31]	7088	1			T2	5		T20	9		T19	52
valid_sources[0x32]	6788	1			T2	5		T16	54		T20	7
valid_sources[0x33]	7291	1			T2	4		T3	17		T20	10
valid_sources[0x34]	7393	1			T2	4		T20	8		T17	2
valid_sources[0x35]	6254	1			T2	5		T20	9		T17	1
valid_sources[0x36]	6993	1			T2	5		T16	61		T20	9
valid_sources[0x37]	7367	1			T2	5		T20	8		T18	2
valid_sources[0x38]	7343	1			T2	6		T20	8		T22	1
valid_sources[0x39]	7433	1			T2	4		T20	9		T18	2
valid_sources[0x3a]	7100	1			T2	3		T20	9		T18	2
valid_sources[0x3b]	8340	1			T2	5		T20	9		T21	3
valid_sources[0x3c]	7136	1			T2	5		T20	8		T22	1
valid_sources[0x3d]	7448	1			T2	5		T20	9		T18	2
valid_sources[0x3e]	7742	1			T2	5		T20	8		T18	1
valid_sources[0x3f]	7095	1			T2	5		T20	9		T18	2
valid_sources[0x40]	6645	1			T2	5		T20	10		T21	1
valid_sources[0x41]	7567	1			T2	5		T20	8		T18	1
valid_sources[0x42]	6824	1			T2	3		T20	9		T19	24
valid_sources[0x43]	7125	1			T2	3		T20	8		T22	2
valid_sources[0x44]	7765	1			T2	5		T16	25		T20	7
valid_sources[0x45]	7314	1			T2	5		T4	8		T20	8
valid_sources[0x46]	7003	1			T2	4		T20	8		T18	1
valid_sources[0x47]	6834	1			T2	5		T20	7		T22	1
valid_sources[0x48]	7842	1			T2	7		T20	8		T21	22
valid_sources[0x49]	6752	1			T2	5		T20	9		T17	13
valid_sources[0x4a]	6837	1			T2	4		T20	7		T18	2
valid_sources[0x4b]	6458	1			T2	5		T20	8		T18	3
valid_sources[0x4c]	7896	1			T2	5		T20	8		T19	90
valid_sources[0x4d]	7233	1			T2	5		T20	7		T19	36
valid_sources[0x4e]	7123	1			T2	4		T20	6		T22	1
valid_sources[0x4f]	7719	1			T2	4		T20	7		T17	1
valid_sources[0x50]	7679	1			T2	5		T20	8		T18	5
valid_sources[0x51]	7865	1			T2	5		T20	9		T18	1
valid_sources[0x52]	6711	1			T2	4		T20	9		T22	1
valid_sources[0x53]	6673	1			T2	5		T16	1		T20	9
valid_sources[0x54]	6779	1			T2	4		T3	73		T20	9
valid_sources[0x55]	7021	1			T2	5		T20	9		T17	11
valid_sources[0x56]	6629	1			T2	5		T20	9		T19	20
valid_sources[0x57]	6870	1			T2	4		T20	9		T18	1
valid_sources[0x58]	7666	1			T2	4		T20	8		T18	1
valid_sources[0x59]	6934	1			T2	4		T3	89		T20	8
valid_sources[0x5a]	6502	1			T2	5		T20	8		T19	21
valid_sources[0x5b]	6794	1			T2	4		T20	9		T18	2
valid_sources[0x5c]	8955	1			T2	4		T16	35		T20	8
valid_sources[0x5d]	7645	1			T2	5		T20	8		T18	1
valid_sources[0x5e]	7278	1			T2	5		T20	9		T18	1
valid_sources[0x5f]	7485	1			T2	5		T20	9		T18	2
valid_sources[0x60]	7039	1			T1	21		T2	5		T20	8
valid_sources[0x61]	6918	1			T2	5		T20	7		T18	2
valid_sources[0x62]	8640	1			T2	6		T20	9		T18	1
valid_sources[0x63]	8063	1			T2	5		T20	9		T18	2
valid_sources[0x64]	6651	1			T2	4		T20	8		T22	1
valid_sources[0x65]	8025	1			T2	5		T20	9		T21	3
valid_sources[0x66]	6861	1			T2	5		T16	117		T20	7
valid_sources[0x67]	6990	1			T2	4		T20	8		T18	2
valid_sources[0x68]	7802	1			T2	4		T20	8		T18	1
valid_sources[0x69]	7356	1			T2	4		T20	9		T22	1
valid_sources[0x6a]	7358	1			T2	6		T20	8		T18	1
valid_sources[0x6b]	7708	1			T2	5		T4	11		T20	8
valid_sources[0x6c]	6630	1			T2	5		T20	7		T19	61
valid_sources[0x6d]	7007	1			T2	5		T20	9		T18	1
valid_sources[0x6e]	7150	1			T2	5		T20	9		T22	1
valid_sources[0x6f]	7020	1			T2	4		T3	60		T20	8
valid_sources[0x70]	7480	1			T2	5		T20	11		T19	46
valid_sources[0x71]	7931	1			T2	4		T3	159		T20	9
valid_sources[0x72]	7291	1			T2	4		T20	9		T18	2
valid_sources[0x73]	6845	1			T2	5		T20	8		T18	1
valid_sources[0x74]	8701	1			T2	4		T20	9		T18	1
valid_sources[0x75]	7810	1			T2	5		T20	8		T18	1
valid_sources[0x76]	6645	1			T2	5		T20	9		T18	2
valid_sources[0x77]	8381	1			T2	5		T20	9		T18	2
valid_sources[0x78]	7507	1			T2	5		T20	8		T21	8
valid_sources[0x79]	8048	1			T2	4		T20	8		T21	7
valid_sources[0x7a]	7502	1			T2	5		T20	8		T18	3
valid_sources[0x7b]	7559	1			T2	4		T20	9		T21	11
valid_sources[0x7c]	8531	1			T2	4		T20	8		T17	34
valid_sources[0x7d]	7127	1			T2	4		T20	7		T21	13
valid_sources[0x7e]	7442	1			T2	5		T4	10		T20	8
valid_sources[0x7f]	7086	1			T2	5		T20	8		T18	2
valid_sources[0x80]	6998	1			T2	5		T20	8		T17	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27083

1

T1

10

T2

16

T3

14

values[0x0]

all_enables

biggest_size

200310

1

T1

42

T2

143

T3

123

values[0x1]

all_enables

biggest_size

27040

1

T1

3

T2

13

T3

20