Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	345767283	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345767283	0	0
T1	42168	1516	0	0
T2	6593664	907362	0	0
T3	124040	5502	0	0
T4	271656	5907	0	0
T16	1360744	26135	0	0
T17	1525664	71032	0	0
T18	11552408	260905	0	0
T19	0	150526	0	0
T20	11638480	1594264	0	0
T21	10375904	198500	0	0
T22	26320	888	0	0
T23	0	1278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42168	40712	0	0
T2	6593664	6593496	0	0
T3	124040	123648	0	0
T4	271656	267904	0	0
T16	1360744	1359792	0	0
T17	1525664	1518944	0	0
T18	11552408	11549496	0	0
T20	11638480	11638200	0	0
T21	10375904	10371816	0	0
T22	26320	25480	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42168	40712	0	0
T2	6593664	6593496	0	0
T3	124040	123648	0	0
T4	271656	267904	0	0
T16	1360744	1359792	0	0
T17	1525664	1518944	0	0
T18	11552408	11549496	0	0
T20	11638480	11638200	0	0
T21	10375904	10371816	0	0
T22	26320	25480	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	42168	40712	0	0
T2	6593664	6593496	0	0
T3	124040	123648	0	0
T4	271656	267904	0	0
T16	1360744	1359792	0	0
T17	1525664	1518944	0	0
T18	11552408	11549496	0	0
T20	11638480	11638200	0	0
T21	10375904	10371816	0	0
T22	26320	25480	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0
T22	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	131992152	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	131992152	0	0
T1	753	583	0	0
T2	117744	5454	0	0
T3	2215	2139	0	0
T4	4851	2349	0	0
T16	24299	11638	0	0
T17	27244	25738	0	0
T18	206293	106925	0	0
T20	207830	9530	0	0
T21	185284	88358	0	0
T22	470	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	87124172	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	87124172	0	0
T1	753	311	0	0
T2	117744	448228	0	0
T3	2215	1121	0	0
T4	4851	1182	0	0
T16	24299	3346	0	0
T17	27244	15440	0	0
T18	206293	51253	0	0
T20	207830	787604	0	0
T21	185284	24657	0	0
T22	470	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1513619	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1513619	0	0
T1	753	8	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	76	0	0
T16	24299	217	0	0
T17	27244	533	0	0
T18	206293	1209	0	0
T19	0	1728	0	0
T20	207830	1154	0	0
T21	185284	1811	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3763429	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3763429	0	0
T1	753	8	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	70	0	0
T16	24299	108	0	0
T17	27244	533	0	0
T18	206293	1122	0	0
T19	0	1608	0	0
T20	207830	96386	0	0
T21	185284	1841	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1470963	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1470963	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	39	0	0
T4	4851	26	0	0
T16	24299	295	0	0
T17	27244	1078	0	0
T18	206293	1339	0	0
T19	0	3645	0	0
T20	207830	0	0	0
T21	185284	1475	0	0
T22	470	2	0	0
T23	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2630126	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2630126	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	39	0	0
T4	4851	26	0	0
T16	24299	154	0	0
T17	27244	1078	0	0
T18	206293	1418	0	0
T19	0	3740	0	0
T20	207830	0	0	0
T21	185284	197	0	0
T22	470	2	0	0
T23	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1505081	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1505081	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	29	0	0
T4	4851	62	0	0
T16	24299	368	0	0
T17	27244	509	0	0
T18	206293	1309	0	0
T19	0	1581	0	0
T20	207830	892	0	0
T21	185284	1618	0	0
T22	470	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3579322	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3579322	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	29	0	0
T4	4851	26	0	0
T16	24299	136	0	0
T17	27244	509	0	0
T18	206293	1260	0	0
T19	0	1795	0	0
T20	207830	81125	0	0
T21	185284	1521	0	0
T22	470	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1549176	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1549176	0	0
T1	753	10	0	0
T2	117744	939	0	0
T3	2215	36	0	0
T4	4851	63	0	0
T16	24299	483	0	0
T17	27244	531	0	0
T18	206293	3364	0	0
T19	0	3729	0	0
T20	207830	0	0	0
T21	185284	627	0	0
T22	470	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2613085	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2613085	0	0
T1	753	10	0	0
T2	117744	79965	0	0
T3	2215	36	0	0
T4	4851	58	0	0
T16	24299	179	0	0
T17	27244	531	0	0
T18	206293	3406	0	0
T19	0	3873	0	0
T20	207830	0	0	0
T21	185284	56	0	0
T22	470	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1583858	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1583858	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	39	0	0
T4	4851	24	0	0
T16	24299	213	0	0
T17	27244	562	0	0
T18	206293	1285	0	0
T19	0	1329	0	0
T20	207830	0	0	0
T21	185284	1564	0	0
T22	470	8	0	0
T23	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3093581	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3093581	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	39	0	0
T4	4851	37	0	0
T16	24299	140	0	0
T17	27244	562	0	0
T18	206293	1196	0	0
T19	0	1582	0	0
T20	207830	0	0	0
T21	185284	711	0	0
T22	470	8	0	0
T23	0	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1537307	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1537307	0	0
T1	753	18	0	0
T2	117744	1141	0	0
T3	2215	37	0	0
T4	4851	25	0	0
T16	24299	246	0	0
T17	27244	824	0	0
T18	206293	1540	0	0
T20	207830	2092	0	0
T21	185284	1578	0	0
T22	470	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3703286	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3703286	0	0
T1	753	18	0	0
T2	117744	92913	0	0
T3	2215	37	0	0
T4	4851	42	0	0
T16	24299	78	0	0
T17	27244	824	0	0
T18	206293	1317	0	0
T20	207830	169287	0	0
T21	185284	559	0	0
T22	470	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1480082	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1480082	0	0
T1	753	15	0	0
T2	117744	0	0	0
T3	2215	41	0	0
T4	4851	38	0	0
T16	24299	302	0	0
T17	27244	802	0	0
T18	206293	1137	0	0
T19	0	1513	0	0
T20	207830	0	0	0
T21	185284	3389	0	0
T22	470	9	0	0
T23	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2730066	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2730066	0	0
T1	753	15	0	0
T2	117744	0	0	0
T3	2215	41	0	0
T4	4851	37	0	0
T16	24299	119	0	0
T17	27244	802	0	0
T18	206293	1181	0	0
T19	0	1651	0	0
T20	207830	0	0	0
T21	185284	2076	0	0
T22	470	9	0	0
T23	0	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1496621	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1496621	0	0
T1	753	5	0	0
T2	117744	0	0	0
T3	2215	47	0	0
T4	4851	32	0	0
T16	24299	240	0	0
T17	27244	753	0	0
T18	206293	1405	0	0
T19	0	3379	0	0
T20	207830	1193	0	0
T21	185284	2173	0	0
T22	470	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3566962	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3566962	0	0
T1	753	5	0	0
T2	117744	0	0	0
T3	2215	47	0	0
T4	4851	30	0	0
T16	24299	114	0	0
T17	27244	753	0	0
T18	206293	1284	0	0
T19	0	3556	0	0
T20	207830	105088	0	0
T21	185284	871	0	0
T22	470	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1469344	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1469344	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	53	0	0
T4	4851	30	0	0
T16	24299	292	0	0
T17	27244	302	0	0
T18	206293	1187	0	0
T19	0	1748	0	0
T20	207830	0	0	0
T21	185284	940	0	0
T22	470	7	0	0
T23	0	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2537316	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2537316	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	53	0	0
T4	4851	48	0	0
T16	24299	187	0	0
T17	27244	302	0	0
T18	206293	1338	0	0
T19	0	1738	0	0
T20	207830	0	0	0
T21	185284	1030	0	0
T22	470	7	0	0
T23	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1471393	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1471393	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	52	0	0
T16	24299	226	0	0
T17	27244	534	0	0
T18	206293	1372	0	0
T19	0	3572	0	0
T20	207830	0	0	0
T21	185284	589	0	0
T22	470	6	0	0
T23	0	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3059103	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3059103	0	0
T1	753	7	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	53	0	0
T16	24299	102	0	0
T17	27244	534	0	0
T18	206293	1253	0	0
T19	0	3833	0	0
T20	207830	0	0	0
T21	185284	3	0	0
T22	470	6	0	0
T23	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1465302	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1465302	0	0
T1	753	21	0	0
T2	117744	0	0	0
T3	2215	32	0	0
T4	4851	38	0	0
T16	24299	272	0	0
T17	27244	701	0	0
T18	206293	1319	0	0
T19	0	1746	0	0
T20	207830	2168	0	0
T21	185284	5148	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3306225	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3306225	0	0
T1	753	21	0	0
T2	117744	0	0	0
T3	2215	32	0	0
T4	4851	50	0	0
T16	24299	138	0	0
T17	27244	701	0	0
T18	206293	1366	0	0
T19	0	1770	0	0
T20	207830	165525	0	0
T21	185284	1696	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1507901	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1507901	0	0
T1	753	14	0	0
T2	117744	0	0	0
T3	2215	30	0	0
T4	4851	46	0	0
T16	24299	306	0	0
T17	27244	500	0	0
T18	206293	2723	0	0
T19	0	3298	0	0
T20	207830	0	0	0
T21	185284	1224	0	0
T22	470	10	0	0
T23	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3678752	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3678752	0	0
T1	753	14	0	0
T2	117744	0	0	0
T3	2215	30	0	0
T4	4851	57	0	0
T16	24299	137	0	0
T17	27244	500	0	0
T18	206293	2754	0	0
T19	0	3280	0	0
T20	207830	0	0	0
T21	185284	522	0	0
T22	470	10	0	0
T23	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1542784	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1542784	0	0
T1	753	13	0	0
T2	117744	0	0	0
T3	2215	44	0	0
T4	4851	36	0	0
T16	24299	254	0	0
T17	27244	773	0	0
T18	206293	1342	0	0
T19	0	1731	0	0
T20	207830	0	0	0
T21	185284	2672	0	0
T22	470	5	0	0
T23	0	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2892394	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2892394	0	0
T1	753	13	0	0
T2	117744	0	0	0
T3	2215	44	0	0
T4	4851	43	0	0
T16	24299	104	0	0
T17	27244	773	0	0
T18	206293	1195	0	0
T19	0	1919	0	0
T20	207830	0	0	0
T21	185284	675	0	0
T22	470	5	0	0
T23	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1482907	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1482907	0	0
T1	753	18	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	30	0	0
T16	24299	280	0	0
T17	27244	471	0	0
T18	206293	1516	0	0
T19	0	1637	0	0
T20	207830	0	0	0
T21	185284	1395	0	0
T22	470	6	0	0
T23	0	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2441848	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2441848	0	0
T1	753	18	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	24	0	0
T16	24299	150	0	0
T17	27244	471	0	0
T18	206293	1578	0	0
T19	0	1699	0	0
T20	207830	0	0	0
T21	185284	140	0	0
T22	470	6	0	0
T23	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1504546	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1504546	0	0
T1	753	10	0	0
T2	117744	0	0	0
T3	2215	34	0	0
T4	4851	60	0	0
T16	24299	326	0	0
T17	27244	513	0	0
T18	206293	1476	0	0
T19	0	6057	0	0
T20	207830	0	0	0
T21	185284	3075	0	0
T22	470	11	0	0
T23	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3404585	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3404585	0	0
T1	753	10	0	0
T2	117744	0	0	0
T3	2215	34	0	0
T4	4851	66	0	0
T16	24299	104	0	0
T17	27244	513	0	0
T18	206293	1384	0	0
T19	0	6068	0	0
T20	207830	0	0	0
T21	185284	1132	0	0
T22	470	11	0	0
T23	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1431843	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1431843	0	0
T1	753	9	0	0
T2	117744	0	0	0
T3	2215	43	0	0
T4	4851	52	0	0
T16	24299	349	0	0
T17	27244	287	0	0
T18	206293	2525	0	0
T19	0	1517	0	0
T20	207830	0	0	0
T21	185284	2766	0	0
T22	470	7	0	0
T23	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3040408	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3040408	0	0
T1	753	9	0	0
T2	117744	0	0	0
T3	2215	43	0	0
T4	4851	47	0	0
T16	24299	107	0	0
T17	27244	287	0	0
T18	206293	2497	0	0
T19	0	1492	0	0
T20	207830	0	0	0
T21	185284	1143	0	0
T22	470	7	0	0
T23	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1484321	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1484321	0	0
T1	753	14	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	48	0	0
T16	24299	311	0	0
T17	27244	311	0	0
T18	206293	1381	0	0
T19	0	3468	0	0
T20	207830	939	0	0
T21	185284	3198	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3572959	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3572959	0	0
T1	753	14	0	0
T2	117744	0	0	0
T3	2215	42	0	0
T4	4851	30	0	0
T16	24299	100	0	0
T17	27244	311	0	0
T18	206293	1469	0	0
T19	0	3561	0	0
T20	207830	79836	0	0
T21	185284	979	0	0
T22	470	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1529704	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1529704	0	0
T1	753	8	0	0
T2	117744	0	0	0
T3	2215	51	0	0
T4	4851	6	0	0
T16	24299	191	0	0
T17	27244	537	0	0
T18	206293	3123	0	0
T19	0	3375	0	0
T20	207830	0	0	0
T21	185284	2403	0	0
T22	470	7	0	0
T23	0	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3678760	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3678760	0	0
T1	753	8	0	0
T2	117744	0	0	0
T3	2215	51	0	0
T4	4851	14	0	0
T16	24299	89	0	0
T17	27244	537	0	0
T18	206293	3135	0	0
T19	0	3754	0	0
T20	207830	0	0	0
T21	185284	639	0	0
T22	470	7	0	0
T23	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1476542	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1476542	0	0
T1	753	6	0	0
T2	117744	0	0	0
T3	2215	48	0	0
T4	4851	51	0	0
T16	24299	257	0	0
T17	27244	314	0	0
T18	206293	3668	0	0
T19	0	5490	0	0
T20	207830	0	0	0
T21	185284	4105	0	0
T22	470	3	0	0
T23	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2869621	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2869621	0	0
T1	753	6	0	0
T2	117744	0	0	0
T3	2215	48	0	0
T4	4851	56	0	0
T16	24299	66	0	0
T17	27244	314	0	0
T18	206293	3735	0	0
T19	0	5721	0	0
T20	207830	0	0	0
T21	185284	1868	0	0
T22	470	3	0	0
T23	0	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1506465	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1506465	0	0
T1	753	9	0	0
T2	117744	976	0	0
T3	2215	66	0	0
T4	4851	72	0	0
T16	24299	279	0	0
T17	27244	272	0	0
T18	206293	1363	0	0
T19	0	3997	0	0
T20	207830	0	0	0
T21	185284	1764	0	0
T22	470	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2552648	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2552648	0	0
T1	753	9	0	0
T2	117744	81409	0	0
T3	2215	66	0	0
T4	4851	47	0	0
T16	24299	143	0	0
T17	27244	272	0	0
T18	206293	1441	0	0
T19	0	4080	0	0
T20	207830	0	0	0
T21	185284	971	0	0
T22	470	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1525183	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1525183	0	0
T1	753	12	0	0
T2	117744	0	0	0
T3	2215	41	0	0
T4	4851	47	0	0
T16	24299	362	0	0
T17	27244	269	0	0
T18	206293	5123	0	0
T19	0	1619	0	0
T20	207830	1090	0	0
T21	185284	3686	0	0
T22	470	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3052863	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3052863	0	0
T1	753	12	0	0
T2	117744	0	0	0
T3	2215	41	0	0
T4	4851	53	0	0
T16	24299	147	0	0
T17	27244	269	0	0
T18	206293	5110	0	0
T19	0	1864	0	0
T20	207830	90355	0	0
T21	185284	1798	0	0
T22	470	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1483015	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1483015	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	40	0	0
T4	4851	27	0	0
T16	24299	331	0	0
T17	27244	291	0	0
T18	206293	3118	0	0
T19	0	1776	0	0
T20	207830	0	0	0
T21	185284	2899	0	0
T22	470	6	0	0
T23	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3729286	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3729286	0	0
T1	753	11	0	0
T2	117744	0	0	0
T3	2215	40	0	0
T4	4851	19	0	0
T16	24299	150	0	0
T17	27244	291	0	0
T18	206293	3085	0	0
T19	0	1906	0	0
T20	207830	0	0	0
T21	185284	785	0	0
T22	470	6	0	0
T23	0	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1502901	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1502901	0	0
T1	753	12	0	0
T2	117744	0	0	0
T3	2215	35	0	0
T4	4851	73	0	0
T16	24299	280	0	0
T17	27244	871	0	0
T18	206293	1430	0	0
T19	0	3394	0	0
T20	207830	0	0	0
T21	185284	1465	0	0
T22	470	8	0	0
T23	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3305872	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3305872	0	0
T1	753	12	0	0
T2	117744	0	0	0
T3	2215	35	0	0
T4	4851	73	0	0
T16	24299	140	0	0
T17	27244	871	0	0
T18	206293	1449	0	0
T19	0	3497	0	0
T20	207830	0	0	0
T21	185284	27	0	0
T22	470	8	0	0
T23	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1498729	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1498729	0	0
T1	753	20	0	0
T2	117744	1199	0	0
T3	2215	46	0	0
T4	4851	74	0	0
T16	24299	178	0	0
T17	27244	484	0	0
T18	206293	1275	0	0
T19	0	3487	0	0
T20	207830	0	0	0
T21	185284	2829	0	0
T22	470	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3016292	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3016292	0	0
T1	753	20	0	0
T2	117744	90622	0	0
T3	2215	46	0	0
T4	4851	63	0	0
T16	24299	61	0	0
T17	27244	484	0	0
T18	206293	1312	0	0
T19	0	3697	0	0
T20	207830	0	0	0
T21	185284	772	0	0
T22	470	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1517473	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1517473	0	0
T1	753	17	0	0
T2	117744	0	0	0
T3	2215	33	0	0
T4	4851	60	0	0
T16	24299	200	0	0
T17	27244	511	0	0
T18	206293	1281	0	0
T19	0	3520	0	0
T20	207830	0	0	0
T21	185284	1463	0	0
T22	470	4	0	0
T23	0	55	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	2899590	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	2899590	0	0
T1	753	17	0	0
T2	117744	0	0	0
T3	2215	33	0	0
T4	4851	71	0	0
T16	24299	102	0	0
T17	27244	511	0	0
T18	206293	1209	0	0
T19	0	3914	0	0
T20	207830	0	0	0
T21	185284	1810	0	0
T22	470	4	0	0
T23	0	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1529864	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1529864	0	0
T1	753	9	0	0
T2	117744	1198	0	0
T3	2215	51	0	0
T4	4851	9	0	0
T16	24299	425	0	0
T17	27244	515	0	0
T18	206293	1242	0	0
T19	0	3520	0	0
T20	207830	0	0	0
T21	185284	3415	0	0
T22	470	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3474895	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3474895	0	0
T1	753	9	0	0
T2	117744	103318	0	0
T3	2215	51	0	0
T4	4851	10	0	0
T16	24299	159	0	0
T17	27244	515	0	0
T18	206293	1140	0	0
T19	0	4013	0	0
T20	207830	0	0	0
T21	185284	450	0	0
T22	470	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	1544137	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	1544137	0	0
T1	753	9	0	0
T2	117744	0	0	0
T3	2215	38	0	0
T4	4851	37	0	0
T16	24299	322	0	0
T17	27244	879	0	0
T18	206293	2449	0	0
T19	0	1517	0	0
T20	207830	0	0	0
T21	185284	1557	0	0
T22	470	1	0	0
T23	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	303164959	3846624	0	0
DepthKnown_A	303164959	303045464	0	0
RvalidKnown_A	303164959	303045464	0	0
WreadyKnown_A	303164959	303045464	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	3846624	0	0
T1	753	9	0	0
T2	117744	0	0	0
T3	2215	38	0	0
T4	4851	32	0	0
T16	24299	132	0	0
T17	27244	879	0	0
T18	206293	2592	0	0
T19	0	1542	0	0
T20	207830	0	0	0
T21	185284	385	0	0
T22	470	1	0	0
T23	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	303164959	303045464	0	0
T1	753	727	0	0
T2	117744	117741	0	0
T3	2215	2208	0	0
T4	4851	4784	0	0
T16	24299	24282	0	0
T17	27244	27124	0	0
T18	206293	206241	0	0
T20	207830	207825	0	0
T21	185284	185211	0	0
T22	470	455	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0