Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1663192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261515

1

T1

119

T2

1806

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	651114	1			T1	302		T2	4320		T3	50
values[0x0]	621724	1			T1	287		T2	4441		T3	11
values[0x1]	651869	1			T1	294		T2	4402		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1289708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634999

1

T1

311

T2

4356

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6600	1			T1	3		T2	30		T13	14
valid_sources[0x01]	7336	1			T1	1		T2	50		T19	15
valid_sources[0x02]	7468	1			T1	2		T2	25		T19	2
valid_sources[0x03]	7146	1			T1	7		T2	28		T13	13
valid_sources[0x04]	7075	1			T1	4		T2	26		T3	2
valid_sources[0x05]	7302	1			T1	6		T2	44		T3	1
valid_sources[0x06]	8576	1			T2	26		T19	1		T13	9
valid_sources[0x07]	7559	1			T1	6		T2	43		T13	4
valid_sources[0x08]	6840	1			T1	1		T2	19		T16	27
valid_sources[0x09]	7257	1			T1	1		T2	51		T13	10
valid_sources[0x0a]	6659	1			T1	6		T2	47		T13	16
valid_sources[0x0b]	7740	1			T1	4		T2	30		T3	2
valid_sources[0x0c]	7118	1			T1	4		T2	52		T3	1
valid_sources[0x0d]	7763	1			T1	3		T2	59		T16	14
valid_sources[0x0e]	8053	1			T1	2		T2	38		T13	11
valid_sources[0x0f]	7419	1			T1	7		T2	88		T19	5
valid_sources[0x10]	7330	1			T1	3		T2	67		T19	18
valid_sources[0x11]	7281	1			T1	4		T2	63		T19	9
valid_sources[0x12]	6844	1			T1	2		T2	20		T16	6
valid_sources[0x13]	8352	1			T1	2		T2	66		T13	13
valid_sources[0x14]	7736	1			T1	1		T2	95		T19	6
valid_sources[0x15]	7079	1			T1	4		T2	39		T19	4
valid_sources[0x16]	7417	1			T1	3		T2	87		T19	20
valid_sources[0x17]	7059	1			T1	1		T2	36		T13	3
valid_sources[0x18]	9314	1			T1	6		T2	30		T19	28
valid_sources[0x19]	8063	1			T1	5		T2	61		T19	2
valid_sources[0x1a]	7013	1			T1	6		T2	84		T16	20
valid_sources[0x1b]	8507	1			T1	5		T2	85		T3	1
valid_sources[0x1c]	7640	1			T1	2		T2	31		T13	10
valid_sources[0x1d]	7186	1			T1	3		T2	59		T3	1
valid_sources[0x1e]	7116	1			T1	1		T2	51		T19	1
valid_sources[0x1f]	7811	1			T1	5		T2	60		T3	1
valid_sources[0x20]	7249	1			T1	6		T2	37		T16	13
valid_sources[0x21]	7916	1			T1	6		T2	39		T3	1
valid_sources[0x22]	7279	1			T1	5		T2	48		T3	1
valid_sources[0x23]	7109	1			T1	2		T2	30		T13	7
valid_sources[0x24]	7602	1			T2	16		T3	1		T19	35
valid_sources[0x25]	7276	1			T1	5		T2	83		T13	7
valid_sources[0x26]	7079	1			T1	2		T2	84		T3	1
valid_sources[0x27]	7562	1			T1	9		T2	60		T19	26
valid_sources[0x28]	7757	1			T1	2		T2	60		T3	1
valid_sources[0x29]	6657	1			T1	5		T2	64		T3	1
valid_sources[0x2a]	7110	1			T1	5		T2	22		T19	1
valid_sources[0x2b]	7337	1			T1	8		T2	54		T13	11
valid_sources[0x2c]	7219	1			T1	2		T2	26		T19	9
valid_sources[0x2d]	8120	1			T1	1		T2	48		T19	3
valid_sources[0x2e]	8434	1			T1	1		T2	74		T13	22
valid_sources[0x2f]	6873	1			T2	55		T16	13		T13	2
valid_sources[0x30]	7087	1			T1	3		T2	37		T3	2
valid_sources[0x31]	7157	1			T1	2		T2	31		T13	8
valid_sources[0x32]	7761	1			T2	67		T3	1		T13	14
valid_sources[0x33]	6885	1			T1	4		T2	42		T3	1
valid_sources[0x34]	7473	1			T1	6		T2	32		T13	8
valid_sources[0x35]	7166	1			T1	1		T2	31		T3	4
valid_sources[0x36]	7335	1			T1	3		T2	32		T19	1
valid_sources[0x37]	7169	1			T1	3		T2	66		T3	1
valid_sources[0x38]	8342	1			T1	6		T2	49		T19	3
valid_sources[0x39]	7485	1			T1	7		T2	47		T3	3
valid_sources[0x3a]	7545	1			T1	2		T2	83		T19	14
valid_sources[0x3b]	7419	1			T1	4		T2	45		T19	1
valid_sources[0x3c]	7750	1			T1	1		T2	54		T19	4
valid_sources[0x3d]	7758	1			T1	1		T2	83		T19	4
valid_sources[0x3e]	7969	1			T1	3		T2	44		T19	15
valid_sources[0x3f]	7190	1			T1	1		T2	74		T19	1
valid_sources[0x40]	7124	1			T1	2		T2	46		T13	12
valid_sources[0x41]	7433	1			T1	6		T2	49		T13	12
valid_sources[0x42]	6934	1			T1	5		T2	93		T13	7
valid_sources[0x43]	7287	1			T1	2		T2	38		T19	10
valid_sources[0x44]	7744	1			T1	3		T2	63		T3	1
valid_sources[0x45]	7568	1			T1	3		T2	74		T3	1
valid_sources[0x46]	8619	1			T1	7		T2	36		T13	10
valid_sources[0x47]	6469	1			T1	4		T2	43		T3	1
valid_sources[0x48]	7989	1			T1	2		T2	44		T3	1
valid_sources[0x49]	8461	1			T1	1		T2	31		T19	8
valid_sources[0x4a]	7773	1			T2	56		T19	15		T13	7
valid_sources[0x4b]	7778	1			T1	1		T2	73		T13	6
valid_sources[0x4c]	7223	1			T1	7		T2	23		T16	21
valid_sources[0x4d]	7854	1			T1	2		T2	74		T13	5
valid_sources[0x4e]	7483	1			T1	3		T2	59		T3	1
valid_sources[0x4f]	7396	1			T1	2		T2	52		T13	10
valid_sources[0x50]	7058	1			T1	2		T2	30		T13	16
valid_sources[0x51]	7537	1			T1	4		T2	41		T16	18
valid_sources[0x52]	8013	1			T1	6		T2	29		T19	52
valid_sources[0x53]	8057	1			T1	1		T2	84		T3	1
valid_sources[0x54]	7477	1			T1	2		T2	58		T3	1
valid_sources[0x55]	6754	1			T1	6		T2	96		T19	25
valid_sources[0x56]	7326	1			T1	4		T2	58		T16	11
valid_sources[0x57]	7740	1			T1	2		T2	39		T13	8
valid_sources[0x58]	7675	1			T1	2		T2	92		T3	2
valid_sources[0x59]	6931	1			T1	3		T2	25		T3	1
valid_sources[0x5a]	7712	1			T1	2		T2	60		T19	29
valid_sources[0x5b]	7443	1			T1	5		T2	27		T3	1
valid_sources[0x5c]	8124	1			T1	4		T2	63		T19	13
valid_sources[0x5d]	7514	1			T1	4		T2	24		T3	1
valid_sources[0x5e]	6955	1			T1	4		T2	74		T19	1
valid_sources[0x5f]	8764	1			T1	6		T2	37		T3	1
valid_sources[0x60]	7050	1			T1	3		T2	67		T13	7
valid_sources[0x61]	7080	1			T1	5		T2	49		T3	1
valid_sources[0x62]	7888	1			T1	6		T2	68		T19	5
valid_sources[0x63]	7400	1			T1	1		T2	85		T3	3
valid_sources[0x64]	7677	1			T1	5		T2	50		T16	9
valid_sources[0x65]	9942	1			T1	5		T2	37		T13	12
valid_sources[0x66]	6993	1			T2	66		T16	30		T13	11
valid_sources[0x67]	7739	1			T1	4		T2	94		T3	1
valid_sources[0x68]	7367	1			T1	2		T2	68		T3	1
valid_sources[0x69]	7975	1			T1	6		T2	50		T19	5
valid_sources[0x6a]	7763	1			T1	1		T2	46		T3	1
valid_sources[0x6b]	6948	1			T1	2		T2	30		T19	16
valid_sources[0x6c]	7445	1			T1	2		T2	52		T13	10
valid_sources[0x6d]	7287	1			T1	5		T2	33		T13	12
valid_sources[0x6e]	7139	1			T1	4		T2	31		T19	17
valid_sources[0x6f]	7079	1			T1	1		T2	68		T16	16
valid_sources[0x70]	7215	1			T1	9		T2	89		T3	1
valid_sources[0x71]	8269	1			T1	3		T2	45		T3	1
valid_sources[0x72]	6763	1			T1	3		T2	60		T19	5
valid_sources[0x73]	7173	1			T1	6		T2	80		T13	6
valid_sources[0x74]	8018	1			T1	6		T2	57		T19	3
valid_sources[0x75]	6854	1			T1	3		T2	34		T13	12
valid_sources[0x76]	6671	1			T1	5		T2	94		T3	1
valid_sources[0x77]	7436	1			T1	4		T2	20		T3	1
valid_sources[0x78]	7570	1			T1	1		T2	45		T16	7
valid_sources[0x79]	7390	1			T1	2		T2	42		T13	5
valid_sources[0x7a]	7445	1			T1	3		T2	61		T13	11
valid_sources[0x7b]	7062	1			T1	10		T2	67		T13	7
valid_sources[0x7c]	7840	1			T1	2		T2	45		T3	2
valid_sources[0x7d]	6850	1			T1	1		T2	26		T19	11
valid_sources[0x7e]	8654	1			T1	4		T2	34		T19	9
valid_sources[0x7f]	8479	1			T1	1		T2	55		T3	1
valid_sources[0x80]	6927	1			T1	5		T2	46		T19	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27458

1

T1

17

T2

175

T3

1

values[0x0]

all_enables

biggest_size

206325

1

T1

90

T2

1449

T3

3

values[0x1]

all_enables

biggest_size

27732

1

T1

12

T2

182

T3

3