Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328610035	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328610035	0	0
T1	6137320	1376819	0	0
T2	16290568	303609	0	0
T3	4298560	99453	0	0
T13	6891248	146582	0	0
T14	19923344	444630	0	0
T16	2618280	36872	0	0
T17	6947976	112838	0	0
T18	160888	10920	0	0
T19	10451056	2272783	0	0
T20	2862496	60167	0	0
T21	0	660241	0	0
T22	0	1171	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6137320	6137152	0	0
T2	16290568	16288440	0	0
T3	4298560	4296712	0	0
T13	6891248	6890968	0	0
T14	19923344	19914104	0	0
T16	2618280	2616264	0	0
T17	6947976	6945680	0	0
T18	160888	160216	0	0
T19	10451056	10450832	0	0
T20	2862496	2862048	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6137320	6137152	0	0
T2	16290568	16288440	0	0
T3	4298560	4296712	0	0
T13	6891248	6890968	0	0
T14	19923344	19914104	0	0
T16	2618280	2616264	0	0
T17	6947976	6945680	0	0
T18	160888	160216	0	0
T19	10451056	10450832	0	0
T20	2862496	2862048	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6137320	6137152	0	0
T2	16290568	16288440	0	0
T3	4298560	4296712	0	0
T13	6891248	6890968	0	0
T14	19923344	19914104	0	0
T16	2618280	2616264	0	0
T17	6947976	6945680	0	0
T18	160888	160216	0	0
T19	10451056	10450832	0	0
T20	2862496	2862048	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	123376520	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	123376520	0	0
T1	109595	592907	0	0
T2	290903	136243	0	0
T3	76760	40839	0	0
T13	123058	120425	0	0
T14	355774	185381	0	0
T16	46755	9203	0	0
T17	124071	54185	0	0
T18	2873	2730	0	0
T19	186626	895061	0	0
T20	51116	27795	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	83773889	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	83773889	0	0
T1	109595	242608	0	0
T2	290903	40614	0	0
T3	76760	19449	0	0
T13	123058	7654	0	0
T14	355774	103082	0	0
T16	46755	9236	0	0
T17	124071	10942	0	0
T18	2873	2730	0	0
T19	186626	454912	0	0
T20	51116	7185	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1456395	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1456395	0	0
T1	109595	14259	0	0
T2	290903	3096	0	0
T3	76760	775	0	0
T13	123058	366	0	0
T14	355774	4262	0	0
T16	46755	311	0	0
T17	124071	2277	0	0
T18	2873	228	0	0
T19	186626	21592	0	0
T20	51116	689	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2912756	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2912756	0	0
T1	109595	13357	0	0
T2	290903	1524	0	0
T3	76760	643	0	0
T13	123058	84	0	0
T14	355774	3790	0	0
T16	46755	379	0	0
T17	124071	253	0	0
T18	2873	228	0	0
T19	186626	20419	0	0
T20	51116	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1413724	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1413724	0	0
T1	109595	9791	0	0
T2	290903	3079	0	0
T3	76760	782	0	0
T13	123058	448	0	0
T14	355774	2859	0	0
T16	46755	306	0	0
T17	124071	897	0	0
T18	2873	0	0	0
T19	186626	15860	0	0
T20	51116	734	0	0
T22	0	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2928463	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2928463	0	0
T1	109595	5750	0	0
T2	290903	1427	0	0
T3	76760	722	0	0
T13	123058	99	0	0
T14	355774	2489	0	0
T16	46755	263	0	0
T17	124071	2	0	0
T18	2873	0	0	0
T19	186626	15419	0	0
T20	51116	257	0	0
T22	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1432060	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1432060	0	0
T1	109595	9778	0	0
T2	290903	3065	0	0
T3	76760	825	0	0
T13	123058	428	0	0
T14	355774	3914	0	0
T16	46755	483	0	0
T17	124071	2121	0	0
T18	2873	248	0	0
T19	186626	19357	0	0
T20	51116	536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2880701	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2880701	0	0
T1	109595	6492	0	0
T2	290903	1248	0	0
T3	76760	830	0	0
T13	123058	102	0	0
T14	355774	3402	0	0
T16	46755	391	0	0
T17	124071	540	0	0
T18	2873	248	0	0
T19	186626	17388	0	0
T20	51116	282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1486966	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1486966	0	0
T1	109595	7428	0	0
T2	290903	2904	0	0
T3	76760	825	0	0
T13	123058	376	0	0
T14	355774	4355	0	0
T16	46755	278	0	0
T17	124071	2153	0	0
T18	2873	0	0	0
T19	186626	17795	0	0
T20	51116	633	0	0
T22	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3235033	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3235033	0	0
T1	109595	7697	0	0
T2	290903	1076	0	0
T3	76760	781	0	0
T13	123058	319	0	0
T14	355774	3446	0	0
T16	46755	325	0	0
T17	124071	207	0	0
T18	2873	0	0	0
T19	186626	14918	0	0
T20	51116	329	0	0
T22	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1420905	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1420905	0	0
T1	109595	10511	0	0
T2	290903	2791	0	0
T3	76760	802	0	0
T13	123058	430	0	0
T14	355774	2320	0	0
T16	46755	263	0	0
T17	124071	916	0	0
T18	2873	212	0	0
T19	186626	22869	0	0
T20	51116	591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2553403	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2553403	0	0
T1	109595	11756	0	0
T2	290903	1189	0	0
T3	76760	701	0	0
T13	123058	1036	0	0
T14	355774	1988	0	0
T16	46755	214	0	0
T17	124071	297	0	0
T18	2873	212	0	0
T19	186626	20304	0	0
T20	51116	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1407581	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1407581	0	0
T1	109595	10443	0	0
T2	290903	2721	0	0
T3	76760	641	0	0
T13	123058	345	0	0
T14	355774	4330	0	0
T16	46755	414	0	0
T17	124071	586	0	0
T18	2873	0	0	0
T19	186626	18143	0	0
T20	51116	787	0	0
T22	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2962617	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2962617	0	0
T1	109595	9816	0	0
T2	290903	1334	0	0
T3	76760	742	0	0
T13	123058	85	0	0
T14	355774	3769	0	0
T16	46755	397	0	0
T17	124071	435	0	0
T18	2873	0	0	0
T19	186626	21199	0	0
T20	51116	301	0	0
T22	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1368163	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1368163	0	0
T1	109595	8996	0	0
T2	290903	3131	0	0
T3	76760	784	0	0
T13	123058	429	0	0
T14	355774	2682	0	0
T16	46755	378	0	0
T17	124071	1201	0	0
T18	2873	0	0	0
T19	186626	20604	0	0
T20	51116	645	0	0
T22	0	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2360687	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2360687	0	0
T1	109595	8398	0	0
T2	290903	1117	0	0
T3	76760	737	0	0
T13	123058	359	0	0
T14	355774	2325	0	0
T16	46755	584	0	0
T17	124071	146	0	0
T18	2873	0	0	0
T19	186626	14034	0	0
T20	51116	190	0	0
T22	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1459056	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1459056	0	0
T1	109595	10843	0	0
T2	290903	2991	0	0
T3	76760	744	0	0
T13	123058	402	0	0
T14	355774	2536	0	0
T16	46755	359	0	0
T17	124071	922	0	0
T18	2873	0	0	0
T19	186626	14983	0	0
T20	51116	662	0	0
T21	0	1328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3432227	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3432227	0	0
T1	109595	9567	0	0
T2	290903	1204	0	0
T3	76760	601	0	0
T13	123058	98	0	0
T14	355774	2158	0	0
T16	46755	394	0	0
T17	124071	690	0	0
T18	2873	0	0	0
T19	186626	15007	0	0
T20	51116	269	0	0
T21	0	108772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1422753	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1422753	0	0
T1	109595	10355	0	0
T2	290903	2809	0	0
T3	76760	619	0	0
T13	123058	363	0	0
T14	355774	2671	0	0
T16	46755	294	0	0
T17	124071	1924	0	0
T18	2873	0	0	0
T19	186626	14862	0	0
T20	51116	661	0	0
T22	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3144920	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3144920	0	0
T1	109595	9411	0	0
T2	290903	1322	0	0
T3	76760	564	0	0
T13	123058	90	0	0
T14	355774	2488	0	0
T16	46755	253	0	0
T17	124071	1067	0	0
T18	2873	0	0	0
T19	186626	14365	0	0
T20	51116	294	0	0
T22	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1408468	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1408468	0	0
T1	109595	11878	0	0
T2	290903	4726	0	0
T3	76760	645	0	0
T13	123058	424	0	0
T14	355774	2825	0	0
T16	46755	298	0	0
T17	124071	2247	0	0
T18	2873	261	0	0
T19	186626	22193	0	0
T20	51116	620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3597052	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3597052	0	0
T1	109595	9814	0	0
T2	290903	2098	0	0
T3	76760	633	0	0
T13	123058	160	0	0
T14	355774	2442	0	0
T16	46755	303	0	0
T17	124071	1078	0	0
T18	2873	261	0	0
T19	186626	17163	0	0
T20	51116	248	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1396309	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1396309	0	0
T1	109595	6989	0	0
T2	290903	2838	0	0
T3	76760	710	0	0
T13	123058	394	0	0
T14	355774	2371	0	0
T16	46755	224	0	0
T17	124071	1068	0	0
T18	2873	228	0	0
T19	186626	13756	0	0
T20	51116	651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2439403	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2439403	0	0
T1	109595	6405	0	0
T2	290903	1258	0	0
T3	76760	723	0	0
T13	123058	676	0	0
T14	355774	2144	0	0
T16	46755	318	0	0
T17	124071	589	0	0
T18	2873	228	0	0
T19	186626	16613	0	0
T20	51116	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1412885	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1412885	0	0
T1	109595	9858	0	0
T2	290903	2782	0	0
T3	76760	721	0	0
T13	123058	416	0	0
T14	355774	4557	0	0
T16	46755	324	0	0
T17	124071	304	0	0
T18	2873	0	0	0
T19	186626	15183	0	0
T20	51116	763	0	0
T22	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3100327	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3100327	0	0
T1	109595	10715	0	0
T2	290903	1217	0	0
T3	76760	823	0	0
T13	123058	97	0	0
T14	355774	4296	0	0
T16	46755	260	0	0
T17	124071	492	0	0
T18	2873	0	0	0
T19	186626	15558	0	0
T20	51116	267	0	0
T22	0	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1461191	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1461191	0	0
T1	109595	10597	0	0
T2	290903	4622	0	0
T3	76760	709	0	0
T13	123058	311	0	0
T14	355774	2662	0	0
T16	46755	481	0	0
T17	124071	1667	0	0
T18	2873	449	0	0
T19	186626	15891	0	0
T20	51116	653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2951888	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2951888	0	0
T1	109595	8137	0	0
T2	290903	2115	0	0
T3	76760	669	0	0
T13	123058	76	0	0
T14	355774	2369	0	0
T16	46755	445	0	0
T17	124071	184	0	0
T18	2873	449	0	0
T19	186626	13955	0	0
T20	51116	261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1475059	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1475059	0	0
T1	109595	14667	0	0
T2	290903	2721	0	0
T3	76760	753	0	0
T13	123058	447	0	0
T14	355774	4853	0	0
T16	46755	432	0	0
T17	124071	995	0	0
T18	2873	298	0	0
T19	186626	18154	0	0
T20	51116	654	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3095388	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3095388	0	0
T1	109595	7970	0	0
T2	290903	1265	0	0
T3	76760	722	0	0
T13	123058	102	0	0
T14	355774	4111	0	0
T16	46755	406	0	0
T17	124071	322	0	0
T18	2873	298	0	0
T19	186626	16100	0	0
T20	51116	267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1367275	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1367275	0	0
T1	109595	11068	0	0
T2	290903	4354	0	0
T3	76760	593	0	0
T13	123058	425	0	0
T14	355774	2551	0	0
T16	46755	350	0	0
T17	124071	1148	0	0
T18	2873	0	0	0
T19	186626	13590	0	0
T20	51116	666	0	0
T22	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3139192	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3139192	0	0
T1	109595	7484	0	0
T2	290903	2269	0	0
T3	76760	647	0	0
T13	123058	94	0	0
T14	355774	2366	0	0
T16	46755	293	0	0
T17	124071	292	0	0
T18	2873	0	0	0
T19	186626	15798	0	0
T20	51116	229	0	0
T22	0	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1402303	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1402303	0	0
T1	109595	9926	0	0
T2	290903	2799	0	0
T3	76760	642	0	0
T13	123058	420	0	0
T14	355774	2946	0	0
T16	46755	327	0	0
T17	124071	1431	0	0
T18	2873	0	0	0
T19	186626	18879	0	0
T20	51116	723	0	0
T22	0	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2977359	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2977359	0	0
T1	109595	5928	0	0
T2	290903	1332	0	0
T3	76760	807	0	0
T13	123058	89	0	0
T14	355774	2647	0	0
T16	46755	352	0	0
T17	124071	326	0	0
T18	2873	0	0	0
T19	186626	19345	0	0
T20	51116	304	0	0
T22	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1416654	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1416654	0	0
T1	109595	8560	0	0
T2	290903	3142	0	0
T3	76760	774	0	0
T13	123058	346	0	0
T14	355774	2451	0	0
T16	46755	377	0	0
T17	124071	1143	0	0
T18	2873	0	0	0
T19	186626	12763	0	0
T20	51116	596	0	0
T21	0	1216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3040149	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3040149	0	0
T1	109595	5037	0	0
T2	290903	1409	0	0
T3	76760	770	0	0
T13	123058	80	0	0
T14	355774	2082	0	0
T16	46755	428	0	0
T17	124071	413	0	0
T18	2873	0	0	0
T19	186626	10957	0	0
T20	51116	292	0	0
T21	0	103145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1379423	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1379423	0	0
T1	109595	9257	0	0
T2	290903	3020	0	0
T3	76760	641	0	0
T13	123058	389	0	0
T14	355774	2660	0	0
T16	46755	262	0	0
T17	124071	1034	0	0
T18	2873	0	0	0
T19	186626	19194	0	0
T20	51116	679	0	0
T21	0	1141	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2805435	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2805435	0	0
T1	109595	9809	0	0
T2	290903	1374	0	0
T3	76760	704	0	0
T13	123058	98	0	0
T14	355774	2212	0	0
T16	46755	269	0	0
T17	124071	844	0	0
T18	2873	0	0	0
T19	186626	19475	0	0
T20	51116	270	0	0
T21	0	87473	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1373706	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1373706	0	0
T1	109595	16079	0	0
T2	290903	3125	0	0
T3	76760	588	0	0
T13	123058	426	0	0
T14	355774	2542	0	0
T16	46755	351	0	0
T17	124071	430	0	0
T18	2873	248	0	0
T19	186626	17707	0	0
T20	51116	651	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2833916	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2833916	0	0
T1	109595	11645	0	0
T2	290903	1408	0	0
T3	76760	609	0	0
T13	123058	147	0	0
T14	355774	2129	0	0
T16	46755	329	0	0
T17	124071	25	0	0
T18	2873	248	0	0
T19	186626	15124	0	0
T20	51116	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1503518	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1503518	0	0
T1	109595	10849	0	0
T2	290903	2717	0	0
T3	76760	720	0	0
T13	123058	444	0	0
T14	355774	2543	0	0
T16	46755	394	0	0
T17	124071	3241	0	0
T18	2873	0	0	0
T19	186626	16247	0	0
T20	51116	605	0	0
T22	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3504462	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3504462	0	0
T1	109595	10289	0	0
T2	290903	1190	0	0
T3	76760	705	0	0
T13	123058	104	0	0
T14	355774	2295	0	0
T16	46755	383	0	0
T17	124071	230	0	0
T18	2873	0	0	0
T19	186626	18662	0	0
T20	51116	225	0	0
T22	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1392137	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1392137	0	0
T1	109595	9273	0	0
T2	290903	2668	0	0
T3	76760	612	0	0
T13	123058	394	0	0
T14	355774	2196	0	0
T16	46755	405	0	0
T17	124071	703	0	0
T18	2873	0	0	0
T19	186626	13499	0	0
T20	51116	644	0	0
T21	0	1261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2936411	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2936411	0	0
T1	109595	7418	0	0
T2	290903	1214	0	0
T3	76760	584	0	0
T13	123058	91	0	0
T14	355774	1966	0	0
T16	46755	365	0	0
T17	124071	155	0	0
T18	2873	0	0	0
T19	186626	16801	0	0
T20	51116	263	0	0
T21	0	109852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1481848	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1481848	0	0
T1	109595	15255	0	0
T2	290903	2951	0	0
T3	76760	858	0	0
T13	123058	434	0	0
T14	355774	2308	0	0
T16	46755	305	0	0
T17	124071	1628	0	0
T18	2873	0	0	0
T19	186626	20003	0	0
T20	51116	719	0	0
T22	0	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2931436	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2931436	0	0
T1	109595	10792	0	0
T2	290903	1246	0	0
T3	76760	762	0	0
T13	123058	97	0	0
T14	355774	2251	0	0
T16	46755	432	0	0
T17	124071	437	0	0
T18	2873	0	0	0
T19	186626	19420	0	0
T20	51116	243	0	0
T22	0	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1411539	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1411539	0	0
T1	109595	11591	0	0
T2	290903	5297	0	0
T3	76760	764	0	0
T13	123058	416	0	0
T14	355774	2499	0	0
T16	46755	426	0	0
T17	124071	1469	0	0
T18	2873	0	0	0
T19	186626	14308	0	0
T20	51116	578	0	0
T22	0	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	2897045	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	2897045	0	0
T1	109595	9008	0	0
T2	290903	2123	0	0
T3	76760	765	0	0
T13	123058	189	0	0
T14	355774	2279	0	0
T16	46755	389	0	0
T17	124071	316	0	0
T18	2873	0	0	0
T19	186626	17621	0	0
T20	51116	284	0	0
T22	0	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1426643	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1426643	0	0
T1	109595	13773	0	0
T2	290903	3013	0	0
T3	76760	679	0	0
T13	123058	370	0	0
T14	355774	4181	0	0
T16	46755	325	0	0
T17	124071	1396	0	0
T18	2873	0	0	0
T19	186626	14492	0	0
T20	51116	796	0	0
T21	0	940	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3480623	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3480623	0	0
T1	109595	12952	0	0
T2	290903	1369	0	0
T3	76760	671	0	0
T13	123058	784	0	0
T14	355774	3589	0	0
T16	46755	366	0	0
T17	124071	104	0	0
T18	2873	0	0	0
T19	186626	12262	0	0
T20	51116	248	0	0
T21	0	71364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1451872	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1451872	0	0
T1	109595	13088	0	0
T2	290903	2885	0	0
T3	76760	849	0	0
T13	123058	329	0	0
T14	355774	2604	0	0
T16	46755	284	0	0
T17	124071	1529	0	0
T18	2873	0	0	0
T19	186626	18892	0	0
T20	51116	745	0	0
T22	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3415918	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3415918	0	0
T1	109595	7964	0	0
T2	290903	1380	0	0
T3	76760	814	0	0
T13	123058	150	0	0
T14	355774	2025	0	0
T16	46755	222	0	0
T17	124071	969	0	0
T18	2873	0	0	0
T19	186626	20046	0	0
T20	51116	319	0	0
T22	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1460857	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1460857	0	0
T1	109595	10545	0	0
T2	290903	4647	0	0
T3	76760	798	0	0
T13	123058	451	0	0
T14	355774	4303	0	0
T16	46755	361	0	0
T17	124071	1548	0	0
T18	2873	0	0	0
T19	186626	17350	0	0
T20	51116	634	0	0
T21	0	2237	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3872024	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3872024	0	0
T1	109595	9601	0	0
T2	290903	1979	0	0
T3	76760	871	0	0
T13	123058	1126	0	0
T14	355774	3602	0	0
T16	46755	286	0	0
T17	124071	230	0	0
T18	2873	0	0	0
T19	186626	17403	0	0
T20	51116	329	0	0
T21	0	171512	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	1490889	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	1490889	0	0
T1	109595	13039	0	0
T2	290903	2929	0	0
T3	76760	863	0	0
T13	123058	426	0	0
T14	355774	2448	0	0
T16	46755	188	0	0
T17	124071	792	0	0
T18	2873	558	0	0
T19	186626	19732	0	0
T20	51116	687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	297865013	3450612	0	0
DepthKnown_A	297865013	297747244	0	0
RvalidKnown_A	297865013	297747244	0	0
WreadyKnown_A	297865013	297747244	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	3450612	0	0
T1	109595	9396	0	0
T2	290903	1242	0	0
T3	76760	849	0	0
T13	123058	1222	0	0
T14	355774	2078	0	0
T16	46755	187	0	0
T17	124071	298	0	0
T18	2873	558	0	0
T19	186626	19556	0	0
T20	51116	222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	297865013	297747244	0	0
T1	109595	109592	0	0
T2	290903	290865	0	0
T3	76760	76727	0	0
T13	123058	123053	0	0
T14	355774	355609	0	0
T16	46755	46719	0	0
T17	124071	124030	0	0
T18	2873	2861	0	0
T19	186626	186622	0	0
T20	51116	51108	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0