Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1656093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260278

1

T1

5

T2

71

T3

230

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647436	1			T1	15		T2	145		T3	588
values[0x0]	621322	1			T1	4		T2	140		T3	561
values[0x1]	647613	1			T1	17		T2	140		T3	551

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1283592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632779

1

T1

16

T2

164

T3

543

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7469	1			T2	3		T17	15		T21	7
valid_sources[0x01]	7634	1			T2	3		T17	19		T21	9
valid_sources[0x02]	7245	1			T17	63		T21	5		T24	1
valid_sources[0x03]	6734	1			T4	5		T17	12		T21	7
valid_sources[0x04]	7498	1			T20	3		T17	37		T21	11
valid_sources[0x05]	7707	1			T2	2		T4	6		T17	24
valid_sources[0x06]	7170	1			T2	1		T17	35		T21	12
valid_sources[0x07]	7249	1			T17	5		T21	4		T19	1
valid_sources[0x08]	8224	1			T2	1		T3	79		T4	8
valid_sources[0x09]	8441	1			T2	3		T17	72		T21	6
valid_sources[0x0a]	8567	1			T2	2		T4	10		T17	68
valid_sources[0x0b]	7335	1			T17	40		T21	2		T24	2
valid_sources[0x0c]	6613	1			T2	1		T3	61		T17	18
valid_sources[0x0d]	7514	1			T17	25		T18	3		T21	7
valid_sources[0x0e]	7265	1			T2	2		T17	11		T21	10
valid_sources[0x0f]	7092	1			T2	9		T17	13		T21	3
valid_sources[0x10]	7404	1			T3	86		T17	102		T21	15
valid_sources[0x11]	6997	1			T2	9		T4	11		T17	27
valid_sources[0x12]	7151	1			T2	1		T17	17		T21	9
valid_sources[0x13]	8639	1			T2	1		T20	2		T17	31
valid_sources[0x14]	6934	1			T2	3		T17	7		T21	9
valid_sources[0x15]	7663	1			T17	45		T21	8		T24	1
valid_sources[0x16]	7869	1			T2	1		T4	2		T17	15
valid_sources[0x17]	6630	1			T2	4		T17	50		T21	8
valid_sources[0x18]	7058	1			T17	71		T21	7		T24	2
valid_sources[0x19]	7329	1			T3	89		T4	16		T17	28
valid_sources[0x1a]	6599	1			T2	2		T4	12		T17	15
valid_sources[0x1b]	7998	1			T4	12		T20	1		T17	40
valid_sources[0x1c]	7387	1			T17	42		T18	10		T21	9
valid_sources[0x1d]	8247	1			T2	1		T4	16		T17	25
valid_sources[0x1e]	6929	1			T2	2		T17	60		T21	14
valid_sources[0x1f]	8143	1			T2	6		T3	196		T17	55
valid_sources[0x20]	7741	1			T2	1		T17	430		T21	4
valid_sources[0x21]	7632	1			T17	28		T21	3		T19	5
valid_sources[0x22]	6812	1			T17	52		T21	3		T24	5
valid_sources[0x23]	7654	1			T17	31		T21	3		T24	6
valid_sources[0x24]	7306	1			T17	65		T21	9		T19	3
valid_sources[0x25]	7144	1			T2	4		T17	31		T21	5
valid_sources[0x26]	7160	1			T2	1		T17	35		T21	7
valid_sources[0x27]	8034	1			T2	1		T20	2		T17	46
valid_sources[0x28]	7391	1			T2	1		T17	24		T21	9
valid_sources[0x29]	7917	1			T17	124		T21	5		T25	10
valid_sources[0x2a]	7506	1			T2	2		T3	63		T4	15
valid_sources[0x2b]	9667	1			T20	1		T17	591		T21	4
valid_sources[0x2c]	8057	1			T4	1		T17	47		T21	8
valid_sources[0x2d]	6443	1			T2	4		T4	4		T17	31
valid_sources[0x2e]	7860	1			T2	3		T4	20		T17	16
valid_sources[0x2f]	7837	1			T2	1		T17	31		T21	9
valid_sources[0x30]	6628	1			T2	2		T17	4		T21	7
valid_sources[0x31]	7714	1			T1	14		T2	2		T17	47
valid_sources[0x32]	7817	1			T2	3		T4	13		T17	64
valid_sources[0x33]	7312	1			T17	59		T21	5		T19	1
valid_sources[0x34]	7946	1			T2	2		T20	6		T17	42
valid_sources[0x35]	7362	1			T17	150		T21	8		T24	3
valid_sources[0x36]	7657	1			T2	4		T17	21		T21	9
valid_sources[0x37]	7083	1			T2	4		T17	43		T18	18
valid_sources[0x38]	7960	1			T17	41		T21	16		T19	1
valid_sources[0x39]	6844	1			T2	3		T17	37		T21	6
valid_sources[0x3a]	6922	1			T4	48		T17	53		T21	3
valid_sources[0x3b]	7343	1			T2	3		T17	44		T21	4
valid_sources[0x3c]	7002	1			T17	32		T21	4		T19	3
valid_sources[0x3d]	7621	1			T2	2		T4	42		T17	64
valid_sources[0x3e]	8249	1			T1	1		T17	50		T21	2
valid_sources[0x3f]	6856	1			T4	6		T20	3		T17	23
valid_sources[0x40]	7480	1			T17	107		T21	7		T19	1
valid_sources[0x41]	7351	1			T4	5		T17	68		T21	6
valid_sources[0x42]	7559	1			T17	36		T21	6		T24	2
valid_sources[0x43]	7425	1			T2	5		T4	5		T17	52
valid_sources[0x44]	6590	1			T4	5		T17	30		T21	7
valid_sources[0x45]	6875	1			T2	1		T4	2		T17	97
valid_sources[0x46]	6808	1			T2	6		T4	4		T17	32
valid_sources[0x47]	8201	1			T2	3		T17	45		T21	6
valid_sources[0x48]	7281	1			T2	1		T17	47		T21	7
valid_sources[0x49]	9215	1			T2	3		T17	229		T21	3
valid_sources[0x4a]	6963	1			T17	65		T21	6		T19	1
valid_sources[0x4b]	7908	1			T20	8		T17	49		T19	3
valid_sources[0x4c]	7116	1			T2	3		T17	27		T21	9
valid_sources[0x4d]	7427	1			T2	4		T17	33		T21	5
valid_sources[0x4e]	7551	1			T2	4		T3	89		T4	1
valid_sources[0x4f]	6413	1			T2	1		T4	1		T17	9
valid_sources[0x50]	7839	1			T2	4		T17	65		T21	11
valid_sources[0x51]	7034	1			T2	3		T17	10		T18	5
valid_sources[0x52]	7890	1			T2	1		T4	44		T17	51
valid_sources[0x53]	7133	1			T2	1		T4	12		T17	23
valid_sources[0x54]	6875	1			T17	25		T21	9		T25	12
valid_sources[0x55]	7153	1			T2	2		T4	10		T17	40
valid_sources[0x56]	7886	1			T2	5		T17	25		T21	4
valid_sources[0x57]	7616	1			T1	1		T2	1		T17	67
valid_sources[0x58]	7167	1			T2	1		T4	8		T17	49
valid_sources[0x59]	7071	1			T4	2		T17	56		T21	4
valid_sources[0x5a]	7593	1			T1	2		T2	1		T4	16
valid_sources[0x5b]	6990	1			T17	12		T21	8		T25	12
valid_sources[0x5c]	7562	1			T4	21		T20	5		T17	58
valid_sources[0x5d]	8095	1			T17	20		T18	20		T21	10
valid_sources[0x5e]	7018	1			T17	19		T21	7		T19	1
valid_sources[0x5f]	7220	1			T17	174		T21	6		T24	3
valid_sources[0x60]	6582	1			T17	10		T21	7		T19	1
valid_sources[0x61]	7248	1			T17	49		T21	9		T24	1
valid_sources[0x62]	7488	1			T2	1		T17	30		T21	2
valid_sources[0x63]	7718	1			T2	3		T4	1		T17	28
valid_sources[0x64]	7524	1			T2	1		T17	16		T21	9
valid_sources[0x65]	8059	1			T2	1		T17	37		T21	14
valid_sources[0x66]	7846	1			T17	51		T21	3		T24	3
valid_sources[0x67]	9167	1			T2	4		T4	8		T17	106
valid_sources[0x68]	7319	1			T2	2		T3	171		T17	16
valid_sources[0x69]	7652	1			T17	47		T21	6		T24	2
valid_sources[0x6a]	7128	1			T17	71		T21	6		T19	1
valid_sources[0x6b]	7942	1			T4	1		T17	25		T18	10
valid_sources[0x6c]	7519	1			T2	1		T17	7		T21	3
valid_sources[0x6d]	7635	1			T2	3		T4	31		T17	11
valid_sources[0x6e]	7537	1			T2	1		T17	34		T21	2
valid_sources[0x6f]	7532	1			T2	2		T4	28		T17	73
valid_sources[0x70]	7729	1			T2	2		T4	1		T17	34
valid_sources[0x71]	6815	1			T2	3		T17	62		T21	4
valid_sources[0x72]	6917	1			T2	3		T17	27		T21	13
valid_sources[0x73]	7808	1			T2	1		T20	1		T17	456
valid_sources[0x74]	7208	1			T2	3		T17	55		T21	5
valid_sources[0x75]	6670	1			T2	1		T17	29		T21	8
valid_sources[0x76]	6547	1			T2	1		T17	15		T21	7
valid_sources[0x77]	7616	1			T2	1		T4	7		T17	25
valid_sources[0x78]	7935	1			T2	1		T4	3		T17	21
valid_sources[0x79]	7776	1			T4	4		T17	64		T21	5
valid_sources[0x7a]	7204	1			T2	8		T17	36		T21	5
valid_sources[0x7b]	7147	1			T2	3		T17	274		T21	8
valid_sources[0x7c]	7175	1			T20	1		T17	44		T21	7
valid_sources[0x7d]	7890	1			T2	3		T17	38		T21	9
valid_sources[0x7e]	7067	1			T2	1		T20	9		T17	6
valid_sources[0x7f]	7016	1			T2	3		T4	16		T17	5
valid_sources[0x80]	6678	1			T2	3		T4	6		T17	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27266

1

T1

2

T2

2

T3

32

values[0x0]

all_enables

biggest_size

205826

1

T1

1

T2

55

T3

175

values[0x1]

all_enables

biggest_size

27186

1

T1

2

T2

14

T3

23