Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	321252670	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	321252670	0	0
T1	719824	9497	0	0
T2	723240	16526	0	0
T3	190624	8344	0	0
T4	49414008	1600221	0	0
T16	38024	544	0	0
T17	13851320	284865	0	0
T18	7883960	233713	0	0
T19	4071816	92944	0	0
T20	6483792	100249	0	0
T21	2296672	47392	0	0
T22	0	103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	719824	718480	0	0
T2	723240	720720	0	0
T3	190624	189896	0	0
T4	49414008	49411544	0	0
T16	38024	34384	0	0
T17	13851320	13832392	0	0
T18	7883960	7879480	0	0
T19	4071816	4059664	0	0
T20	6483792	6480544	0	0
T21	2296672	2293648	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	719824	718480	0	0
T2	723240	720720	0	0
T3	190624	189896	0	0
T4	49414008	49411544	0	0
T16	38024	34384	0	0
T17	13851320	13832392	0	0
T18	7883960	7879480	0	0
T19	4071816	4059664	0	0
T20	6483792	6480544	0	0
T21	2296672	2293648	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	719824	718480	0	0
T2	723240	720720	0	0
T3	190624	189896	0	0
T4	49414008	49411544	0	0
T16	38024	34384	0	0
T17	13851320	13832392	0	0
T18	7883960	7879480	0	0
T19	4071816	4059664	0	0
T20	6483792	6480544	0	0
T21	2296672	2293648	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	115713534	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	115713534	0	0
T1	12854	4296	0	0
T2	12915	6703	0	0
T3	3404	3244	0	0
T4	882393	871007	0	0
T16	679	208	0	0
T17	247345	114530	0	0
T18	140785	138982	0	0
T19	72711	38346	0	0
T20	115782	46787	0	0
T21	41012	21323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	83820852	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	83820852	0	0
T1	12854	1462	0	0
T2	12915	3200	0	0
T3	3404	1700	0	0
T4	882393	362882	0	0
T16	679	112	0	0
T17	247345	41381	0	0
T18	140785	46982	0	0
T19	72711	18308	0	0
T20	115782	11325	0	0
T21	41012	5934	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1473714	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1473714	0	0
T1	12854	59	0	0
T2	12915	81	0	0
T3	3404	59	0	0
T4	882393	125	0	0
T16	679	7	0	0
T17	247345	3661	0	0
T18	140785	30	0	0
T19	72711	377	0	0
T20	115782	1605	0	0
T21	41012	438	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3037415	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3037415	0	0
T1	12854	28	0	0
T2	12915	105	0	0
T3	3404	59	0	0
T4	882393	13188	0	0
T16	679	7	0	0
T17	247345	1514	0	0
T18	140785	2596	0	0
T19	72711	476	0	0
T20	115782	666	0	0
T21	41012	191	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1463075	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1463075	0	0
T1	12854	101	0	0
T2	12915	117	0	0
T3	3404	62	0	0
T4	882393	113	0	0
T16	679	6	0	0
T17	247345	6030	0	0
T18	140785	7	0	0
T19	72711	2133	0	0
T20	115782	1172	0	0
T21	41012	408	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3041966	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3041966	0	0
T1	12854	30	0	0
T2	12915	72	0	0
T3	3404	62	0	0
T4	882393	12965	0	0
T16	679	6	0	0
T17	247345	2693	0	0
T18	140785	899	0	0
T19	72711	2090	0	0
T20	115782	673	0	0
T21	41012	165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1427413	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1427413	0	0
T1	12854	68	0	0
T2	12915	178	0	0
T3	3404	63	0	0
T4	882393	202	0	0
T16	679	3	0	0
T17	247345	1455	0	0
T18	140785	17	0	0
T19	72711	376	0	0
T20	115782	6	0	0
T21	41012	420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3085457	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3085457	0	0
T1	12854	13	0	0
T2	12915	149	0	0
T3	3404	63	0	0
T4	882393	14975	0	0
T16	679	3	0	0
T17	247345	683	0	0
T18	140785	892	0	0
T19	72711	405	0	0
T20	115782	150	0	0
T21	41012	275	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1438989	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1438989	0	0
T1	12854	92	0	0
T2	12915	141	0	0
T3	3404	71	0	0
T4	882393	176	0	0
T16	679	8	0	0
T17	247345	6222	0	0
T18	140785	30	0	0
T19	72711	258	0	0
T20	115782	1366	0	0
T21	41012	446	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2939148	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2939148	0	0
T1	12854	16	0	0
T2	12915	141	0	0
T3	3404	71	0	0
T4	882393	13521	0	0
T16	679	8	0	0
T17	247345	2479	0	0
T18	140785	1923	0	0
T19	72711	228	0	0
T20	115782	73	0	0
T21	41012	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1396945	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1396945	0	0
T1	12854	173	0	0
T2	12915	102	0	0
T3	3404	84	0	0
T4	882393	128	0	0
T16	679	1	0	0
T17	247345	1659	0	0
T18	140785	61	0	0
T19	72711	325	0	0
T20	115782	105	0	0
T21	41012	653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3126793	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3126793	0	0
T1	12854	103	0	0
T2	12915	90	0	0
T3	3404	84	0	0
T4	882393	15189	0	0
T16	679	1	0	0
T17	247345	670	0	0
T18	140785	3050	0	0
T19	72711	329	0	0
T20	115782	305	0	0
T21	41012	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1406417	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1406417	0	0
T1	12854	85	0	0
T2	12915	136	0	0
T3	3404	53	0	0
T4	882393	118	0	0
T16	679	6	0	0
T17	247345	4593	0	0
T18	140785	17	0	0
T19	72711	347	0	0
T20	115782	366	0	0
T21	41012	484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3489450	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3489450	0	0
T1	12854	58	0	0
T2	12915	95	0	0
T3	3404	53	0	0
T4	882393	10914	0	0
T16	679	6	0	0
T17	247345	2630	0	0
T18	140785	86	0	0
T19	72711	359	0	0
T20	115782	1	0	0
T21	41012	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1413639	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1413639	0	0
T1	12854	102	0	0
T2	12915	124	0	0
T3	3404	60	0	0
T4	882393	191	0	0
T16	679	5	0	0
T17	247345	1680	0	0
T18	140785	22	0	0
T19	72711	341	0	0
T20	115782	2843	0	0
T21	41012	463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3091048	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3091048	0	0
T1	12854	40	0	0
T2	12915	131	0	0
T3	3404	60	0	0
T4	882393	14446	0	0
T16	679	5	0	0
T17	247345	650	0	0
T18	140785	830	0	0
T19	72711	285	0	0
T20	115782	427	0	0
T21	41012	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1463977	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1463977	0	0
T1	12854	104	0	0
T2	12915	162	0	0
T3	3404	58	0	0
T4	882393	190	0	0
T16	679	4	0	0
T17	247345	1582	0	0
T18	140785	15	0	0
T19	72711	2352	0	0
T20	115782	332	0	0
T21	41012	581	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3610784	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3610784	0	0
T1	12854	48	0	0
T2	12915	141	0	0
T3	3404	58	0	0
T4	882393	13945	0	0
T16	679	4	0	0
T17	247345	821	0	0
T18	140785	1321	0	0
T19	72711	2167	0	0
T20	115782	0	0	0
T21	41012	198	0	0
T22	0	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1444544	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1444544	0	0
T1	12854	61	0	0
T2	12915	82	0	0
T3	3404	60	0	0
T4	882393	140	0	0
T16	679	3	0	0
T17	247345	2735	0	0
T18	140785	41	0	0
T19	72711	293	0	0
T20	115782	278	0	0
T21	41012	414	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2528221	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2528221	0	0
T1	12854	22	0	0
T2	12915	89	0	0
T3	3404	60	0	0
T4	882393	10811	0	0
T16	679	3	0	0
T17	247345	1397	0	0
T18	140785	3701	0	0
T19	72711	379	0	0
T20	115782	720	0	0
T21	41012	165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1473990	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1473990	0	0
T1	12854	190	0	0
T2	12915	142	0	0
T3	3404	55	0	0
T4	882393	182	0	0
T16	679	5	0	0
T17	247345	7550	0	0
T18	140785	36	0	0
T19	72711	392	0	0
T20	115782	849	0	0
T21	41012	395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3578107	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3578107	0	0
T1	12854	93	0	0
T2	12915	85	0	0
T3	3404	55	0	0
T4	882393	14211	0	0
T16	679	5	0	0
T17	247345	3432	0	0
T18	140785	2024	0	0
T19	72711	293	0	0
T20	115782	29	0	0
T21	41012	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1476300	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1476300	0	0
T1	12854	46	0	0
T2	12915	126	0	0
T3	3404	63	0	0
T4	882393	188	0	0
T16	679	5	0	0
T17	247345	1749	0	0
T18	140785	11	0	0
T19	72711	1893	0	0
T20	115782	1541	0	0
T21	41012	600	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2750448	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2750448	0	0
T1	12854	26	0	0
T2	12915	109	0	0
T3	3404	63	0	0
T4	882393	14496	0	0
T16	679	5	0	0
T17	247345	746	0	0
T18	140785	701	0	0
T19	72711	1896	0	0
T20	115782	662	0	0
T21	41012	301	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1477398	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1477398	0	0
T1	12854	36	0	0
T2	12915	177	0	0
T3	3404	68	0	0
T4	882393	191	0	0
T16	679	3	0	0
T17	247345	1561	0	0
T18	140785	33	0	0
T19	72711	360	0	0
T20	115782	522	0	0
T21	41012	534	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3783884	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3783884	0	0
T1	12854	17	0	0
T2	12915	158	0	0
T3	3404	68	0	0
T4	882393	13730	0	0
T16	679	3	0	0
T17	247345	606	0	0
T18	140785	1954	0	0
T19	72711	367	0	0
T20	115782	368	0	0
T21	41012	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1403703	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1403703	0	0
T1	12854	65	0	0
T2	12915	177	0	0
T3	3404	71	0	0
T4	882393	140	0	0
T16	679	9	0	0
T17	247345	4140	0	0
T18	140785	15	0	0
T19	72711	429	0	0
T20	115782	1532	0	0
T21	41012	513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2891154	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2891154	0	0
T1	12854	26	0	0
T2	12915	145	0	0
T3	3404	71	0	0
T4	882393	12470	0	0
T16	679	9	0	0
T17	247345	2645	0	0
T18	140785	1299	0	0
T19	72711	370	0	0
T20	115782	3	0	0
T21	41012	169	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1442950	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1442950	0	0
T1	12854	83	0	0
T2	12915	110	0	0
T3	3404	78	0	0
T4	882393	186	0	0
T16	679	2	0	0
T17	247345	3078	0	0
T18	140785	30	0	0
T19	72711	269	0	0
T20	115782	824	0	0
T21	41012	611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2224950	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2224950	0	0
T1	12854	36	0	0
T2	12915	105	0	0
T3	3404	78	0	0
T4	882393	14009	0	0
T16	679	2	0	0
T17	247345	1580	0	0
T18	140785	1030	0	0
T19	72711	255	0	0
T20	115782	477	0	0
T21	41012	233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1459805	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1459805	0	0
T1	12854	68	0	0
T2	12915	133	0	0
T3	3404	86	0	0
T4	882393	153	0	0
T16	679	2	0	0
T17	247345	3321	0	0
T18	140785	16	0	0
T19	72711	368	0	0
T20	115782	1372	0	0
T21	41012	456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3450963	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3450963	0	0
T1	12854	34	0	0
T2	12915	134	0	0
T3	3404	86	0	0
T4	882393	10071	0	0
T16	679	2	0	0
T17	247345	1391	0	0
T18	140785	1481	0	0
T19	72711	372	0	0
T20	115782	1003	0	0
T21	41012	229	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1464893	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1464893	0	0
T1	12854	194	0	0
T2	12915	124	0	0
T3	3404	55	0	0
T4	882393	176	0	0
T16	679	1	0	0
T17	247345	1821	0	0
T18	140785	26	0	0
T19	72711	459	0	0
T20	115782	2269	0	0
T21	41012	533	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3428226	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3428226	0	0
T1	12854	87	0	0
T2	12915	94	0	0
T3	3404	55	0	0
T4	882393	16432	0	0
T16	679	1	0	0
T17	247345	711	0	0
T18	140785	2199	0	0
T19	72711	392	0	0
T20	115782	805	0	0
T21	41012	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1447696	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1447696	0	0
T1	12854	132	0	0
T2	12915	166	0	0
T3	3404	66	0	0
T4	882393	177	0	0
T16	679	5	0	0
T17	247345	1529	0	0
T18	140785	37	0	0
T19	72711	441	0	0
T20	115782	1559	0	0
T21	41012	652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3822466	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3822466	0	0
T1	12854	54	0	0
T2	12915	203	0	0
T3	3404	66	0	0
T4	882393	14620	0	0
T16	679	5	0	0
T17	247345	582	0	0
T18	140785	2170	0	0
T19	72711	393	0	0
T20	115782	25	0	0
T21	41012	269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1417958	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1417958	0	0
T1	12854	53	0	0
T2	12915	52	0	0
T3	3404	59	0	0
T4	882393	159	0	0
T16	679	8	0	0
T17	247345	1639	0	0
T18	140785	56	0	0
T19	72711	337	0	0
T20	115782	1513	0	0
T21	41012	384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2496503	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2496503	0	0
T1	12854	26	0	0
T2	12915	61	0	0
T3	3404	59	0	0
T4	882393	12278	0	0
T16	679	8	0	0
T17	247345	651	0	0
T18	140785	3261	0	0
T19	72711	442	0	0
T20	115782	416	0	0
T21	41012	148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1426018	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1426018	0	0
T1	12854	72	0	0
T2	12915	157	0	0
T3	3404	66	0	0
T4	882393	160	0	0
T16	679	3	0	0
T17	247345	3911	0	0
T18	140785	43	0	0
T19	72711	248	0	0
T20	115782	791	0	0
T21	41012	605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2593379	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2593379	0	0
T1	12854	6	0	0
T2	12915	191	0	0
T3	3404	66	0	0
T4	882393	10923	0	0
T16	679	3	0	0
T17	247345	1693	0	0
T18	140785	3526	0	0
T19	72711	197	0	0
T20	115782	388	0	0
T21	41012	314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1447831	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1447831	0	0
T1	12854	100	0	0
T2	12915	167	0	0
T3	3404	57	0	0
T4	882393	233	0	0
T16	679	3	0	0
T17	247345	3110	0	0
T18	140785	36	0	0
T19	72711	1899	0	0
T20	115782	2075	0	0
T21	41012	738	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2981805	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2981805	0	0
T1	12854	55	0	0
T2	12915	173	0	0
T3	3404	57	0	0
T4	882393	16536	0	0
T16	679	3	0	0
T17	247345	1806	0	0
T18	140785	2653	0	0
T19	72711	1893	0	0
T20	115782	1758	0	0
T21	41012	208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1390813	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1390813	0	0
T1	12854	155	0	0
T2	12915	107	0	0
T3	3404	48	0	0
T4	882393	181	0	0
T16	679	4	0	0
T17	247345	2110	0	0
T18	140785	24	0	0
T19	72711	221	0	0
T20	115782	2247	0	0
T21	41012	523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3022189	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3022189	0	0
T1	12854	76	0	0
T2	12915	63	0	0
T3	3404	48	0	0
T4	882393	14283	0	0
T16	679	4	0	0
T17	247345	797	0	0
T18	140785	631	0	0
T19	72711	244	0	0
T20	115782	1083	0	0
T21	41012	187	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1415954	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1415954	0	0
T1	12854	119	0	0
T2	12915	64	0	0
T3	3404	73	0	0
T4	882393	175	0	0
T16	679	4	0	0
T17	247345	5839	0	0
T18	140785	26	0	0
T19	72711	434	0	0
T20	115782	109	0	0
T21	41012	606	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3652467	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3652467	0	0
T1	12854	46	0	0
T2	12915	106	0	0
T3	3404	73	0	0
T4	882393	14941	0	0
T16	679	4	0	0
T17	247345	2540	0	0
T18	140785	637	0	0
T19	72711	469	0	0
T20	115782	0	0	0
T21	41012	295	0	0
T22	0	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1453197	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1453197	0	0
T1	12854	140	0	0
T2	12915	151	0	0
T3	3404	64	0	0
T4	882393	133	0	0
T16	679	3	0	0
T17	247345	7475	0	0
T18	140785	58	0	0
T19	72711	309	0	0
T20	115782	1381	0	0
T21	41012	464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2661442	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2661442	0	0
T1	12854	56	0	0
T2	12915	136	0	0
T3	3404	64	0	0
T4	882393	11386	0	0
T16	679	3	0	0
T17	247345	3205	0	0
T18	140785	2959	0	0
T19	72711	319	0	0
T20	115782	96	0	0
T21	41012	268	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1422161	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1422161	0	0
T1	12854	125	0	0
T2	12915	116	0	0
T3	3404	54	0	0
T4	882393	167	0	0
T16	679	1	0	0
T17	247345	2943	0	0
T18	140785	23	0	0
T19	72711	2318	0	0
T20	115782	937	0	0
T21	41012	586	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2174569	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2174569	0	0
T1	12854	20	0	0
T2	12915	119	0	0
T3	3404	54	0	0
T4	882393	15309	0	0
T16	679	1	0	0
T17	247345	1650	0	0
T18	140785	1596	0	0
T19	72711	2269	0	0
T20	115782	257	0	0
T21	41012	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1437352	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1437352	0	0
T1	12854	76	0	0
T2	12915	70	0	0
T3	3404	57	0	0
T4	882393	140	0	0
T16	679	2	0	0
T17	247345	3813	0	0
T18	140785	17	0	0
T19	72711	320	0	0
T20	115782	520	0	0
T21	41012	484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3383625	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3383625	0	0
T1	12854	13	0	0
T2	12915	80	0	0
T3	3404	57	0	0
T4	882393	12076	0	0
T16	679	2	0	0
T17	247345	1683	0	0
T18	140785	868	0	0
T19	72711	393	0	0
T20	115782	1	0	0
T21	41012	189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1441236	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1441236	0	0
T1	12854	66	0	0
T2	12915	137	0	0
T3	3404	54	0	0
T4	882393	148	0	0
T16	679	2	0	0
T17	247345	1614	0	0
T18	140785	38	0	0
T19	72711	333	0	0
T20	115782	1183	0	0
T21	41012	474	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	3232707	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	3232707	0	0
T1	12854	34	0	0
T2	12915	93	0	0
T3	3404	54	0	0
T4	882393	10798	0	0
T16	679	2	0	0
T17	247345	648	0	0
T18	140785	1837	0	0
T19	72711	294	0	0
T20	115782	672	0	0
T21	41012	244	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	1396564	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	1396564	0	0
T1	12854	72	0	0
T2	12915	124	0	0
T3	3404	56	0	0
T4	882393	166	0	0
T16	679	7	0	0
T17	247345	1590	0	0
T18	140785	2	0	0
T19	72711	365	0	0
T20	115782	1515	0	0
T21	41012	736	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	295946747	2814586	0	0
DepthKnown_A	295946747	295826293	0	0
RvalidKnown_A	295946747	295826293	0	0
WreadyKnown_A	295946747	295826293	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	2814586	0	0
T1	12854	39	0	0
T2	12915	132	0	0
T3	3404	56	0	0
T4	882393	13371	0	0
T16	679	7	0	0
T17	247345	641	0	0
T18	140785	858	0	0
T19	72711	517	0	0
T20	115782	267	0	0
T21	41012	227	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295946747	295826293	0	0
T1	12854	12830	0	0
T2	12915	12870	0	0
T3	3404	3391	0	0
T4	882393	882349	0	0
T16	679	614	0	0
T17	247345	247007	0	0
T18	140785	140705	0	0
T19	72711	72494	0	0
T20	115782	115724	0	0
T21	41012	40958	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0