Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1617127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254705

1

T1

314

T2

25

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	633134	1			T1	779		T2	114		T3	84
values[0x0]	606418	1			T1	753		T2	16		T3	13
values[0x1]	632280	1			T1	761		T2	137		T3	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253607	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

618225

1

T1

792

T2

96

T3

70

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8773	1			T1	7		T4	132		T19	5
valid_sources[0x01]	8012	1			T1	10		T4	273		T16	4
valid_sources[0x02]	6695	1			T1	7		T4	53		T16	4
valid_sources[0x03]	7676	1			T1	12		T3	1		T4	96
valid_sources[0x04]	6930	1			T1	10		T3	1		T4	84
valid_sources[0x05]	7625	1			T1	9		T4	75		T16	3
valid_sources[0x06]	7156	1			T1	9		T2	2		T4	55
valid_sources[0x07]	6439	1			T1	9		T4	112		T16	1
valid_sources[0x08]	7402	1			T1	7		T4	44		T20	3
valid_sources[0x09]	7723	1			T1	8		T2	1		T4	20
valid_sources[0x0a]	7345	1			T1	9		T4	101		T16	2
valid_sources[0x0b]	6677	1			T1	7		T4	11		T15	20
valid_sources[0x0c]	7674	1			T1	9		T2	1		T4	30
valid_sources[0x0d]	6887	1			T1	10		T4	233		T16	1
valid_sources[0x0e]	7437	1			T1	8		T4	18		T15	18
valid_sources[0x0f]	6939	1			T1	8		T4	175		T16	2
valid_sources[0x10]	7312	1			T1	4		T4	148		T16	4
valid_sources[0x11]	7656	1			T1	11		T3	1		T4	64
valid_sources[0x12]	7024	1			T1	11		T2	1		T4	111
valid_sources[0x13]	6482	1			T1	8		T4	160		T15	17
valid_sources[0x14]	7873	1			T1	11		T2	1		T4	73
valid_sources[0x15]	7293	1			T1	14		T4	79		T16	1
valid_sources[0x16]	6885	1			T1	8		T2	5		T4	117
valid_sources[0x17]	6883	1			T1	16		T3	1		T4	146
valid_sources[0x18]	7260	1			T1	11		T3	2		T4	71
valid_sources[0x19]	7915	1			T1	11		T3	1		T4	125
valid_sources[0x1a]	6934	1			T1	7		T4	100		T15	38
valid_sources[0x1b]	6962	1			T1	8		T4	112		T14	4
valid_sources[0x1c]	6958	1			T1	7		T4	143		T16	4
valid_sources[0x1d]	6992	1			T1	6		T4	148		T15	18
valid_sources[0x1e]	7573	1			T1	13		T4	226		T16	4
valid_sources[0x1f]	6766	1			T1	11		T4	122		T16	3
valid_sources[0x20]	7480	1			T1	2		T3	8		T4	88
valid_sources[0x21]	6936	1			T1	3		T3	3		T4	31
valid_sources[0x22]	7104	1			T1	13		T4	138		T15	8
valid_sources[0x23]	7612	1			T1	7		T4	27		T19	1
valid_sources[0x24]	7458	1			T1	11		T4	109		T14	30
valid_sources[0x25]	7506	1			T1	16		T2	1		T4	45
valid_sources[0x26]	6844	1			T1	11		T4	79		T16	4
valid_sources[0x27]	6734	1			T1	15		T4	109		T14	12
valid_sources[0x28]	7586	1			T1	6		T2	1		T4	313
valid_sources[0x29]	7707	1			T1	7		T4	165		T15	20
valid_sources[0x2a]	7622	1			T1	8		T2	1		T4	395
valid_sources[0x2b]	6618	1			T1	8		T4	90		T15	11
valid_sources[0x2c]	7568	1			T1	10		T4	96		T16	1
valid_sources[0x2d]	7375	1			T1	8		T3	2		T4	402
valid_sources[0x2e]	6834	1			T1	11		T3	1		T4	115
valid_sources[0x2f]	6925	1			T1	12		T4	88		T20	1
valid_sources[0x30]	8254	1			T1	7		T3	4		T4	173
valid_sources[0x31]	7206	1			T1	3		T4	231		T16	1
valid_sources[0x32]	6584	1			T1	3		T4	70		T16	1
valid_sources[0x33]	7710	1			T1	13		T3	34		T4	195
valid_sources[0x34]	6708	1			T1	8		T2	5		T4	59
valid_sources[0x35]	6998	1			T1	6		T4	47		T16	2
valid_sources[0x36]	7371	1			T1	9		T3	1		T4	80
valid_sources[0x37]	6856	1			T1	3		T3	4		T4	132
valid_sources[0x38]	7685	1			T1	7		T4	126		T16	2
valid_sources[0x39]	6964	1			T1	4		T4	148		T16	6
valid_sources[0x3a]	6894	1			T1	7		T4	79		T15	16
valid_sources[0x3b]	6836	1			T1	10		T4	50		T15	13
valid_sources[0x3c]	8552	1			T1	10		T4	79		T16	1
valid_sources[0x3d]	7201	1			T1	12		T3	1		T4	83
valid_sources[0x3e]	7384	1			T1	15		T4	64		T16	4
valid_sources[0x3f]	7478	1			T1	14		T4	122		T15	3
valid_sources[0x40]	7986	1			T1	7		T2	1		T4	133
valid_sources[0x41]	7373	1			T1	7		T3	2		T4	99
valid_sources[0x42]	6368	1			T1	6		T4	41		T16	6
valid_sources[0x43]	7803	1			T1	8		T4	188		T15	12
valid_sources[0x44]	6604	1			T1	17		T4	31		T16	2
valid_sources[0x45]	6937	1			T1	10		T2	18		T4	84
valid_sources[0x46]	7385	1			T1	13		T2	2		T3	7
valid_sources[0x47]	7106	1			T1	10		T4	119		T15	11
valid_sources[0x48]	7333	1			T1	12		T4	69		T16	6
valid_sources[0x49]	7165	1			T1	3		T4	106		T16	2
valid_sources[0x4a]	8044	1			T1	8		T4	201		T16	2
valid_sources[0x4b]	6898	1			T1	10		T4	70		T16	3
valid_sources[0x4c]	7294	1			T1	12		T4	28		T19	3
valid_sources[0x4d]	8374	1			T1	11		T3	2		T4	172
valid_sources[0x4e]	7237	1			T1	7		T4	9		T16	2
valid_sources[0x4f]	6948	1			T1	11		T4	121		T16	2
valid_sources[0x50]	6897	1			T1	8		T4	27		T15	11
valid_sources[0x51]	6678	1			T1	10		T4	89		T16	3
valid_sources[0x52]	7584	1			T1	13		T3	1		T4	45
valid_sources[0x53]	8848	1			T1	12		T4	159		T16	9
valid_sources[0x54]	6517	1			T1	6		T4	51		T16	1
valid_sources[0x55]	7366	1			T1	6		T3	1		T4	199
valid_sources[0x56]	8013	1			T1	11		T3	2		T4	105
valid_sources[0x57]	7135	1			T1	8		T2	2		T4	148
valid_sources[0x58]	6808	1			T1	6		T4	173		T15	12
valid_sources[0x59]	8510	1			T1	10		T4	413		T14	8
valid_sources[0x5a]	10417	1			T1	7		T4	158		T14	31
valid_sources[0x5b]	6870	1			T1	9		T4	41		T16	3
valid_sources[0x5c]	8646	1			T1	9		T2	1		T4	142
valid_sources[0x5d]	7679	1			T1	8		T2	3		T4	127
valid_sources[0x5e]	7331	1			T1	6		T4	549		T14	11
valid_sources[0x5f]	6416	1			T1	4		T3	1		T4	152
valid_sources[0x60]	7066	1			T1	9		T3	2		T4	82
valid_sources[0x61]	6915	1			T1	7		T2	1		T4	155
valid_sources[0x62]	7088	1			T1	8		T4	52		T15	14
valid_sources[0x63]	6733	1			T1	12		T2	2		T4	60
valid_sources[0x64]	7525	1			T1	13		T4	184		T15	12
valid_sources[0x65]	7967	1			T1	10		T3	2		T4	135
valid_sources[0x66]	7672	1			T1	5		T4	135		T15	30
valid_sources[0x67]	7605	1			T1	9		T3	1		T4	327
valid_sources[0x68]	7350	1			T1	10		T4	78		T16	3
valid_sources[0x69]	6725	1			T1	9		T4	53		T15	8
valid_sources[0x6a]	6916	1			T1	8		T4	102		T16	3
valid_sources[0x6b]	7863	1			T1	13		T4	85		T16	4
valid_sources[0x6c]	6978	1			T1	9		T4	127		T16	5
valid_sources[0x6d]	7032	1			T1	6		T4	367		T15	8
valid_sources[0x6e]	6716	1			T1	9		T4	114		T15	6
valid_sources[0x6f]	7590	1			T1	13		T2	1		T4	119
valid_sources[0x70]	6411	1			T1	7		T4	38		T15	23
valid_sources[0x71]	6762	1			T1	9		T4	163		T15	19
valid_sources[0x72]	9614	1			T1	12		T3	11		T4	353
valid_sources[0x73]	8959	1			T1	8		T2	71		T4	94
valid_sources[0x74]	6918	1			T1	12		T4	146		T19	2
valid_sources[0x75]	7897	1			T1	11		T4	184		T15	26
valid_sources[0x76]	6882	1			T1	6		T2	1		T4	72
valid_sources[0x77]	7038	1			T1	14		T4	54		T15	11
valid_sources[0x78]	6973	1			T1	11		T2	2		T4	123
valid_sources[0x79]	6848	1			T1	8		T3	2		T4	75
valid_sources[0x7a]	8025	1			T1	14		T2	8		T4	51
valid_sources[0x7b]	7808	1			T1	8		T2	62		T4	249
valid_sources[0x7c]	7529	1			T1	8		T3	16		T4	23
valid_sources[0x7d]	8620	1			T1	9		T4	36		T15	5
valid_sources[0x7e]	7248	1			T1	12		T2	1		T4	55
valid_sources[0x7f]	8058	1			T1	15		T3	20		T4	269
valid_sources[0x80]	6983	1			T1	11		T2	1		T4	70

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26863

1

T1

25

T2

7

T3

6

values[0x0]

all_enables

biggest_size

201234

1

T1

251

T2

8

T3

6

values[0x1]

all_enables

biggest_size

26608

1

T1

38

T2

10

T3

9