Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	355642344	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	355642344	0	0
T1	264432	11262	0	0
T2	724920	28392	0	0
T3	449680	16979	0	0
T4	51971192	1138308	0	0
T14	17966424	2079460	0	0
T15	3026408	44556	0	0
T16	23700768	531999	0	0
T17	36232	0	0	0
T18	40488	941	0	0
T19	26220544	492748	0	0
T20	0	248469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	264432	261912	0	0
T2	724920	699944	0	0
T3	449680	436800	0	0
T4	51971192	51965760	0	0
T14	17966424	17966088	0	0
T15	3026408	3024280	0	0
T16	23700768	23693712	0	0
T17	36232	21168	0	0
T18	40488	37912	0	0
T19	26220544	26175016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	264432	261912	0	0
T2	724920	699944	0	0
T3	449680	436800	0	0
T4	51971192	51965760	0	0
T14	17966424	17966088	0	0
T15	3026408	3024280	0	0
T16	23700768	23693712	0	0
T17	36232	21168	0	0
T18	40488	37912	0	0
T19	26220544	26175016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	264432	261912	0	0
T2	724920	699944	0	0
T3	449680	436800	0	0
T4	51971192	51965760	0	0
T14	17966424	17966088	0	0
T15	3026408	3024280	0	0
T16	23700768	23693712	0	0
T17	36232	21168	0	0
T18	40488	37912	0	0
T19	26220544	26175016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	127903409	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	127903409	0	0
T1	4722	4383	0	0
T2	12945	11756	0	0
T3	8030	7348	0	0
T4	928057	439872	0	0
T14	320829	156673	0	0
T15	54043	11086	0	0
T16	423228	192701	0	0
T17	647	0	0	0
T18	723	365	0	0
T19	468224	217438	0	0
T20	0	106680	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	93173361	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	93173361	0	0
T1	4722	2293	0	0
T2	12945	6112	0	0
T3	8030	3807	0	0
T4	928057	259127	0	0
T14	320829	564696	0	0
T15	54043	11206	0	0
T16	423228	117740	0	0
T17	647	0	0	0
T18	723	192	0	0
T19	468224	66513	0	0
T20	0	44444	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1533081	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1533081	0	0
T1	4722	71	0	0
T2	12945	379	0	0
T3	8030	90	0	0
T4	928057	7016	0	0
T14	320829	26415	0	0
T15	54043	396	0	0
T16	423228	4383	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	7170	0	0
T20	0	2295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3284750	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3284750	0	0
T1	4722	71	0	0
T2	12945	379	0	0
T3	8030	90	0	0
T4	928057	7148	0	0
T14	320829	21434	0	0
T15	54043	351	0	0
T16	423228	4326	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	3066	0	0
T20	0	813	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1602442	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1602442	0	0
T1	4722	74	0	0
T2	12945	158	0	0
T3	8030	64	0	0
T4	928057	5120	0	0
T14	320829	35692	0	0
T15	54043	405	0	0
T16	423228	2444	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	4537	0	0
T20	0	4012	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	4101728	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	4101728	0	0
T1	4722	74	0	0
T2	12945	158	0	0
T3	8030	64	0	0
T4	928057	5197	0	0
T14	320829	21244	0	0
T15	54043	466	0	0
T16	423228	2339	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	2004	0	0
T20	0	3365	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1577228	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1577228	0	0
T1	4722	84	0	0
T2	12945	143	0	0
T3	8030	72	0	0
T4	928057	12866	0	0
T14	320829	29446	0	0
T15	54043	314	0	0
T16	423228	7751	0	0
T17	647	0	0	0
T18	723	10	0	0
T19	468224	4570	0	0
T20	0	2391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3639349	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3639349	0	0
T1	4722	84	0	0
T2	12945	143	0	0
T3	8030	72	0	0
T4	928057	13343	0	0
T14	320829	24233	0	0
T15	54043	385	0	0
T16	423228	7059	0	0
T17	647	0	0	0
T18	723	10	0	0
T19	468224	2097	0	0
T20	0	2569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1525613	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1525613	0	0
T1	4722	90	0	0
T2	12945	137	0	0
T3	8030	76	0	0
T4	928057	7639	0	0
T14	320829	25173	0	0
T15	54043	537	0	0
T16	423228	6249	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	7549	0	0
T20	0	852	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	2975866	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	2975866	0	0
T1	4722	90	0	0
T2	12945	137	0	0
T3	8030	76	0	0
T4	928057	7583	0	0
T14	320829	20999	0	0
T15	54043	508	0	0
T16	423228	6101	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	3536	0	0
T20	0	1678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1611939	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1611939	0	0
T1	4722	70	0	0
T2	12945	153	0	0
T3	8030	89	0	0
T4	928057	8365	0	0
T14	320829	26105	0	0
T15	54043	348	0	0
T16	423228	6535	0	0
T17	647	0	0	0
T18	723	9	0	0
T19	468224	4503	0	0
T20	0	900	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3997367	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3997367	0	0
T1	4722	70	0	0
T2	12945	153	0	0
T3	8030	89	0	0
T4	928057	8763	0	0
T14	320829	22316	0	0
T15	54043	333	0	0
T16	423228	6278	0	0
T17	647	0	0	0
T18	723	9	0	0
T19	468224	2142	0	0
T20	0	1213	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1571635	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1571635	0	0
T1	4722	79	0	0
T2	12945	138	0	0
T3	8030	73	0	0
T4	928057	8837	0	0
T14	320829	27380	0	0
T15	54043	347	0	0
T16	423228	2634	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	4809	0	0
T20	0	1473	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3277761	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3277761	0	0
T1	4722	79	0	0
T2	12945	138	0	0
T3	8030	73	0	0
T4	928057	8630	0	0
T14	320829	21105	0	0
T15	54043	433	0	0
T16	423228	2565	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	2093	0	0
T20	0	1781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1564860	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1564860	0	0
T1	4722	83	0	0
T2	12945	122	0	0
T3	8030	503	0	0
T4	928057	6854	0	0
T14	320829	27987	0	0
T15	54043	357	0	0
T16	423228	2497	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	4648	0	0
T20	0	2986	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3858869	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3858869	0	0
T1	4722	83	0	0
T2	12945	122	0	0
T3	8030	503	0	0
T4	928057	6616	0	0
T14	320829	25101	0	0
T15	54043	287	0	0
T16	423228	2556	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	2277	0	0
T20	0	2548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1564390	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1564390	0	0
T1	4722	91	0	0
T2	12945	391	0	0
T3	8030	74	0	0
T4	928057	5060	0	0
T14	320829	32005	0	0
T15	54043	463	0	0
T16	423228	4394	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	4815	0	0
T20	0	782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3352885	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3352885	0	0
T1	4722	91	0	0
T2	12945	391	0	0
T3	8030	74	0	0
T4	928057	5496	0	0
T14	320829	23247	0	0
T15	54043	423	0	0
T16	423228	4346	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	2187	0	0
T20	0	957	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1557696	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1557696	0	0
T1	4722	67	0	0
T2	12945	155	0	0
T3	8030	70	0	0
T4	928057	9007	0	0
T14	320829	26919	0	0
T15	54043	432	0	0
T16	423228	4420	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	4119	0	0
T20	0	1261	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3639722	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3639722	0	0
T1	4722	67	0	0
T2	12945	155	0	0
T3	8030	70	0	0
T4	928057	9566	0	0
T14	320829	18504	0	0
T15	54043	458	0	0
T16	423228	4108	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	1889	0	0
T20	0	540	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1531133	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1531133	0	0
T1	4722	76	0	0
T2	12945	147	0	0
T3	8030	96	0	0
T4	928057	8536	0	0
T14	320829	30199	0	0
T15	54043	435	0	0
T16	423228	2405	0	0
T17	647	0	0	0
T18	723	8	0	0
T19	468224	4459	0	0
T20	0	2568	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	2773784	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	2773784	0	0
T1	4722	76	0	0
T2	12945	147	0	0
T3	8030	96	0	0
T4	928057	8683	0	0
T14	320829	20119	0	0
T15	54043	484	0	0
T16	423228	2489	0	0
T17	647	0	0	0
T18	723	8	0	0
T19	468224	2109	0	0
T20	0	1746	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1629130	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1629130	0	0
T1	4722	101	0	0
T2	12945	134	0	0
T3	8030	195	0	0
T4	928057	4719	0	0
T14	320829	31206	0	0
T15	54043	388	0	0
T16	423228	2716	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	6309	0	0
T20	0	2688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3120773	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3120773	0	0
T1	4722	101	0	0
T2	12945	134	0	0
T3	8030	195	0	0
T4	928057	4699	0	0
T14	320829	19195	0	0
T15	54043	379	0	0
T16	423228	2652	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	3145	0	0
T20	0	2563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1530921	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1530921	0	0
T1	4722	76	0	0
T2	12945	248	0	0
T3	8030	72	0	0
T4	928057	7869	0	0
T14	320829	34115	0	0
T15	54043	357	0	0
T16	423228	4539	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	4497	0	0
T20	0	1413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3925623	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3925623	0	0
T1	4722	76	0	0
T2	12945	248	0	0
T3	8030	72	0	0
T4	928057	7403	0	0
T14	320829	22360	0	0
T15	54043	339	0	0
T16	423228	4379	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	2035	0	0
T20	0	764	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1566308	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1566308	0	0
T1	4722	81	0	0
T2	12945	444	0	0
T3	8030	78	0	0
T4	928057	7340	0	0
T14	320829	28395	0	0
T15	54043	436	0	0
T16	423228	4790	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	4927	0	0
T20	0	1762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3804294	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3804294	0	0
T1	4722	81	0	0
T2	12945	444	0	0
T3	8030	78	0	0
T4	928057	7086	0	0
T14	320829	22591	0	0
T15	54043	418	0	0
T16	423228	4765	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	2248	0	0
T20	0	1608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1531165	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1531165	0	0
T1	4722	108	0	0
T2	12945	146	0	0
T3	8030	75	0	0
T4	928057	10353	0	0
T14	320829	36808	0	0
T15	54043	404	0	0
T16	423228	4588	0	0
T17	647	0	0	0
T18	723	12	0	0
T19	468224	4537	0	0
T20	0	186	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3604851	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3604851	0	0
T1	4722	108	0	0
T2	12945	146	0	0
T3	8030	75	0	0
T4	928057	10395	0	0
T14	320829	19467	0	0
T15	54043	486	0	0
T16	423228	4529	0	0
T17	647	0	0	0
T18	723	12	0	0
T19	468224	2003	0	0
T20	0	417	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1547181	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1547181	0	0
T1	4722	68	0	0
T2	12945	136	0	0
T3	8030	109	0	0
T4	928057	12264	0	0
T14	320829	28743	0	0
T15	54043	453	0	0
T16	423228	3887	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	6510	0	0
T20	0	1838	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	2915052	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	2915052	0	0
T1	4722	68	0	0
T2	12945	136	0	0
T3	8030	109	0	0
T4	928057	12784	0	0
T14	320829	15685	0	0
T15	54043	469	0	0
T16	423228	3775	0	0
T17	647	0	0	0
T18	723	4	0	0
T19	468224	3154	0	0
T20	0	907	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1550847	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1550847	0	0
T1	4722	77	0	0
T2	12945	144	0	0
T3	8030	335	0	0
T4	928057	7002	0	0
T14	320829	25821	0	0
T15	54043	386	0	0
T16	423228	4540	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	6403	0	0
T20	0	2951	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3556420	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3556420	0	0
T1	4722	77	0	0
T2	12945	144	0	0
T3	8030	335	0	0
T4	928057	6897	0	0
T14	320829	14597	0	0
T15	54043	355	0	0
T16	423228	4391	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	2832	0	0
T20	0	1914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1590224	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1590224	0	0
T1	4722	94	0	0
T2	12945	162	0	0
T3	8030	70	0	0
T4	928057	4919	0	0
T14	320829	27881	0	0
T15	54043	227	0	0
T16	423228	2524	0	0
T17	647	0	0	0
T18	723	14	0	0
T19	468224	8607	0	0
T20	0	2424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3633655	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3633655	0	0
T1	4722	94	0	0
T2	12945	162	0	0
T3	8030	70	0	0
T4	928057	4800	0	0
T14	320829	18396	0	0
T15	54043	223	0	0
T16	423228	2447	0	0
T17	647	0	0	0
T18	723	14	0	0
T19	468224	3999	0	0
T20	0	2236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1545173	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1545173	0	0
T1	4722	87	0	0
T2	12945	140	0	0
T3	8030	81	0	0
T4	928057	6396	0	0
T14	320829	23832	0	0
T15	54043	607	0	0
T16	423228	4406	0	0
T17	647	0	0	0
T18	723	10	0	0
T19	468224	4512	0	0
T20	0	1445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3291064	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3291064	0	0
T1	4722	87	0	0
T2	12945	140	0	0
T3	8030	81	0	0
T4	928057	6713	0	0
T14	320829	18046	0	0
T15	54043	413	0	0
T16	423228	4370	0	0
T17	647	0	0	0
T18	723	10	0	0
T19	468224	1953	0	0
T20	0	1249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1518105	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1518105	0	0
T1	4722	73	0	0
T2	12945	119	0	0
T3	8030	82	0	0
T4	928057	11719	0	0
T14	320829	26811	0	0
T15	54043	529	0	0
T16	423228	4539	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	4339	0	0
T20	0	2587	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	4505707	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	4505707	0	0
T1	4722	73	0	0
T2	12945	119	0	0
T3	8030	82	0	0
T4	928057	11668	0	0
T14	320829	20782	0	0
T15	54043	499	0	0
T16	423228	4453	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	1952	0	0
T20	0	1517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1558829	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1558829	0	0
T1	4722	98	0	0
T2	12945	150	0	0
T3	8030	85	0	0
T4	928057	7689	0	0
T14	320829	30413	0	0
T15	54043	454	0	0
T16	423228	2326	0	0
T17	647	0	0	0
T18	723	11	0	0
T19	468224	4654	0	0
T20	0	2199	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3001165	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3001165	0	0
T1	4722	98	0	0
T2	12945	150	0	0
T3	8030	85	0	0
T4	928057	7853	0	0
T14	320829	21879	0	0
T15	54043	336	0	0
T16	423228	2137	0	0
T17	647	0	0	0
T18	723	11	0	0
T19	468224	2100	0	0
T20	0	3021	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1571493	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1571493	0	0
T1	4722	92	0	0
T2	12945	157	0	0
T3	8030	78	0	0
T4	928057	9334	0	0
T14	320829	28585	0	0
T15	54043	394	0	0
T16	423228	4388	0	0
T17	647	0	0	0
T18	723	8	0	0
T19	468224	6481	0	0
T20	0	1730	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3289749	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3289749	0	0
T1	4722	92	0	0
T2	12945	157	0	0
T3	8030	78	0	0
T4	928057	10994	0	0
T14	320829	23662	0	0
T15	54043	456	0	0
T16	423228	3949	0	0
T17	647	0	0	0
T18	723	8	0	0
T19	468224	2852	0	0
T20	0	322	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1615867	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1615867	0	0
T1	4722	95	0	0
T2	12945	128	0	0
T3	8030	83	0	0
T4	928057	6866	0	0
T14	320829	30485	0	0
T15	54043	408	0	0
T16	423228	4337	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	5780	0	0
T20	0	977	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3658785	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3658785	0	0
T1	4722	95	0	0
T2	12945	128	0	0
T3	8030	83	0	0
T4	928057	7317	0	0
T14	320829	24687	0	0
T15	54043	470	0	0
T16	423228	4154	0	0
T17	647	0	0	0
T18	723	5	0	0
T19	468224	2973	0	0
T20	0	767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1569420	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1569420	0	0
T1	4722	93	0	0
T2	12945	374	0	0
T3	8030	59	0	0
T4	928057	12400	0	0
T14	320829	29352	0	0
T15	54043	318	0	0
T16	423228	4195	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	4442	0	0
T20	0	1634	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	2513589	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	2513589	0	0
T1	4722	93	0	0
T2	12945	374	0	0
T3	8030	59	0	0
T4	928057	12198	0	0
T14	320829	22859	0	0
T15	54043	359	0	0
T16	423228	4076	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	2073	0	0
T20	0	1993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1583644	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1583644	0	0
T1	4722	89	0	0
T2	12945	141	0	0
T3	8030	79	0	0
T4	928057	7224	0	0
T14	320829	24125	0	0
T15	54043	536	0	0
T16	423228	6199	0	0
T17	647	0	0	0
T18	723	9	0	0
T19	468224	4135	0	0
T20	0	1269	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	2825092	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	2825092	0	0
T1	4722	89	0	0
T2	12945	141	0	0
T3	8030	79	0	0
T4	928057	7333	0	0
T14	320829	17584	0	0
T15	54043	525	0	0
T16	423228	6529	0	0
T17	647	0	0	0
T18	723	9	0	0
T19	468224	1886	0	0
T20	0	1745	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1584268	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1584268	0	0
T1	4722	101	0	0
T2	12945	127	0	0
T3	8030	85	0	0
T4	928057	6463	0	0
T14	320829	31502	0	0
T15	54043	339	0	0
T16	423228	4003	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	4727	0	0
T20	0	1308	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3002836	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3002836	0	0
T1	4722	101	0	0
T2	12945	127	0	0
T3	8030	85	0	0
T4	928057	6946	0	0
T14	320829	18402	0	0
T15	54043	355	0	0
T16	423228	3587	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	2014	0	0
T20	0	1714	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1525109	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1525109	0	0
T1	4722	94	0	0
T2	12945	160	0	0
T3	8030	62	0	0
T4	928057	8842	0	0
T14	320829	35148	0	0
T15	54043	449	0	0
T16	423228	2452	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	4613	0	0
T20	0	5079	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3571371	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3571371	0	0
T1	4722	94	0	0
T2	12945	160	0	0
T3	8030	62	0	0
T4	928057	9166	0	0
T14	320829	21602	0	0
T15	54043	555	0	0
T16	423228	2473	0	0
T17	647	0	0	0
T18	723	7	0	0
T19	468224	2110	0	0
T20	0	2317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	1589329	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	1589329	0	0
T1	4722	81	0	0
T2	12945	429	0	0
T3	8030	77	0	0
T4	928057	6777	0	0
T14	320829	32853	0	0
T15	54043	363	0	0
T16	423228	4377	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	6598	0	0
T20	0	1891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329862291	3196437	0	0
DepthKnown_A	329862291	329737811	0	0
RvalidKnown_A	329862291	329737811	0	0
WreadyKnown_A	329862291	329737811	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	3196437	0	0
T1	4722	81	0	0
T2	12945	429	0	0
T3	8030	77	0	0
T4	928057	6556	0	0
T14	320829	24599	0	0
T15	54043	417	0	0
T16	423228	4207	0	0
T17	647	0	0	0
T18	723	6	0	0
T19	468224	2818	0	0
T20	0	2180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329862291	329737811	0	0
T1	4722	4677	0	0
T2	12945	12499	0	0
T3	8030	7800	0	0
T4	928057	927960	0	0
T14	320829	320823	0	0
T15	54043	54005	0	0
T16	423228	423102	0	0
T17	647	378	0	0
T18	723	677	0	0
T19	468224	467411	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0