Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1794866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282810

1

T1

25

T2

29

T3

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	701970	1			T1	65		T2	124		T3	476
values[0x0]	673754	1			T1	17		T2	82		T3	80
values[0x1]	701952	1			T1	66		T2	129		T3	457

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1392772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

684904

1

T1

71

T2

99

T3

387

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8183	1			T3	5		T4	8		T9	39
valid_sources[0x01]	7919	1			T3	3		T4	23		T9	46
valid_sources[0x02]	8196	1			T2	1		T3	5		T4	14
valid_sources[0x03]	7858	1			T2	10		T3	3		T4	12
valid_sources[0x04]	8006	1			T1	1		T3	1		T4	10
valid_sources[0x05]	7918	1			T1	1		T3	5		T4	36
valid_sources[0x06]	8958	1			T2	2		T3	3		T4	8
valid_sources[0x07]	7731	1			T1	1		T3	3		T4	11
valid_sources[0x08]	9034	1			T1	1		T2	2		T3	3
valid_sources[0x09]	7845	1			T3	3		T4	15		T9	41
valid_sources[0x0a]	8299	1			T1	2		T2	2		T3	5
valid_sources[0x0b]	7858	1			T3	3		T4	30		T9	34
valid_sources[0x0c]	8219	1			T2	1		T3	3		T4	7
valid_sources[0x0d]	7644	1			T2	2		T3	3		T4	3
valid_sources[0x0e]	7721	1			T1	1		T2	1		T3	1
valid_sources[0x0f]	8060	1			T2	4		T3	4		T4	19
valid_sources[0x10]	7335	1			T3	5		T14	2		T9	36
valid_sources[0x11]	8640	1			T3	4		T4	16		T9	43
valid_sources[0x12]	8108	1			T3	6		T4	9		T5	2
valid_sources[0x13]	9985	1			T1	1		T2	1		T3	1
valid_sources[0x14]	8361	1			T2	2		T3	2		T4	1
valid_sources[0x15]	7915	1			T1	1		T2	5		T3	3
valid_sources[0x16]	7438	1			T3	4		T4	18		T14	1
valid_sources[0x17]	7860	1			T1	1		T2	1		T3	4
valid_sources[0x18]	8217	1			T2	1		T3	3		T4	20
valid_sources[0x19]	8409	1			T1	3		T2	5		T3	7
valid_sources[0x1a]	8588	1			T1	1		T2	3		T3	4
valid_sources[0x1b]	8244	1			T3	6		T4	12		T5	1
valid_sources[0x1c]	7674	1			T2	1		T3	5		T4	9
valid_sources[0x1d]	7247	1			T2	4		T3	4		T4	7
valid_sources[0x1e]	7650	1			T2	1		T3	4		T4	21
valid_sources[0x1f]	8764	1			T1	1		T2	5		T3	4
valid_sources[0x20]	8457	1			T1	2		T3	3		T4	21
valid_sources[0x21]	8356	1			T2	1		T3	7		T4	8
valid_sources[0x22]	7852	1			T3	7		T4	11		T9	61
valid_sources[0x23]	8250	1			T1	1		T2	1		T3	2
valid_sources[0x24]	7928	1			T3	7		T4	14		T14	1
valid_sources[0x25]	7626	1			T3	6		T4	16		T9	42
valid_sources[0x26]	7813	1			T1	1		T2	2		T3	3
valid_sources[0x27]	7820	1			T2	1		T3	8		T4	9
valid_sources[0x28]	8454	1			T3	9		T14	1		T9	37
valid_sources[0x29]	8222	1			T2	1		T3	2		T4	30
valid_sources[0x2a]	8277	1			T1	1		T3	6		T4	10
valid_sources[0x2b]	7928	1			T1	2		T2	1		T3	1
valid_sources[0x2c]	7524	1			T1	1		T2	1		T3	6
valid_sources[0x2d]	8868	1			T1	1		T3	4		T4	32
valid_sources[0x2e]	7930	1			T3	5		T4	10		T9	50
valid_sources[0x2f]	8053	1			T2	1		T3	5		T4	24
valid_sources[0x30]	7739	1			T3	3		T4	8		T9	39
valid_sources[0x31]	8082	1			T1	1		T3	8		T4	10
valid_sources[0x32]	8049	1			T2	6		T3	3		T4	21
valid_sources[0x33]	8680	1			T3	3		T4	4		T14	2
valid_sources[0x34]	8174	1			T1	1		T3	2		T4	8
valid_sources[0x35]	7879	1			T1	1		T2	2		T3	2
valid_sources[0x36]	8277	1			T3	2		T4	6		T9	36
valid_sources[0x37]	7574	1			T1	1		T3	2		T4	22
valid_sources[0x38]	8058	1			T1	1		T2	2		T3	4
valid_sources[0x39]	7720	1			T2	3		T3	4		T4	21
valid_sources[0x3a]	8195	1			T2	1		T3	3		T4	6
valid_sources[0x3b]	8225	1			T2	2		T3	3		T4	10
valid_sources[0x3c]	7967	1			T3	3		T4	15		T5	3
valid_sources[0x3d]	8242	1			T2	1		T3	5		T4	4
valid_sources[0x3e]	7720	1			T3	3		T4	16		T14	2
valid_sources[0x3f]	8708	1			T1	1		T3	7		T4	22
valid_sources[0x40]	9516	1			T1	1		T3	3		T4	10
valid_sources[0x41]	7568	1			T3	1		T4	34		T9	28
valid_sources[0x42]	8107	1			T2	4		T3	5		T4	8
valid_sources[0x43]	7969	1			T1	1		T4	2		T5	5
valid_sources[0x44]	8744	1			T1	1		T2	1		T3	2
valid_sources[0x45]	8380	1			T2	2		T3	8		T4	4
valid_sources[0x46]	8257	1			T2	4		T3	4		T4	7
valid_sources[0x47]	8852	1			T1	1		T3	4		T4	29
valid_sources[0x48]	7440	1			T2	4		T3	2		T4	15
valid_sources[0x49]	7892	1			T3	6		T4	3		T14	1
valid_sources[0x4a]	7724	1			T3	4		T4	19		T5	2
valid_sources[0x4b]	8184	1			T3	2		T5	3		T9	55
valid_sources[0x4c]	8521	1			T1	1		T2	7		T3	6
valid_sources[0x4d]	8253	1			T1	1		T3	5		T4	13
valid_sources[0x4e]	7702	1			T3	3		T4	33		T9	66
valid_sources[0x4f]	7603	1			T1	1		T3	4		T4	20
valid_sources[0x50]	8333	1			T1	3		T3	5		T4	9
valid_sources[0x51]	7728	1			T1	1		T3	4		T4	16
valid_sources[0x52]	8111	1			T2	1		T3	1		T4	9
valid_sources[0x53]	7880	1			T3	8		T4	7		T5	1
valid_sources[0x54]	7760	1			T3	4		T4	8		T9	45
valid_sources[0x55]	8521	1			T2	1		T3	3		T4	24
valid_sources[0x56]	8146	1			T2	4		T3	4		T4	6
valid_sources[0x57]	7500	1			T3	5		T4	40		T9	28
valid_sources[0x58]	8702	1			T2	1		T3	4		T4	2
valid_sources[0x59]	8634	1			T3	2		T4	3		T9	46
valid_sources[0x5a]	7858	1			T1	1		T3	2		T4	9
valid_sources[0x5b]	8831	1			T1	1		T3	2		T4	12
valid_sources[0x5c]	8412	1			T1	1		T2	2		T3	7
valid_sources[0x5d]	7468	1			T1	1		T3	2		T4	9
valid_sources[0x5e]	7780	1			T3	6		T4	17		T9	40
valid_sources[0x5f]	7723	1			T3	3		T4	5		T5	3
valid_sources[0x60]	8059	1			T3	3		T4	16		T5	2
valid_sources[0x61]	8179	1			T1	1		T2	2		T3	3
valid_sources[0x62]	7735	1			T1	2		T2	1		T3	1
valid_sources[0x63]	8213	1			T2	5		T3	7		T4	16
valid_sources[0x64]	8310	1			T1	1		T2	10		T3	5
valid_sources[0x65]	8609	1			T2	8		T3	4		T4	2
valid_sources[0x66]	7363	1			T1	1		T2	1		T3	4
valid_sources[0x67]	7513	1			T2	1		T3	1		T4	9
valid_sources[0x68]	8220	1			T3	6		T4	14		T9	55
valid_sources[0x69]	8268	1			T1	1		T3	3		T4	5
valid_sources[0x6a]	8792	1			T1	1		T3	5		T4	4
valid_sources[0x6b]	8532	1			T2	2		T3	1		T4	1
valid_sources[0x6c]	8331	1			T1	1		T2	4		T3	2
valid_sources[0x6d]	7341	1			T1	1		T2	3		T3	5
valid_sources[0x6e]	8232	1			T1	1		T3	7		T4	30
valid_sources[0x6f]	7545	1			T3	6		T4	9		T14	1
valid_sources[0x70]	8230	1			T1	1		T3	3		T4	20
valid_sources[0x71]	8091	1			T2	3		T3	3		T4	7
valid_sources[0x72]	8329	1			T1	3		T3	10		T4	13
valid_sources[0x73]	8008	1			T1	3		T2	1		T3	2
valid_sources[0x74]	9369	1			T1	1		T3	1		T4	4
valid_sources[0x75]	8420	1			T2	6		T3	2		T9	41
valid_sources[0x76]	7897	1			T1	1		T3	7		T4	24
valid_sources[0x77]	8385	1			T1	1		T2	1		T3	5
valid_sources[0x78]	8063	1			T2	6		T3	3		T4	14
valid_sources[0x79]	7764	1			T2	1		T3	2		T4	26
valid_sources[0x7a]	7236	1			T2	7		T3	4		T4	1
valid_sources[0x7b]	7473	1			T1	1		T2	2		T3	5
valid_sources[0x7c]	7861	1			T3	2		T4	2		T9	38
valid_sources[0x7d]	8239	1			T1	2		T2	5		T3	4
valid_sources[0x7e]	8547	1			T3	2		T4	7		T9	65
valid_sources[0x7f]	8250	1			T1	1		T3	10		T4	22
valid_sources[0x80]	8334	1			T2	4		T3	4		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29687

1

T1

4

T2

3

T3

38

values[0x0]

all_enables

biggest_size

223494

1

T1

8

T2

24

T3

34

values[0x1]

all_enables

biggest_size

29629

1

T1

13

T2

2

T3

28