Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	340883170	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	340883170	0	0
T1	345296	14522	0	0
T2	45248	1323	0	0
T3	38132304	821956	0	0
T4	4130112	81410	0	0
T5	11563720	280964	0	0
T9	14178808	261629	0	0
T14	2815904	73459	0	0
T15	194096	7568	0	0
T16	9615592	209955	0	0
T17	6527976	195208	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	345296	341208	0	0
T2	45248	44408	0	0
T3	38132304	38127656	0	0
T4	4130112	4129328	0	0
T5	11563720	11559968	0	0
T9	14178808	14070000	0	0
T14	2815904	2812208	0	0
T15	194096	191016	0	0
T16	9615592	9612904	0	0
T17	6527976	6527472	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	345296	341208	0	0
T2	45248	44408	0	0
T3	38132304	38127656	0	0
T4	4130112	4129328	0	0
T5	11563720	11559968	0	0
T9	14178808	14070000	0	0
T14	2815904	2812208	0	0
T15	194096	191016	0	0
T16	9615592	9612904	0	0
T17	6527976	6527472	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	345296	341208	0	0
T2	45248	44408	0	0
T3	38132304	38127656	0	0
T4	4130112	4129328	0	0
T5	11563720	11559968	0	0
T9	14178808	14070000	0	0
T14	2815904	2812208	0	0
T15	194096	191016	0	0
T16	9615592	9612904	0	0
T17	6527976	6527472	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T9	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	122407487	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	122407487	0	0
T1	6166	5650	0	0
T2	808	654	0	0
T3	680934	303412	0	0
T4	73752	35853	0	0
T5	206495	134944	0	0
T9	253193	110225	0	0
T14	50284	31506	0	0
T15	3466	2942	0	0
T16	171707	98793	0	0
T17	116571	114687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	89560318	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	89560318	0	0
T1	6166	2958	0	0
T2	808	335	0	0
T3	680934	179216	0	0
T4	73752	10761	0	0
T5	206495	48801	0	0
T9	253193	38569	0	0
T14	50284	14107	0	0
T15	3466	1542	0	0
T16	171707	32513	0	0
T17	116571	39973	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1547078	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1547078	0	0
T1	6166	99	0	0
T2	808	1	0	0
T3	680934	3364	0	0
T4	73752	807	0	0
T5	206495	1238	0	0
T9	253193	3475	0	0
T14	50284	671	0	0
T15	3466	53	0	0
T16	171707	651	0	0
T17	116571	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	4198869	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	4198869	0	0
T1	6166	99	0	0
T2	808	1	0	0
T3	680934	3660	0	0
T4	73752	358	0	0
T5	206495	2158	0	0
T9	253193	1670	0	0
T14	50284	607	0	0
T15	3466	53	0	0
T16	171707	315	0	0
T17	116571	1635	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1534562	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1534562	0	0
T1	6166	97	0	0
T2	808	7	0	0
T3	680934	8643	0	0
T4	73752	948	0	0
T5	206495	2233	0	0
T9	253193	1499	0	0
T14	50284	585	0	0
T15	3466	53	0	0
T16	171707	724	0	0
T17	116571	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3019317	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3019317	0	0
T1	6166	97	0	0
T2	808	7	0	0
T3	680934	8936	0	0
T4	73752	383	0	0
T5	206495	1879	0	0
T9	253193	710	0	0
T14	50284	559	0	0
T15	3466	53	0	0
T16	171707	455	0	0
T17	116571	1477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1540619	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1540619	0	0
T1	6166	103	0	0
T2	808	6	0	0
T3	680934	8423	0	0
T4	73752	972	0	0
T5	206495	2043	0	0
T9	253193	4942	0	0
T14	50284	561	0	0
T15	3466	59	0	0
T16	171707	2246	0	0
T17	116571	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3085304	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3085304	0	0
T1	6166	103	0	0
T2	808	6	0	0
T3	680934	8207	0	0
T4	73752	425	0	0
T5	206495	1849	0	0
T9	253193	2856	0	0
T14	50284	540	0	0
T15	3466	59	0	0
T16	171707	1135	0	0
T17	116571	1683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1473835	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1473835	0	0
T1	6166	112	0	0
T2	808	6	0	0
T3	680934	4418	0	0
T4	73752	737	0	0
T5	206495	2022	0	0
T9	253193	3142	0	0
T14	50284	479	0	0
T15	3466	55	0	0
T16	171707	759	0	0
T17	116571	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3373591	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3373591	0	0
T1	6166	112	0	0
T2	808	6	0	0
T3	680934	4270	0	0
T4	73752	309	0	0
T5	206495	3465	0	0
T9	253193	1510	0	0
T14	50284	487	0	0
T15	3466	55	0	0
T16	171707	379	0	0
T17	116571	545	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1456317	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1456317	0	0
T1	6166	128	0	0
T2	808	11	0	0
T3	680934	3636	0	0
T4	73752	891	0	0
T5	206495	394	0	0
T9	253193	1387	0	0
T14	50284	541	0	0
T15	3466	63	0	0
T16	171707	1785	0	0
T17	116571	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3496934	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3496934	0	0
T1	6166	128	0	0
T2	808	11	0	0
T3	680934	3661	0	0
T4	73752	370	0	0
T5	206495	570	0	0
T9	253193	649	0	0
T14	50284	425	0	0
T15	3466	63	0	0
T16	171707	383	0	0
T17	116571	1659	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1470720	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1470720	0	0
T1	6166	88	0	0
T2	808	7	0	0
T3	680934	5949	0	0
T4	73752	672	0	0
T5	206495	1599	0	0
T9	253193	1580	0	0
T14	50284	549	0	0
T15	3466	64	0	0
T16	171707	1447	0	0
T17	116571	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2769731	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2769731	0	0
T1	6166	88	0	0
T2	808	7	0	0
T3	680934	5856	0	0
T4	73752	364	0	0
T5	206495	1195	0	0
T9	253193	663	0	0
T14	50284	577	0	0
T15	3466	64	0	0
T16	171707	754	0	0
T17	116571	2074	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1559993	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1559993	0	0
T1	6166	103	0	0
T2	808	6	0	0
T3	680934	7379	0	0
T4	73752	843	0	0
T5	206495	3757	0	0
T9	253193	1769	0	0
T14	50284	470	0	0
T15	3466	59	0	0
T16	171707	1542	0	0
T17	116571	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3788434	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3788434	0	0
T1	6166	103	0	0
T2	808	6	0	0
T3	680934	8445	0	0
T4	73752	298	0	0
T5	206495	3421	0	0
T9	253193	890	0	0
T14	50284	498	0	0
T15	3466	59	0	0
T16	171707	1199	0	0
T17	116571	2519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1457078	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1457078	0	0
T1	6166	117	0	0
T2	808	4	0	0
T3	680934	4175	0	0
T4	73752	921	0	0
T5	206495	1836	0	0
T9	253193	2856	0	0
T14	50284	430	0	0
T15	3466	57	0	0
T16	171707	3907	0	0
T17	116571	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3174861	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3174861	0	0
T1	6166	117	0	0
T2	808	4	0	0
T3	680934	4074	0	0
T4	73752	399	0	0
T5	206495	701	0	0
T9	253193	1574	0	0
T14	50284	441	0	0
T15	3466	57	0	0
T16	171707	3584	0	0
T17	116571	442	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1517487	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1517487	0	0
T1	6166	124	0	0
T2	808	8	0	0
T3	680934	5791	0	0
T4	73752	929	0	0
T5	206495	805	0	0
T9	253193	1455	0	0
T14	50284	590	0	0
T15	3466	51	0	0
T16	171707	1901	0	0
T17	116571	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3076260	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3076260	0	0
T1	6166	124	0	0
T2	808	8	0	0
T3	680934	5944	0	0
T4	73752	491	0	0
T5	206495	1407	0	0
T9	253193	702	0	0
T14	50284	637	0	0
T15	3466	51	0	0
T16	171707	2155	0	0
T17	116571	2017	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1469268	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1469268	0	0
T1	6166	104	0	0
T2	808	6	0	0
T3	680934	5529	0	0
T4	73752	815	0	0
T5	206495	946	0	0
T9	253193	1603	0	0
T14	50284	509	0	0
T15	3466	53	0	0
T16	171707	2400	0	0
T17	116571	19	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3440688	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3440688	0	0
T1	6166	104	0	0
T2	808	6	0	0
T3	680934	5253	0	0
T4	73752	386	0	0
T5	206495	2619	0	0
T9	253193	643	0	0
T14	50284	547	0	0
T15	3466	53	0	0
T16	171707	1432	0	0
T17	116571	2485	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1434386	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1434386	0	0
T1	6166	109	0	0
T2	808	5	0	0
T3	680934	6475	0	0
T4	73752	1065	0	0
T5	206495	1069	0	0
T9	253193	2247	0	0
T14	50284	475	0	0
T15	3466	56	0	0
T16	171707	2109	0	0
T17	116571	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2856878	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2856878	0	0
T1	6166	109	0	0
T2	808	5	0	0
T3	680934	6248	0	0
T4	73752	530	0	0
T5	206495	1066	0	0
T9	253193	984	0	0
T14	50284	541	0	0
T15	3466	56	0	0
T16	171707	2128	0	0
T17	116571	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1453056	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1453056	0	0
T1	6166	104	0	0
T2	808	9	0	0
T3	680934	8372	0	0
T4	73752	949	0	0
T5	206495	952	0	0
T9	253193	3312	0	0
T14	50284	547	0	0
T15	3466	53	0	0
T16	171707	304	0	0
T17	116571	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3273191	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3273191	0	0
T1	6166	104	0	0
T2	808	9	0	0
T3	680934	8162	0	0
T4	73752	415	0	0
T5	206495	536	0	0
T9	253193	1403	0	0
T14	50284	556	0	0
T15	3466	53	0	0
T16	171707	169	0	0
T17	116571	622	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1506655	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1506655	0	0
T1	6166	100	0	0
T2	808	5	0	0
T3	680934	10238	0	0
T4	73752	797	0	0
T5	206495	1819	0	0
T9	253193	1564	0	0
T14	50284	380	0	0
T15	3466	44	0	0
T16	171707	1523	0	0
T17	116571	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2919490	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2919490	0	0
T1	6166	100	0	0
T2	808	5	0	0
T3	680934	9617	0	0
T4	73752	364	0	0
T5	206495	853	0	0
T9	253193	661	0	0
T14	50284	405	0	0
T15	3466	44	0	0
T16	171707	2148	0	0
T17	116571	2242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1526470	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1526470	0	0
T1	6166	111	0	0
T2	808	10	0	0
T3	680934	8708	0	0
T4	73752	825	0	0
T5	206495	2191	0	0
T9	253193	1455	0	0
T14	50284	471	0	0
T15	3466	43	0	0
T16	171707	2496	0	0
T17	116571	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3931362	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3931362	0	0
T1	6166	111	0	0
T2	808	10	0	0
T3	680934	9389	0	0
T4	73752	414	0	0
T5	206495	4132	0	0
T9	253193	733	0	0
T14	50284	575	0	0
T15	3466	43	0	0
T16	171707	879	0	0
T17	116571	464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1524407	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1524407	0	0
T1	6166	116	0	0
T2	808	11	0	0
T3	680934	5472	0	0
T4	73752	813	0	0
T5	206495	1508	0	0
T9	253193	4970	0	0
T14	50284	515	0	0
T15	3466	58	0	0
T16	171707	1291	0	0
T17	116571	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2994956	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2994956	0	0
T1	6166	116	0	0
T2	808	11	0	0
T3	680934	5759	0	0
T4	73752	321	0	0
T5	206495	1115	0	0
T9	253193	2731	0	0
T14	50284	478	0	0
T15	3466	58	0	0
T16	171707	1157	0	0
T17	116571	1498	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1538720	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1538720	0	0
T1	6166	94	0	0
T2	808	6	0	0
T3	680934	5934	0	0
T4	73752	995	0	0
T5	206495	1770	0	0
T9	253193	2275	0	0
T14	50284	534	0	0
T15	3466	57	0	0
T16	171707	2244	0	0
T17	116571	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3098265	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3098265	0	0
T1	6166	94	0	0
T2	808	6	0	0
T3	680934	6133	0	0
T4	73752	422	0	0
T5	206495	1758	0	0
T9	253193	929	0	0
T14	50284	605	0	0
T15	3466	57	0	0
T16	171707	1051	0	0
T17	116571	2122	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1466421	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1466421	0	0
T1	6166	121	0	0
T2	808	2	0	0
T3	680934	7197	0	0
T4	73752	776	0	0
T5	206495	716	0	0
T9	253193	1589	0	0
T14	50284	532	0	0
T15	3466	55	0	0
T16	171707	1666	0	0
T17	116571	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2626745	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2626745	0	0
T1	6166	121	0	0
T2	808	2	0	0
T3	680934	7363	0	0
T4	73752	411	0	0
T5	206495	1646	0	0
T9	253193	668	0	0
T14	50284	491	0	0
T15	3466	55	0	0
T16	171707	1113	0	0
T17	116571	3219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1487563	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1487563	0	0
T1	6166	125	0	0
T2	808	9	0	0
T3	680934	4128	0	0
T4	73752	925	0	0
T5	206495	2290	0	0
T9	253193	5180	0	0
T14	50284	461	0	0
T15	3466	58	0	0
T16	171707	2629	0	0
T17	116571	36	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3186872	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3186872	0	0
T1	6166	125	0	0
T2	808	9	0	0
T3	680934	4071	0	0
T4	73752	446	0	0
T5	206495	2287	0	0
T9	253193	3044	0	0
T14	50284	481	0	0
T15	3466	58	0	0
T16	171707	2384	0	0
T17	116571	1937	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1493715	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1493715	0	0
T1	6166	113	0	0
T2	808	8	0	0
T3	680934	10767	0	0
T4	73752	1064	0	0
T5	206495	5055	0	0
T9	253193	4620	0	0
T14	50284	501	0	0
T15	3466	53	0	0
T16	171707	1720	0	0
T17	116571	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3505470	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3505470	0	0
T1	6166	113	0	0
T2	808	8	0	0
T3	680934	10370	0	0
T4	73752	532	0	0
T5	206495	4548	0	0
T9	253193	2556	0	0
T14	50284	470	0	0
T15	3466	53	0	0
T16	171707	477	0	0
T17	116571	1844	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1453541	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1453541	0	0
T1	6166	128	0	0
T2	808	6	0	0
T3	680934	7395	0	0
T4	73752	840	0	0
T5	206495	794	0	0
T9	253193	1591	0	0
T14	50284	452	0	0
T15	3466	50	0	0
T16	171707	1571	0	0
T17	116571	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	2797560	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	2797560	0	0
T1	6166	128	0	0
T2	808	6	0	0
T3	680934	7814	0	0
T4	73752	424	0	0
T5	206495	813	0	0
T9	253193	687	0	0
T14	50284	497	0	0
T15	3466	50	0	0
T16	171707	1063	0	0
T17	116571	932	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1411685	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1411685	0	0
T1	6166	96	0	0
T2	808	5	0	0
T3	680934	4076	0	0
T4	73752	793	0	0
T5	206495	2754	0	0
T9	253193	5278	0	0
T14	50284	512	0	0
T15	3466	63	0	0
T16	171707	842	0	0
T17	116571	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3135928	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3135928	0	0
T1	6166	96	0	0
T2	808	5	0	0
T3	680934	3748	0	0
T4	73752	271	0	0
T5	206495	1595	0	0
T9	253193	2372	0	0
T14	50284	480	0	0
T15	3466	63	0	0
T16	171707	500	0	0
T17	116571	847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1510206	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1510206	0	0
T1	6166	109	0	0
T2	808	2	0	0
T3	680934	4370	0	0
T4	73752	846	0	0
T5	206495	852	0	0
T9	253193	3278	0	0
T14	50284	524	0	0
T15	3466	73	0	0
T16	171707	1035	0	0
T17	116571	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	4190964	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	4190964	0	0
T1	6166	109	0	0
T2	808	2	0	0
T3	680934	4345	0	0
T4	73752	337	0	0
T5	206495	608	0	0
T9	253193	1366	0	0
T14	50284	592	0	0
T15	3466	73	0	0
T16	171707	1518	0	0
T17	116571	1290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1485190	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1485190	0	0
T1	6166	116	0	0
T2	808	2	0	0
T3	680934	4078	0	0
T4	73752	1067	0	0
T5	206495	2257	0	0
T9	253193	1996	0	0
T14	50284	539	0	0
T15	3466	79	0	0
T16	171707	3024	0	0
T17	116571	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3294274	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3294274	0	0
T1	6166	116	0	0
T2	808	2	0	0
T3	680934	3902	0	0
T4	73752	445	0	0
T5	206495	1611	0	0
T9	253193	847	0	0
T14	50284	599	0	0
T15	3466	79	0	0
T16	171707	3319	0	0
T17	116571	1491	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1510117	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1510117	0	0
T1	6166	107	0	0
T2	808	2	0	0
T3	680934	4527	0	0
T4	73752	991	0	0
T5	206495	721	0	0
T9	253193	3925	0	0
T14	50284	517	0	0
T15	3466	57	0	0
T16	171707	1255	0	0
T17	116571	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3451907	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3451907	0	0
T1	6166	107	0	0
T2	808	2	0	0
T3	680934	4138	0	0
T4	73752	397	0	0
T5	206495	339	0	0
T9	253193	2167	0	0
T14	50284	539	0	0
T15	3466	57	0	0
T16	171707	55	0	0
T17	116571	1459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1470054	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1470054	0	0
T1	6166	110	0	0
T2	808	9	0	0
T3	680934	6268	0	0
T4	73752	998	0	0
T5	206495	2694	0	0
T9	253193	2331	0	0
T14	50284	405	0	0
T15	3466	62	0	0
T16	171707	910	0	0
T17	116571	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3354942	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3354942	0	0
T1	6166	110	0	0
T2	808	9	0	0
T3	680934	6527	0	0
T4	73752	412	0	0
T5	206495	858	0	0
T9	253193	1150	0	0
T14	50284	399	0	0
T15	3466	62	0	0
T16	171707	146	0	0
T17	116571	283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1504845	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1504845	0	0
T1	6166	93	0	0
T2	808	6	0	0
T3	680934	8279	0	0
T4	73752	902	0	0
T5	206495	1652	0	0
T9	253193	1396	0	0
T14	50284	564	0	0
T15	3466	56	0	0
T16	171707	1733	0	0
T17	116571	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3404674	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3404674	0	0
T1	6166	93	0	0
T2	808	6	0	0
T3	680934	7887	0	0
T4	73752	359	0	0
T5	206495	2183	0	0
T9	253193	575	0	0
T14	50284	634	0	0
T15	3466	56	0	0
T16	171707	1754	0	0
T17	116571	1796	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	1517260	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	1517260	0	0
T1	6166	130	0	0
T2	808	8	0	0
T3	680934	6087	0	0
T4	73752	855	0	0
T5	206495	2451	0	0
T9	253193	4830	0	0
T14	50284	425	0	0
T15	3466	58	0	0
T16	171707	2422	0	0
T17	116571	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315072753	3146650	0	0
DepthKnown_A	315072753	314946687	0	0
RvalidKnown_A	315072753	314946687	0	0
WreadyKnown_A	315072753	314946687	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	3146650	0	0
T1	6166	130	0	0
T2	808	8	0	0
T3	680934	5871	0	0
T4	73752	477	0	0
T5	206495	3589	0	0
T9	253193	2550	0	0
T14	50284	447	0	0
T15	3466	58	0	0
T16	171707	861	0	0
T17	116571	1320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315072753	314946687	0	0
T1	6166	6093	0	0
T2	808	793	0	0
T3	680934	680851	0	0
T4	73752	73738	0	0
T5	206495	206428	0	0
T9	253193	251250	0	0
T14	50284	50218	0	0
T15	3466	3411	0	0
T16	171707	171659	0	0
T17	116571	116562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0