Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1671594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262829

1

T1

21

T2

25

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	654886	1			T1	50		T2	61		T3	29
values[0x0]	623854	1			T1	50		T2	53		T3	3
values[0x1]	655683	1			T1	59		T2	79		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1295423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639000

1

T1

46

T2

64

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7824	1			T17	78		T14	1		T15	6
valid_sources[0x01]	7729	1			T3	1		T17	37		T15	11
valid_sources[0x02]	7588	1			T17	19		T15	6		T16	5
valid_sources[0x03]	7549	1			T3	1		T17	4		T15	11
valid_sources[0x04]	7777	1			T2	1		T17	58		T14	1
valid_sources[0x05]	8969	1			T1	8		T2	3		T17	42
valid_sources[0x06]	7194	1			T17	26		T14	4		T15	8
valid_sources[0x07]	7302	1			T17	99		T14	2		T15	7
valid_sources[0x08]	7566	1			T2	6		T17	22		T15	18
valid_sources[0x09]	8421	1			T2	2		T17	41		T14	2
valid_sources[0x0a]	7259	1			T17	35		T15	6		T16	6
valid_sources[0x0b]	6274	1			T17	11		T14	1		T15	13
valid_sources[0x0c]	7678	1			T17	83		T14	1		T15	13
valid_sources[0x0d]	6621	1			T17	57		T14	1		T15	11
valid_sources[0x0e]	8141	1			T1	1		T2	2		T3	1
valid_sources[0x0f]	8686	1			T3	1		T17	47		T15	8
valid_sources[0x10]	7524	1			T17	13		T15	4		T16	5
valid_sources[0x11]	7316	1			T17	86		T15	11		T16	6
valid_sources[0x12]	8465	1			T3	1		T17	96		T15	15
valid_sources[0x13]	7627	1			T17	77		T15	14		T16	6
valid_sources[0x14]	7318	1			T3	1		T17	62		T14	1
valid_sources[0x15]	7265	1			T17	66		T14	3		T15	6
valid_sources[0x16]	7356	1			T17	21		T14	1		T15	10
valid_sources[0x17]	7511	1			T17	58		T15	9		T16	7
valid_sources[0x18]	6933	1			T17	41		T15	8		T16	6
valid_sources[0x19]	7305	1			T17	45		T15	17		T16	7
valid_sources[0x1a]	7426	1			T1	18		T17	58		T15	10
valid_sources[0x1b]	7921	1			T17	26		T15	9		T16	7
valid_sources[0x1c]	7191	1			T1	2		T2	3		T17	44
valid_sources[0x1d]	7105	1			T17	83		T15	13		T16	6
valid_sources[0x1e]	6737	1			T2	2		T17	43		T15	8
valid_sources[0x1f]	7440	1			T17	69		T14	2		T15	16
valid_sources[0x20]	7956	1			T17	10		T15	7		T16	6
valid_sources[0x21]	7652	1			T17	6		T14	1		T15	10
valid_sources[0x22]	6728	1			T2	1		T17	15		T14	1
valid_sources[0x23]	8213	1			T17	75		T15	4		T16	6
valid_sources[0x24]	6952	1			T3	2		T17	76		T15	12
valid_sources[0x25]	7520	1			T17	39		T15	7		T16	5
valid_sources[0x26]	7286	1			T3	1		T17	44		T15	13
valid_sources[0x27]	7310	1			T17	51		T14	3		T15	4
valid_sources[0x28]	7813	1			T3	1		T17	75		T15	15
valid_sources[0x29]	7847	1			T17	115		T15	9		T16	6
valid_sources[0x2a]	6536	1			T17	55		T15	13		T16	7
valid_sources[0x2b]	7075	1			T17	24		T15	8		T16	7
valid_sources[0x2c]	6818	1			T2	5		T17	13		T15	7
valid_sources[0x2d]	7321	1			T3	1		T17	52		T14	3
valid_sources[0x2e]	7862	1			T2	2		T17	32		T14	2
valid_sources[0x2f]	7135	1			T17	43		T14	2		T15	14
valid_sources[0x30]	7243	1			T17	73		T15	5		T16	5
valid_sources[0x31]	7807	1			T2	2		T17	61		T14	1
valid_sources[0x32]	7903	1			T17	16		T14	1		T15	8
valid_sources[0x33]	7521	1			T17	15		T14	1		T15	11
valid_sources[0x34]	7270	1			T2	1		T17	142		T15	8
valid_sources[0x35]	7955	1			T17	67		T14	4		T15	12
valid_sources[0x36]	7467	1			T17	35		T14	1		T15	9
valid_sources[0x37]	6894	1			T17	36		T15	13		T16	5
valid_sources[0x38]	9183	1			T17	75		T14	4		T15	16
valid_sources[0x39]	7110	1			T17	22		T15	9		T16	5
valid_sources[0x3a]	9038	1			T3	1		T17	55		T14	5
valid_sources[0x3b]	7119	1			T17	25		T15	6		T16	7
valid_sources[0x3c]	7599	1			T17	26		T14	2		T15	10
valid_sources[0x3d]	7407	1			T17	134		T14	2		T15	9
valid_sources[0x3e]	8042	1			T17	16		T14	3		T15	13
valid_sources[0x3f]	8012	1			T1	1		T2	1		T3	1
valid_sources[0x40]	6968	1			T17	80		T15	8		T16	4
valid_sources[0x41]	7503	1			T17	33		T15	12		T16	7
valid_sources[0x42]	6656	1			T3	2		T17	9		T15	8
valid_sources[0x43]	8185	1			T17	55		T15	11		T16	6
valid_sources[0x44]	7750	1			T17	46		T15	21		T16	7
valid_sources[0x45]	7587	1			T3	1		T17	18		T14	1
valid_sources[0x46]	6696	1			T17	26		T15	14		T16	6
valid_sources[0x47]	8673	1			T2	4		T17	56		T14	1
valid_sources[0x48]	7610	1			T17	129		T15	10		T16	5
valid_sources[0x49]	7644	1			T2	2		T17	69		T14	1
valid_sources[0x4a]	6840	1			T2	1		T17	81		T15	4
valid_sources[0x4b]	7556	1			T2	1		T17	95		T15	9
valid_sources[0x4c]	7322	1			T17	140		T15	12		T16	7
valid_sources[0x4d]	7712	1			T17	48		T14	1		T15	9
valid_sources[0x4e]	7485	1			T17	88		T14	1		T15	7
valid_sources[0x4f]	6670	1			T2	1		T17	32		T14	2
valid_sources[0x50]	7462	1			T17	31		T15	14		T16	4
valid_sources[0x51]	8153	1			T17	17		T14	2		T15	11
valid_sources[0x52]	7064	1			T17	26		T15	15		T16	6
valid_sources[0x53]	7702	1			T2	1		T17	17		T14	1
valid_sources[0x54]	8653	1			T3	1		T17	10		T15	8
valid_sources[0x55]	7073	1			T2	7		T17	5		T15	6
valid_sources[0x56]	8137	1			T1	4		T2	1		T17	12
valid_sources[0x57]	7622	1			T17	43		T14	1		T15	10
valid_sources[0x58]	7139	1			T17	62		T15	11		T16	4
valid_sources[0x59]	7046	1			T17	39		T14	2		T15	9
valid_sources[0x5a]	8033	1			T2	1		T17	91		T14	1
valid_sources[0x5b]	7424	1			T2	4		T17	19		T15	12
valid_sources[0x5c]	7140	1			T1	9		T17	11		T15	4
valid_sources[0x5d]	8293	1			T17	20		T14	3		T15	5
valid_sources[0x5e]	6997	1			T1	21		T17	35		T14	1
valid_sources[0x5f]	7308	1			T3	1		T17	40		T15	6
valid_sources[0x60]	7511	1			T2	4		T3	2		T17	79
valid_sources[0x61]	7321	1			T17	93		T15	16		T16	6
valid_sources[0x62]	7011	1			T1	7		T2	1		T17	26
valid_sources[0x63]	7541	1			T17	15		T15	14		T16	7
valid_sources[0x64]	6735	1			T3	1		T17	6		T15	6
valid_sources[0x65]	7959	1			T17	18		T14	3		T15	9
valid_sources[0x66]	7566	1			T17	45		T15	10		T16	5
valid_sources[0x67]	7038	1			T17	54		T15	12		T16	7
valid_sources[0x68]	9040	1			T1	3		T2	3		T17	15
valid_sources[0x69]	7808	1			T2	3		T3	1		T17	17
valid_sources[0x6a]	8164	1			T2	5		T17	47		T14	2
valid_sources[0x6b]	7242	1			T17	53		T15	12		T16	6
valid_sources[0x6c]	8501	1			T17	9		T14	1		T15	8
valid_sources[0x6d]	7302	1			T3	1		T17	52		T15	11
valid_sources[0x6e]	7149	1			T17	25		T14	2		T15	6
valid_sources[0x6f]	7900	1			T2	1		T17	90		T14	3
valid_sources[0x70]	7034	1			T17	69		T14	1		T15	7
valid_sources[0x71]	8420	1			T17	60		T14	1		T15	7
valid_sources[0x72]	7732	1			T1	15		T3	2		T17	65
valid_sources[0x73]	8493	1			T2	2		T17	59		T15	7
valid_sources[0x74]	7193	1			T17	24		T15	16		T16	9
valid_sources[0x75]	8557	1			T2	1		T17	38		T15	7
valid_sources[0x76]	7878	1			T1	8		T17	72		T15	10
valid_sources[0x77]	9476	1			T17	77		T15	8		T16	7
valid_sources[0x78]	10643	1			T17	209		T15	12		T16	6
valid_sources[0x79]	7149	1			T17	19		T15	12		T16	6
valid_sources[0x7a]	7461	1			T17	12		T15	11		T16	5
valid_sources[0x7b]	7628	1			T17	143		T15	12		T16	6
valid_sources[0x7c]	7237	1			T17	47		T14	2		T15	10
valid_sources[0x7d]	8036	1			T17	7		T14	1		T15	9
valid_sources[0x7e]	7190	1			T2	2		T17	15		T15	11
valid_sources[0x7f]	7353	1			T3	1		T17	81		T14	1
valid_sources[0x80]	6633	1			T17	9		T15	8		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27781

1

T1

1

T2

2

T3

3

values[0x0]

all_enables

biggest_size

207442

1

T1

16

T2

20

T3

2

values[0x1]

all_enables

biggest_size

27606

1

T1

4

T2

3

T3

4