Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	357758857	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357758857	0	0
T1	4391128	77376	0	0
T2	280224	5475	0	0
T3	1980160	42051	0	0
T14	14132832	332133	0	0
T15	4148760	91130	0	0
T16	8349544	1102862	0	0
T17	20518288	410754	0	0
T18	0	3037	0	0
T19	24662288	1869577	0	0
T20	34048	916	0	0
T21	44464	925	0	0
T22	0	212	0	0
T23	0	1258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4391128	4387992	0	0
T2	280224	277032	0	0
T3	1980160	1977752	0	0
T14	14132832	14131768	0	0
T15	4148760	4148256	0	0
T16	8349544	8349488	0	0
T17	20518288	20509104	0	0
T19	24662288	24662232	0	0
T20	34048	32592	0	0
T21	44464	42112	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4391128	4387992	0	0
T2	280224	277032	0	0
T3	1980160	1977752	0	0
T14	14132832	14131768	0	0
T15	4148760	4148256	0	0
T16	8349544	8349488	0	0
T17	20518288	20509104	0	0
T19	24662288	24662232	0	0
T20	34048	32592	0	0
T21	44464	42112	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4391128	4387992	0	0
T2	280224	277032	0	0
T3	1980160	1977752	0	0
T14	14132832	14131768	0	0
T15	4148760	4148256	0	0
T16	8349544	8349488	0	0
T17	20518288	20509104	0	0
T19	24662288	24662232	0	0
T20	34048	32592	0	0
T21	44464	42112	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	129656384	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	129656384	0	0
T1	78413	75676	0	0
T2	5004	2405	0	0
T3	35360	15828	0	0
T14	252372	148672	0	0
T15	74085	38264	0	0
T16	149099	7186	0	0
T17	366398	148003	0	0
T19	440398	20870	0	0
T20	608	355	0	0
T21	794	361	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	94343094	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	94343094	0	0
T1	78413	470	0	0
T2	5004	753	0	0
T3	35360	13650	0	0
T14	252372	59329	0	0
T15	74085	16269	0	0
T16	149099	544245	0	0
T17	366398	95494	0	0
T19	440398	166167	0	0
T20	608	187	0	0
T21	794	188	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1484848	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1484848	0	0
T1	78413	19	0	0
T2	5004	40	0	0
T3	35360	129	0	0
T14	252372	2307	0	0
T15	74085	873	0	0
T16	149099	0	0	0
T17	366398	2967	0	0
T19	440398	3241	0	0
T20	608	6	0	0
T21	794	3	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3642096	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3642096	0	0
T1	78413	8	0	0
T2	5004	17	0	0
T3	35360	139	0	0
T14	252372	2383	0	0
T15	74085	688	0	0
T16	149099	0	0	0
T17	366398	2761	0	0
T19	440398	258940	0	0
T20	608	6	0	0
T21	794	3	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1502076	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1502076	0	0
T1	78413	22	0	0
T2	5004	71	0	0
T3	35360	236	0	0
T14	252372	1796	0	0
T15	74085	778	0	0
T16	149099	0	0	0
T17	366398	2920	0	0
T19	440398	1344	0	0
T20	608	5	0	0
T21	794	5	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3396550	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3396550	0	0
T1	78413	4	0	0
T2	5004	22	0	0
T3	35360	210	0	0
T14	252372	1706	0	0
T15	74085	610	0	0
T16	149099	0	0	0
T17	366398	2512	0	0
T19	440398	116375	0	0
T20	608	5	0	0
T21	794	5	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1482080	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1482080	0	0
T1	78413	35	0	0
T2	5004	55	0	0
T3	35360	298	0	0
T14	252372	2830	0	0
T15	74085	591	0	0
T16	149099	0	0	0
T17	366398	2820	0	0
T18	0	238	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	15	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3461015	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3461015	0	0
T1	78413	6	0	0
T2	5004	11	0	0
T3	35360	266	0	0
T14	252372	2077	0	0
T15	74085	595	0	0
T16	149099	0	0	0
T17	366398	2537	0	0
T18	0	148	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	15	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1483048	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1483048	0	0
T1	78413	24	0	0
T2	5004	75	0	0
T3	35360	195	0	0
T14	252372	1550	0	0
T15	74085	769	0	0
T16	149099	0	0	0
T17	366398	2374	0	0
T19	440398	1303	0	0
T20	608	12	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2722213	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2722213	0	0
T1	78413	4	0	0
T2	5004	40	0	0
T3	35360	169	0	0
T14	252372	666	0	0
T15	74085	680	0	0
T16	149099	0	0	0
T17	366398	2190	0	0
T19	440398	103978	0	0
T20	608	12	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1510364	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1510364	0	0
T1	78413	18	0	0
T2	5004	38	0	0
T3	35360	281	0	0
T14	252372	1055	0	0
T15	74085	892	0	0
T16	149099	0	0	0
T17	366398	4498	0	0
T18	0	63	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	5	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3706545	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3706545	0	0
T1	78413	4	0	0
T2	5004	30	0	0
T3	35360	241	0	0
T14	252372	785	0	0
T15	74085	644	0	0
T16	149099	0	0	0
T17	366398	4011	0	0
T18	0	51	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	5	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1463935	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1463935	0	0
T1	78413	25	0	0
T2	5004	27	0	0
T3	35360	242	0	0
T14	252372	4210	0	0
T15	74085	979	0	0
T16	149099	1428	0	0
T17	366398	2731	0	0
T19	440398	2464	0	0
T20	608	4	0	0
T21	794	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3953221	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3953221	0	0
T1	78413	6	0	0
T2	5004	25	0	0
T3	35360	266	0	0
T14	252372	3071	0	0
T15	74085	713	0	0
T16	149099	105241	0	0
T17	366398	2817	0	0
T19	440398	200810	0	0
T20	608	4	0	0
T21	794	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1501050	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1501050	0	0
T1	78413	31	0	0
T2	5004	47	0	0
T3	35360	203	0	0
T14	252372	1161	0	0
T15	74085	756	0	0
T16	149099	0	0	0
T17	366398	2817	0	0
T18	0	136	0	0
T19	440398	0	0	0
T20	608	4	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3464701	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3464701	0	0
T1	78413	6	0	0
T2	5004	11	0	0
T3	35360	203	0	0
T14	252372	1583	0	0
T15	74085	580	0	0
T16	149099	0	0	0
T17	366398	2571	0	0
T18	0	148	0	0
T19	440398	0	0	0
T20	608	4	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1506052	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1506052	0	0
T1	78413	23	0	0
T2	5004	77	0	0
T3	35360	273	0	0
T14	252372	3160	0	0
T15	74085	874	0	0
T16	149099	1373	0	0
T17	366398	2804	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	4	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3968040	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3968040	0	0
T1	78413	4	0	0
T2	5004	41	0	0
T3	35360	303	0	0
T14	252372	3877	0	0
T15	74085	638	0	0
T16	149099	95874	0	0
T17	366398	2644	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	4	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1514559	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1514559	0	0
T1	78413	30	0	0
T2	5004	39	0	0
T3	35360	326	0	0
T14	252372	1586	0	0
T15	74085	911	0	0
T16	149099	1088	0	0
T17	366398	4113	0	0
T19	440398	1309	0	0
T20	608	7	0	0
T21	794	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3760493	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3760493	0	0
T1	78413	8	0	0
T2	5004	22	0	0
T3	35360	299	0	0
T14	252372	1281	0	0
T15	74085	674	0	0
T16	149099	78938	0	0
T17	366398	4216	0	0
T19	440398	103123	0	0
T20	608	7	0	0
T21	794	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1503350	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1503350	0	0
T1	78413	17	0	0
T2	5004	90	0	0
T3	35360	186	0	0
T14	252372	2058	0	0
T15	74085	659	0	0
T16	149099	0	0	0
T17	366398	2997	0	0
T18	0	134	0	0
T19	440398	0	0	0
T20	608	12	0	0
T21	794	8	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3234063	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3234063	0	0
T1	78413	5	0	0
T2	5004	23	0	0
T3	35360	163	0	0
T14	252372	1132	0	0
T15	74085	455	0	0
T16	149099	0	0	0
T17	366398	2793	0	0
T18	0	143	0	0
T19	440398	0	0	0
T20	608	12	0	0
T21	794	8	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1478374	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1478374	0	0
T1	78413	14	0	0
T2	5004	42	0	0
T3	35360	209	0	0
T14	252372	1591	0	0
T15	74085	736	0	0
T16	149099	0	0	0
T17	366398	4582	0	0
T18	0	136	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	2	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3581143	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3581143	0	0
T1	78413	5	0	0
T2	5004	18	0	0
T3	35360	255	0	0
T14	252372	1719	0	0
T15	74085	665	0	0
T16	149099	0	0	0
T17	366398	4449	0	0
T18	0	108	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	2	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1440317	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1440317	0	0
T1	78413	25	0	0
T2	5004	54	0	0
T3	35360	319	0	0
T14	252372	2235	0	0
T15	74085	648	0	0
T16	149099	0	0	0
T17	366398	6640	0	0
T18	0	34	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	7	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2957297	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2957297	0	0
T1	78413	6	0	0
T2	5004	29	0	0
T3	35360	275	0	0
T14	252372	3517	0	0
T15	74085	517	0	0
T16	149099	0	0	0
T17	366398	6287	0	0
T18	0	68	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	7	0	0
T22	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1539980	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1539980	0	0
T1	78413	23	0	0
T2	5004	46	0	0
T3	35360	290	0	0
T14	252372	1417	0	0
T15	74085	896	0	0
T16	149099	0	0	0
T17	366398	2811	0	0
T18	0	152	0	0
T19	440398	0	0	0
T20	608	0	0	0
T21	794	11	0	0
T22	0	8	0	0
T23	0	477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2995535	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2995535	0	0
T1	78413	4	0	0
T2	5004	25	0	0
T3	35360	232	0	0
T14	252372	1899	0	0
T15	74085	685	0	0
T16	149099	0	0	0
T17	366398	2485	0	0
T18	0	206	0	0
T19	440398	0	0	0
T20	608	0	0	0
T21	794	11	0	0
T22	0	8	0	0
T23	0	781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1475184	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1475184	0	0
T1	78413	25	0	0
T2	5004	64	0	0
T3	35360	209	0	0
T14	252372	2447	0	0
T15	74085	654	0	0
T16	149099	1335	0	0
T17	366398	2435	0	0
T19	440398	0	0	0
T20	608	4	0	0
T21	794	16	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3453920	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3453920	0	0
T1	78413	5	0	0
T2	5004	22	0	0
T3	35360	208	0	0
T14	252372	1372	0	0
T15	74085	501	0	0
T16	149099	102108	0	0
T17	366398	2259	0	0
T19	440398	0	0	0
T20	608	4	0	0
T21	794	16	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1503506	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1503506	0	0
T1	78413	33	0	0
T2	5004	65	0	0
T3	35360	202	0	0
T14	252372	1514	0	0
T15	74085	621	0	0
T16	149099	0	0	0
T17	366398	2351	0	0
T19	440398	1340	0	0
T20	608	8	0	0
T21	794	13	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	4039807	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	4039807	0	0
T1	78413	8	0	0
T2	5004	42	0	0
T3	35360	190	0	0
T14	252372	2633	0	0
T15	74085	614	0	0
T16	149099	0	0	0
T17	366398	2189	0	0
T19	440398	103668	0	0
T20	608	8	0	0
T21	794	13	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1474973	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1474973	0	0
T1	78413	37	0	0
T2	5004	60	0	0
T3	35360	203	0	0
T14	252372	2353	0	0
T15	74085	687	0	0
T16	149099	0	0	0
T17	366398	2445	0	0
T19	440398	1455	0	0
T20	608	8	0	0
T21	794	8	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3818261	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3818261	0	0
T1	78413	11	0	0
T2	5004	36	0	0
T3	35360	208	0	0
T14	252372	3163	0	0
T15	74085	705	0	0
T16	149099	0	0	0
T17	366398	2485	0	0
T19	440398	111062	0	0
T20	608	8	0	0
T21	794	8	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1487246	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1487246	0	0
T1	78413	10	0	0
T2	5004	95	0	0
T3	35360	196	0	0
T14	252372	1680	0	0
T15	74085	660	0	0
T16	149099	0	0	0
T17	366398	4561	0	0
T19	440398	2343	0	0
T20	608	7	0	0
T21	794	5	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2907900	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2907900	0	0
T1	78413	2	0	0
T2	5004	54	0	0
T3	35360	196	0	0
T14	252372	1778	0	0
T15	74085	458	0	0
T16	149099	0	0	0
T17	366398	4322	0	0
T19	440398	180274	0	0
T20	608	7	0	0
T21	794	5	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1466390	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1466390	0	0
T1	78413	33	0	0
T2	5004	8	0	0
T3	35360	294	0	0
T14	252372	1690	0	0
T15	74085	723	0	0
T16	149099	0	0	0
T17	366398	2675	0	0
T18	0	92	0	0
T19	440398	0	0	0
T20	608	5	0	0
T21	794	4	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3428686	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3428686	0	0
T1	78413	9	0	0
T2	5004	14	0	0
T3	35360	275	0	0
T14	252372	2143	0	0
T15	74085	607	0	0
T16	149099	0	0	0
T17	366398	2745	0	0
T18	0	119	0	0
T19	440398	0	0	0
T20	608	5	0	0
T21	794	4	0	0
T22	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1492034	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1492034	0	0
T1	78413	21	0	0
T2	5004	41	0	0
T3	35360	272	0	0
T14	252372	5722	0	0
T15	74085	675	0	0
T16	149099	0	0	0
T17	366398	2382	0	0
T18	0	187	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	6	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3715918	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3715918	0	0
T1	78413	5	0	0
T2	5004	16	0	0
T3	35360	205	0	0
T14	252372	2889	0	0
T15	74085	639	0	0
T16	149099	0	0	0
T17	366398	2435	0	0
T18	0	111	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	6	0	0
T22	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1503560	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1503560	0	0
T1	78413	32	0	0
T2	5004	53	0	0
T3	35360	202	0	0
T14	252372	2639	0	0
T15	74085	770	0	0
T16	149099	970	0	0
T17	366398	2651	0	0
T19	440398	873	0	0
T20	608	9	0	0
T21	794	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	4555459	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	4555459	0	0
T1	78413	9	0	0
T2	5004	52	0	0
T3	35360	174	0	0
T14	252372	2124	0	0
T15	74085	548	0	0
T16	149099	84782	0	0
T17	366398	2407	0	0
T19	440398	71103	0	0
T20	608	9	0	0
T21	794	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1470726	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1470726	0	0
T1	78413	28	0	0
T2	5004	50	0	0
T3	35360	293	0	0
T14	252372	3268	0	0
T15	74085	694	0	0
T16	149099	0	0	0
T17	366398	2293	0	0
T18	0	140	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	3	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3324231	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3324231	0	0
T1	78413	6	0	0
T2	5004	36	0	0
T3	35360	301	0	0
T14	252372	2815	0	0
T15	74085	521	0	0
T16	149099	0	0	0
T17	366398	2242	0	0
T18	0	124	0	0
T19	440398	0	0	0
T20	608	6	0	0
T21	794	3	0	0
T22	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1508140	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1508140	0	0
T1	78413	40	0	0
T2	5004	78	0	0
T3	35360	302	0	0
T14	252372	2791	0	0
T15	74085	846	0	0
T16	149099	0	0	0
T17	366398	4461	0	0
T18	0	160	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	3	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3225381	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3225381	0	0
T1	78413	8	0	0
T2	5004	42	0	0
T3	35360	236	0	0
T14	252372	2869	0	0
T15	74085	631	0	0
T16	149099	0	0	0
T17	366398	4050	0	0
T18	0	118	0	0
T19	440398	0	0	0
T20	608	7	0	0
T21	794	3	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1517330	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1517330	0	0
T1	78413	22	0	0
T2	5004	70	0	0
T3	35360	194	0	0
T14	252372	916	0	0
T15	74085	796	0	0
T16	149099	0	0	0
T17	366398	4747	0	0
T18	0	105	0	0
T19	440398	0	0	0
T20	608	10	0	0
T21	794	9	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2566337	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2566337	0	0
T1	78413	6	0	0
T2	5004	29	0	0
T3	35360	214	0	0
T14	252372	1129	0	0
T15	74085	586	0	0
T16	149099	0	0	0
T17	366398	4708	0	0
T18	0	116	0	0
T19	440398	0	0	0
T20	608	10	0	0
T21	794	9	0	0
T22	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1460822	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1460822	0	0
T1	78413	65	0	0
T2	5004	79	0	0
T3	35360	251	0	0
T14	252372	3576	0	0
T15	74085	779	0	0
T16	149099	0	0	0
T17	366398	2319	0	0
T19	440398	1154	0	0
T20	608	5	0	0
T21	794	8	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3720192	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3720192	0	0
T1	78413	12	0	0
T2	5004	23	0	0
T3	35360	231	0	0
T14	252372	2268	0	0
T15	74085	752	0	0
T16	149099	0	0	0
T17	366398	2438	0	0
T19	440398	90222	0	0
T20	608	5	0	0
T21	794	8	0	0
T22	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1472528	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1472528	0	0
T1	78413	39	0	0
T2	5004	38	0	0
T3	35360	195	0	0
T14	252372	2504	0	0
T15	74085	749	0	0
T16	149099	0	0	0
T17	366398	2465	0	0
T19	440398	2686	0	0
T20	608	10	0	0
T21	794	3	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3666070	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3666070	0	0
T1	78413	307	0	0
T2	5004	24	0	0
T3	35360	253	0	0
T14	252372	1736	0	0
T15	74085	523	0	0
T16	149099	0	0	0
T17	366398	2698	0	0
T19	440398	217488	0	0
T20	608	10	0	0
T21	794	3	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1475486	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1475486	0	0
T1	78413	37	0	0
T2	5004	102	0	0
T3	35360	161	0	0
T14	252372	2972	0	0
T15	74085	762	0	0
T16	149099	992	0	0
T17	366398	2174	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	3337221	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	3337221	0	0
T1	78413	8	0	0
T2	5004	12	0	0
T3	35360	145	0	0
T14	252372	3649	0	0
T15	74085	579	0	0
T16	149099	77302	0	0
T17	366398	2131	0	0
T19	440398	0	0	0
T20	608	8	0	0
T21	794	7	0	0
T22	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	1475432	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	1475432	0	0
T1	78413	32	0	0
T2	5004	60	0	0
T3	35360	296	0	0
T14	252372	3776	0	0
T15	74085	551	0	0
T16	149099	0	0	0
T17	366398	2354	0	0
T19	440398	1357	0	0
T20	608	8	0	0
T21	794	8	0	0
T22	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	319378907	2963694	0	0
DepthKnown_A	319378907	319254853	0	0
RvalidKnown_A	319378907	319254853	0	0
WreadyKnown_A	319378907	319254853	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	2963694	0	0
T1	78413	4	0	0
T2	5004	37	0	0
T3	35360	259	0	0
T14	252372	3064	0	0
T15	74085	460	0	0
T16	149099	0	0	0
T17	366398	2488	0	0
T19	440398	104628	0	0
T20	608	8	0	0
T21	794	8	0	0
T22	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319378907	319254853	0	0
T1	78413	78357	0	0
T2	5004	4947	0	0
T3	35360	35317	0	0
T14	252372	252353	0	0
T15	74085	74076	0	0
T16	149099	149098	0	0
T17	366398	366234	0	0
T19	440398	440397	0	0
T20	608	582	0	0
T21	794	752	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0