Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1559999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245214

1

T2

13

T3

198

T4

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611616	1			T1	2		T2	30		T3	501
values[0x0]	582246	1			T2	27		T3	479		T4	42
values[0x1]	611351	1			T1	3		T2	41		T3	477

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1208895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596318

1

T1

3

T2

38

T3

475

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6770	1			T2	1		T16	1		T15	9
valid_sources[0x01]	6701	1			T2	1		T3	4		T4	1
valid_sources[0x02]	6905	1			T3	9		T4	2		T16	1
valid_sources[0x03]	8177	1			T2	1		T3	3		T16	1
valid_sources[0x04]	7720	1			T2	1		T3	10		T16	1
valid_sources[0x05]	7165	1			T2	2		T3	7		T16	1
valid_sources[0x06]	7413	1			T3	3		T15	7		T13	128
valid_sources[0x07]	6691	1			T2	1		T3	10		T16	1
valid_sources[0x08]	6847	1			T3	13		T16	1		T15	12
valid_sources[0x09]	7059	1			T3	9		T16	1		T5	3
valid_sources[0x0a]	6939	1			T3	4		T16	1		T5	12
valid_sources[0x0b]	6466	1			T3	10		T4	1		T15	8
valid_sources[0x0c]	6982	1			T3	5		T5	1		T15	2
valid_sources[0x0d]	6791	1			T3	8		T5	9		T15	6
valid_sources[0x0e]	6945	1			T3	6		T16	1		T5	27
valid_sources[0x0f]	7075	1			T2	2		T3	6		T16	1
valid_sources[0x10]	7310	1			T2	1		T3	4		T5	4
valid_sources[0x11]	7543	1			T3	1		T4	2		T5	2
valid_sources[0x12]	6748	1			T3	6		T5	8		T15	20
valid_sources[0x13]	7607	1			T3	5		T16	1		T5	19
valid_sources[0x14]	7070	1			T3	6		T4	1		T16	1
valid_sources[0x15]	6830	1			T3	1		T16	1		T5	1
valid_sources[0x16]	7154	1			T3	23		T4	2		T16	1
valid_sources[0x17]	7182	1			T3	5		T4	1		T16	1
valid_sources[0x18]	6317	1			T16	1		T14	1		T13	83
valid_sources[0x19]	6958	1			T3	8		T5	2		T13	94
valid_sources[0x1a]	7035	1			T4	2		T16	1		T5	2
valid_sources[0x1b]	6530	1			T3	3		T5	4		T13	92
valid_sources[0x1c]	6927	1			T3	9		T4	3		T5	19
valid_sources[0x1d]	6959	1			T3	4		T4	1		T15	4
valid_sources[0x1e]	6590	1			T3	7		T16	1		T5	1
valid_sources[0x1f]	6604	1			T5	14		T15	4		T13	81
valid_sources[0x20]	6757	1			T2	3		T3	7		T4	2
valid_sources[0x21]	7310	1			T3	6		T5	1		T13	118
valid_sources[0x22]	6395	1			T3	13		T16	1		T5	1
valid_sources[0x23]	9094	1			T3	5		T4	1		T16	1
valid_sources[0x24]	7223	1			T3	5		T4	2		T16	1
valid_sources[0x25]	7414	1			T3	16		T4	2		T16	1
valid_sources[0x26]	7279	1			T3	9		T4	1		T16	1
valid_sources[0x27]	6749	1			T2	1		T3	7		T4	1
valid_sources[0x28]	6584	1			T3	6		T4	1		T16	1
valid_sources[0x29]	7061	1			T3	14		T16	1		T5	31
valid_sources[0x2a]	6763	1			T3	2		T16	1		T5	11
valid_sources[0x2b]	6637	1			T16	1		T15	3		T13	76
valid_sources[0x2c]	7570	1			T16	1		T5	3		T15	13
valid_sources[0x2d]	7267	1			T3	4		T16	1		T5	2
valid_sources[0x2e]	6374	1			T2	1		T16	1		T15	2
valid_sources[0x2f]	6718	1			T3	1		T4	2		T16	1
valid_sources[0x30]	6520	1			T3	3		T16	1		T15	10
valid_sources[0x31]	6889	1			T3	1		T4	1		T16	1
valid_sources[0x32]	6851	1			T2	1		T3	5		T5	4
valid_sources[0x33]	7234	1			T16	1		T5	27		T15	5
valid_sources[0x34]	7545	1			T2	3		T3	2		T16	1
valid_sources[0x35]	8203	1			T3	1		T16	1		T5	4
valid_sources[0x36]	6559	1			T3	5		T16	1		T5	3
valid_sources[0x37]	6321	1			T2	1		T3	4		T4	1
valid_sources[0x38]	7463	1			T3	3		T16	1		T5	7
valid_sources[0x39]	6907	1			T3	6		T16	1		T5	4
valid_sources[0x3a]	6460	1			T4	1		T16	1		T5	19
valid_sources[0x3b]	6639	1			T3	9		T16	1		T5	4
valid_sources[0x3c]	7181	1			T3	8		T16	1		T5	13
valid_sources[0x3d]	7194	1			T2	1		T3	1		T16	1
valid_sources[0x3e]	7022	1			T3	3		T16	1		T15	1
valid_sources[0x3f]	7407	1			T3	13		T4	1		T16	2
valid_sources[0x40]	7782	1			T3	2		T4	2		T16	1
valid_sources[0x41]	6398	1			T3	6		T4	1		T16	1
valid_sources[0x42]	6683	1			T2	2		T3	7		T16	1
valid_sources[0x43]	7092	1			T3	1		T4	2		T5	3
valid_sources[0x44]	7171	1			T3	5		T4	1		T16	1
valid_sources[0x45]	7244	1			T3	5		T4	2		T16	1
valid_sources[0x46]	6432	1			T2	2		T3	5		T4	1
valid_sources[0x47]	7744	1			T3	9		T16	1		T5	12
valid_sources[0x48]	7068	1			T3	9		T16	1		T15	4
valid_sources[0x49]	7764	1			T3	8		T16	1		T5	4
valid_sources[0x4a]	6643	1			T3	2		T16	1		T15	3
valid_sources[0x4b]	7873	1			T3	9		T4	1		T16	1
valid_sources[0x4c]	6599	1			T3	16		T4	2		T16	1
valid_sources[0x4d]	6429	1			T3	6		T4	1		T15	13
valid_sources[0x4e]	6951	1			T4	1		T16	1		T5	2
valid_sources[0x4f]	7289	1			T2	1		T3	4		T16	1
valid_sources[0x50]	6743	1			T3	1		T4	1		T16	1
valid_sources[0x51]	6720	1			T3	4		T16	1		T15	8
valid_sources[0x52]	6550	1			T3	6		T16	1		T5	3
valid_sources[0x53]	6950	1			T3	24		T4	1		T16	1
valid_sources[0x54]	6896	1			T3	10		T5	19		T15	2
valid_sources[0x55]	7888	1			T3	3		T4	1		T5	4
valid_sources[0x56]	6810	1			T2	1		T4	1		T16	1
valid_sources[0x57]	6755	1			T3	11		T4	4		T16	1
valid_sources[0x58]	7175	1			T2	1		T3	2		T4	1
valid_sources[0x59]	6660	1			T16	1		T5	9		T15	7
valid_sources[0x5a]	7163	1			T3	14		T16	1		T5	2
valid_sources[0x5b]	7239	1			T2	1		T3	2		T16	1
valid_sources[0x5c]	7374	1			T3	13		T16	1		T5	12
valid_sources[0x5d]	6920	1			T3	1		T4	2		T16	1
valid_sources[0x5e]	6568	1			T3	3		T13	57		T17	6
valid_sources[0x5f]	6393	1			T2	1		T3	15		T4	1
valid_sources[0x60]	6632	1			T3	5		T5	1		T13	51
valid_sources[0x61]	7403	1			T2	1		T3	2		T4	1
valid_sources[0x62]	6632	1			T3	22		T4	1		T16	1
valid_sources[0x63]	6725	1			T2	1		T3	9		T16	1
valid_sources[0x64]	6404	1			T1	1		T2	1		T3	3
valid_sources[0x65]	6764	1			T2	1		T3	9		T5	4
valid_sources[0x66]	6904	1			T3	4		T4	1		T15	2
valid_sources[0x67]	6718	1			T2	2		T3	4		T4	2
valid_sources[0x68]	7319	1			T3	1		T5	10		T15	10
valid_sources[0x69]	8409	1			T2	1		T3	4		T4	1
valid_sources[0x6a]	7353	1			T1	1		T2	2		T3	11
valid_sources[0x6b]	6931	1			T3	10		T16	1		T15	9
valid_sources[0x6c]	6606	1			T3	3		T16	1		T5	3
valid_sources[0x6d]	7000	1			T3	2		T4	1		T5	5
valid_sources[0x6e]	6919	1			T3	1		T4	1		T16	1
valid_sources[0x6f]	6753	1			T4	2		T16	1		T5	4
valid_sources[0x70]	6788	1			T3	3		T16	1		T15	9
valid_sources[0x71]	7591	1			T3	4		T15	5		T13	69
valid_sources[0x72]	6904	1			T3	9		T16	1		T5	2
valid_sources[0x73]	7919	1			T3	6		T5	18		T15	7
valid_sources[0x74]	6264	1			T3	9		T4	1		T13	58
valid_sources[0x75]	6841	1			T2	2		T3	3		T16	1
valid_sources[0x76]	7395	1			T3	2		T16	1		T15	1
valid_sources[0x77]	7386	1			T2	2		T3	9		T4	2
valid_sources[0x78]	9407	1			T3	4		T4	1		T16	1
valid_sources[0x79]	7577	1			T2	2		T3	6		T16	1
valid_sources[0x7a]	8739	1			T3	3		T16	1		T5	8
valid_sources[0x7b]	7254	1			T3	6		T16	1		T15	2
valid_sources[0x7c]	7403	1			T3	19		T16	1		T5	6
valid_sources[0x7d]	7060	1			T2	1		T3	6		T16	1
valid_sources[0x7e]	6969	1			T3	6		T16	1		T5	11
valid_sources[0x7f]	6795	1			T2	1		T3	4		T16	1
valid_sources[0x80]	8941	1			T1	1		T2	1		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25822

1

T3

24

T4

3

T16

2

values[0x0]

all_enables

biggest_size

193327

1

T2

11

T3

158

T4

14

values[0x1]

all_enables

biggest_size

26065

1

T2

2

T3

16

T4

1