Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	341491864	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341491864	0	0
T1	147200	3200	0	0
T2	6399232	142386	0	0
T3	1678600	38139	0	0
T4	284760	6136	0	0
T5	173768	7271	0	0
T13	2428328	109587	0	0
T14	19208	386	0	0
T15	137368	6021	0	0
T16	10401720	148694	0	0
T17	254352	10813	0	0
T18	724728	570100	0	0
T19	0	1330	0	0
T20	0	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	164864	155736	0	0
T2	6399232	6394920	0	0
T3	1678600	1674736	0	0
T4	284760	281288	0	0
T5	173768	171472	0	0
T13	2428328	2379552	0	0
T14	19208	18200	0	0
T15	137368	136472	0	0
T16	10401720	10398360	0	0
T17	254352	251552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	164864	155736	0	0
T2	6399232	6394920	0	0
T3	1678600	1674736	0	0
T4	284760	281288	0	0
T5	173768	171472	0	0
T13	2428328	2379552	0	0
T14	19208	18200	0	0
T15	137368	136472	0	0
T16	10401720	10398360	0	0
T17	254352	251552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	164864	155736	0	0
T2	6399232	6394920	0	0
T3	1678600	1674736	0	0
T4	284760	281288	0	0
T5	173768	171472	0	0
T13	2428328	2379552	0	0
T14	19208	18200	0	0
T15	137368	136472	0	0
T16	10401720	10398360	0	0
T17	254352	251552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	130906381	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	130906381	0	0
T1	2944	1403	0	0
T2	114272	60485	0	0
T3	29975	14334	0	0
T4	5085	2443	0	0
T5	3103	2824	0	0
T13	43363	41611	0	0
T14	343	199	0	0
T15	2453	2337	0	0
T16	185745	926	0	0
T17	4542	4205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	85596776	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	85596776	0	0
T1	2944	565	0	0
T2	114272	25180	0	0
T3	29975	13069	0	0
T4	5085	1189	0	0
T5	3103	1483	0	0
T13	43363	23204	0	0
T14	343	101	0	0
T15	2453	1228	0	0
T16	185745	73421	0	0
T17	4542	2204	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1481008	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1481008	0	0
T2	114272	798	0	0
T3	29975	161	0	0
T4	5085	40	0	0
T5	3103	53	0	0
T13	43363	427	0	0
T14	343	2	0	0
T15	2453	35	0	0
T16	185745	0	0	0
T17	4542	66	0	0
T18	120788	9515	0	0
T19	0	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3787919	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3787919	0	0
T2	114272	500	0	0
T3	29975	211	0	0
T4	5085	78	0	0
T5	3103	53	0	0
T13	43363	427	0	0
T14	343	2	0	0
T15	2453	35	0	0
T16	185745	0	0	0
T17	4542	66	0	0
T18	120788	11634	0	0
T19	0	107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1500936	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1500936	0	0
T1	2944	21	0	0
T2	114272	831	0	0
T3	29975	109	0	0
T4	5085	99	0	0
T5	3103	58	0	0
T13	43363	685	0	0
T14	343	1	0	0
T15	2453	41	0	0
T16	185745	0	0	0
T17	4542	87	0	0
T18	0	7196	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2943737	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2943737	0	0
T1	2944	22	0	0
T2	114272	318	0	0
T3	29975	103	0	0
T4	5085	55	0	0
T5	3103	58	0	0
T13	43363	685	0	0
T14	343	1	0	0
T15	2453	41	0	0
T16	185745	0	0	0
T17	4542	87	0	0
T18	0	7880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1490714	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1490714	0	0
T1	2944	19	0	0
T2	114272	2094	0	0
T3	29975	139	0	0
T4	5085	22	0	0
T5	3103	44	0	0
T13	43363	703	0	0
T14	343	1	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	83	0	0
T18	0	11676	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2750406	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2750406	0	0
T1	2944	5	0	0
T2	114272	1596	0	0
T3	29975	204	0	0
T4	5085	30	0	0
T5	3103	44	0	0
T13	43363	703	0	0
T14	343	1	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	83	0	0
T18	0	12355	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1493410	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1493410	0	0
T1	2944	20	0	0
T2	114272	0	0	0
T3	29975	153	0	0
T4	5085	42	0	0
T5	3103	48	0	0
T13	43363	679	0	0
T14	343	1	0	0
T15	2453	58	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	0	11491	0	0
T19	0	121	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	4008370	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	4008370	0	0
T1	2944	4	0	0
T2	114272	0	0	0
T3	29975	173	0	0
T4	5085	21	0	0
T5	3103	48	0	0
T13	43363	679	0	0
T14	343	1	0	0
T15	2453	58	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	0	9318	0	0
T19	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1443270	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1443270	0	0
T1	2944	10	0	0
T2	114272	1733	0	0
T3	29975	224	0	0
T4	5085	56	0	0
T5	3103	61	0	0
T13	43363	658	0	0
T14	343	1	0	0
T15	2453	33	0	0
T16	185745	0	0	0
T17	4542	94	0	0
T18	0	7950	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3129503	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3129503	0	0
T1	2944	11	0	0
T2	114272	1715	0	0
T3	29975	275	0	0
T4	5085	34	0	0
T5	3103	61	0	0
T13	43363	658	0	0
T14	343	1	0	0
T15	2453	33	0	0
T16	185745	0	0	0
T17	4542	94	0	0
T18	0	8239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1528778	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1528778	0	0
T1	2944	18	0	0
T2	114272	1201	0	0
T3	29975	141	0	0
T4	5085	34	0	0
T5	3103	50	0	0
T13	43363	466	0	0
T14	343	0	0	0
T15	2453	63	0	0
T16	185745	0	0	0
T17	4542	68	0	0
T18	0	12910	0	0
T19	0	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3514305	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3514305	0	0
T1	2944	5	0	0
T2	114272	656	0	0
T3	29975	156	0	0
T4	5085	12	0	0
T5	3103	50	0	0
T13	43363	466	0	0
T14	343	0	0	0
T15	2453	63	0	0
T16	185745	0	0	0
T17	4542	68	0	0
T18	0	13181	0	0
T19	0	79	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1493398	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1493398	0	0
T1	2944	15	0	0
T2	114272	2227	0	0
T3	29975	230	0	0
T4	5085	95	0	0
T5	3103	70	0	0
T13	43363	468	0	0
T14	343	1	0	0
T15	2453	50	0	0
T16	185745	926	0	0
T17	4542	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2989586	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2989586	0	0
T1	2944	21	0	0
T2	114272	2966	0	0
T3	29975	278	0	0
T4	5085	55	0	0
T5	3103	70	0	0
T13	43363	468	0	0
T14	343	1	0	0
T15	2453	50	0	0
T16	185745	73421	0	0
T17	4542	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1475733	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1475733	0	0
T1	2944	13	0	0
T2	114272	368	0	0
T3	29975	170	0	0
T4	5085	43	0	0
T5	3103	68	0	0
T13	43363	1156	0	0
T14	343	2	0	0
T15	2453	44	0	0
T16	185745	0	0	0
T17	4542	74	0	0
T18	0	11452	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2949753	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2949753	0	0
T1	2944	30	0	0
T2	114272	23	0	0
T3	29975	182	0	0
T4	5085	39	0	0
T5	3103	68	0	0
T13	43363	1156	0	0
T14	343	2	0	0
T15	2453	44	0	0
T16	185745	0	0	0
T17	4542	74	0	0
T18	0	10125	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1515547	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1515547	0	0
T1	2944	24	0	0
T2	114272	917	0	0
T3	29975	157	0	0
T4	5085	60	0	0
T5	3103	62	0	0
T13	43363	915	0	0
T14	343	3	0	0
T15	2453	57	0	0
T16	185745	0	0	0
T17	4542	79	0	0
T18	0	16789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3462021	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3462021	0	0
T1	2944	11	0	0
T2	114272	1	0	0
T3	29975	152	0	0
T4	5085	47	0	0
T5	3103	62	0	0
T13	43363	914	0	0
T14	343	3	0	0
T15	2453	57	0	0
T16	185745	0	0	0
T17	4542	79	0	0
T18	0	11563	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1483232	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1483232	0	0
T2	114272	1217	0	0
T3	29975	190	0	0
T4	5085	88	0	0
T5	3103	49	0	0
T13	43363	511	0	0
T14	343	1	0	0
T15	2453	56	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	120788	8765	0	0
T19	0	106	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3091702	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3091702	0	0
T2	114272	764	0	0
T3	29975	221	0	0
T4	5085	18	0	0
T5	3103	49	0	0
T13	43363	511	0	0
T14	343	1	0	0
T15	2453	56	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	120788	11908	0	0
T19	0	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1534129	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1534129	0	0
T1	2944	38	0	0
T2	114272	3643	0	0
T3	29975	137	0	0
T4	5085	15	0	0
T5	3103	59	0	0
T13	43363	993	0	0
T14	343	1	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	83	0	0
T18	0	11292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2568234	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2568234	0	0
T1	2944	27	0	0
T2	114272	2605	0	0
T3	29975	145	0	0
T4	5085	38	0	0
T5	3103	59	0	0
T13	43363	993	0	0
T14	343	1	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	83	0	0
T18	0	7605	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1510632	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1510632	0	0
T1	2944	12	0	0
T2	114272	2100	0	0
T3	29975	132	0	0
T4	5085	83	0	0
T5	3103	34	0	0
T13	43363	749	0	0
T14	343	2	0	0
T15	2453	57	0	0
T16	185745	0	0	0
T17	4542	66	0	0
T18	0	11163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3356537	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3356537	0	0
T1	2944	11	0	0
T2	114272	651	0	0
T3	29975	153	0	0
T4	5085	65	0	0
T5	3103	34	0	0
T13	43363	748	0	0
T14	343	2	0	0
T15	2453	57	0	0
T16	185745	0	0	0
T17	4542	66	0	0
T18	0	9879	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1476580	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1476580	0	0
T1	2944	38	0	0
T2	114272	2292	0	0
T3	29975	173	0	0
T4	5085	45	0	0
T5	3103	44	0	0
T13	43363	442	0	0
T14	343	2	0	0
T15	2453	43	0	0
T16	185745	0	0	0
T17	4542	92	0	0
T18	0	13059	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3051585	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3051585	0	0
T1	2944	29	0	0
T2	114272	1693	0	0
T3	29975	228	0	0
T4	5085	48	0	0
T5	3103	44	0	0
T13	43363	442	0	0
T14	343	2	0	0
T15	2453	43	0	0
T16	185745	0	0	0
T17	4542	92	0	0
T18	0	14631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1512822	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1512822	0	0
T1	2944	59	0	0
T2	114272	1502	0	0
T3	29975	184	0	0
T4	5085	24	0	0
T5	3103	59	0	0
T13	43363	1142	0	0
T14	343	1	0	0
T15	2453	44	0	0
T16	185745	0	0	0
T17	4542	73	0	0
T18	0	12679	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3328977	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3328977	0	0
T1	2944	60	0	0
T2	114272	1882	0	0
T3	29975	224	0	0
T4	5085	57	0	0
T5	3103	59	0	0
T13	43363	1142	0	0
T14	343	1	0	0
T15	2453	44	0	0
T16	185745	0	0	0
T17	4542	73	0	0
T18	0	12085	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1490807	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1490807	0	0
T1	2944	10	0	0
T2	114272	0	0	0
T3	29975	225	0	0
T4	5085	40	0	0
T5	3103	64	0	0
T13	43363	1172	0	0
T14	343	4	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	89	0	0
T18	0	9229	0	0
T19	0	154	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2460881	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2460881	0	0
T1	2944	6	0	0
T2	114272	0	0	0
T3	29975	214	0	0
T4	5085	34	0	0
T5	3103	64	0	0
T13	43363	1171	0	0
T14	343	4	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	89	0	0
T18	0	8154	0	0
T19	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1447103	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1447103	0	0
T1	2944	12	0	0
T2	114272	252	0	0
T3	29975	166	0	0
T4	5085	14	0	0
T5	3103	64	0	0
T13	43363	714	0	0
T14	343	3	0	0
T15	2453	33	0	0
T16	185745	0	0	0
T17	4542	84	0	0
T18	0	10528	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3020241	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3020241	0	0
T1	2944	1	0	0
T2	114272	313	0	0
T3	29975	210	0	0
T4	5085	9	0	0
T5	3103	64	0	0
T13	43363	713	0	0
T14	343	3	0	0
T15	2453	33	0	0
T16	185745	0	0	0
T17	4542	84	0	0
T18	0	8675	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1481915	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1481915	0	0
T1	2944	38	0	0
T2	114272	681	0	0
T3	29975	241	0	0
T4	5085	106	0	0
T5	3103	41	0	0
T13	43363	1748	0	0
T14	343	2	0	0
T15	2453	39	0	0
T16	185745	0	0	0
T17	4542	71	0	0
T18	0	6416	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3267318	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3267318	0	0
T1	2944	11	0	0
T2	114272	615	0	0
T3	29975	222	0	0
T4	5085	124	0	0
T5	3103	41	0	0
T13	43363	1748	0	0
T14	343	2	0	0
T15	2453	39	0	0
T16	185745	0	0	0
T17	4542	71	0	0
T18	0	7484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1494977	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1494977	0	0
T1	2944	19	0	0
T2	114272	473	0	0
T3	29975	366	0	0
T4	5085	65	0	0
T5	3103	52	0	0
T13	43363	991	0	0
T14	343	1	0	0
T15	2453	60	0	0
T16	185745	0	0	0
T17	4542	84	0	0
T18	0	6973	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2614399	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2614399	0	0
T1	2944	4	0	0
T2	114272	331	0	0
T3	29975	326	0	0
T4	5085	39	0	0
T5	3103	52	0	0
T13	43363	990	0	0
T14	343	1	0	0
T15	2453	60	0	0
T16	185745	0	0	0
T17	4542	84	0	0
T18	0	8666	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1450192	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1450192	0	0
T1	2944	24	0	0
T2	114272	1734	0	0
T3	29975	204	0	0
T4	5085	40	0	0
T5	3103	60	0	0
T13	43363	615	0	0
T14	343	1	0	0
T15	2453	53	0	0
T16	185745	0	0	0
T17	4542	67	0	0
T18	0	10194	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3358753	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3358753	0	0
T1	2944	15	0	0
T2	114272	873	0	0
T3	29975	174	0	0
T4	5085	24	0	0
T5	3103	60	0	0
T13	43363	615	0	0
T14	343	1	0	0
T15	2453	53	0	0
T16	185745	0	0	0
T17	4542	67	0	0
T18	0	10994	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1442343	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1442343	0	0
T1	2944	122	0	0
T2	114272	511	0	0
T3	29975	229	0	0
T4	5085	37	0	0
T5	3103	60	0	0
T13	43363	699	0	0
T14	343	3	0	0
T15	2453	46	0	0
T16	185745	0	0	0
T17	4542	103	0	0
T18	0	12249	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2922656	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2922656	0	0
T1	2944	107	0	0
T2	114272	756	0	0
T3	29975	294	0	0
T4	5085	57	0	0
T5	3103	60	0	0
T13	43363	699	0	0
T14	343	3	0	0
T15	2453	46	0	0
T16	185745	0	0	0
T17	4542	103	0	0
T18	0	10861	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1466385	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1466385	0	0
T1	2944	30	0	0
T2	114272	1076	0	0
T3	29975	213	0	0
T4	5085	29	0	0
T5	3103	52	0	0
T13	43363	470	0	0
T14	343	1	0	0
T15	2453	52	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	0	11420	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2681839	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2681839	0	0
T1	2944	24	0	0
T2	114272	1043	0	0
T3	29975	251	0	0
T4	5085	54	0	0
T5	3103	52	0	0
T13	43363	470	0	0
T14	343	1	0	0
T15	2453	52	0	0
T16	185745	0	0	0
T17	4542	80	0	0
T18	0	9817	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1489771	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1489771	0	0
T2	114272	1118	0	0
T3	29975	216	0	0
T4	5085	40	0	0
T5	3103	47	0	0
T13	43363	1175	0	0
T14	343	0	0	0
T15	2453	39	0	0
T16	185745	0	0	0
T17	4542	93	0	0
T18	120788	14980	0	0
T19	0	136	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3108610	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3108610	0	0
T2	114272	1384	0	0
T3	29975	239	0	0
T4	5085	42	0	0
T5	3103	47	0	0
T13	43363	1175	0	0
T14	343	0	0	0
T15	2453	39	0	0
T16	185745	0	0	0
T17	4542	93	0	0
T18	120788	11456	0	0
T19	0	101	0	0
T20	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1499648	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1499648	0	0
T1	2944	17	0	0
T2	114272	1155	0	0
T3	29975	164	0	0
T4	5085	60	0	0
T5	3103	54	0	0
T13	43363	1035	0	0
T14	343	2	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	67	0	0
T18	0	15628	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3562511	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3562511	0	0
T1	2944	17	0	0
T2	114272	1609	0	0
T3	29975	183	0	0
T4	5085	32	0	0
T5	3103	54	0	0
T13	43363	1035	0	0
T14	343	2	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	67	0	0
T18	0	12880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1514446	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1514446	0	0
T1	2944	11	0	0
T2	114272	1167	0	0
T3	29975	134	0	0
T4	5085	15	0	0
T5	3103	45	0	0
T13	43363	449	0	0
T14	343	1	0	0
T15	2453	42	0	0
T16	185745	0	0	0
T17	4542	79	0	0
T18	0	15859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	2930011	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	2930011	0	0
T1	2944	8	0	0
T2	114272	937	0	0
T3	29975	170	0	0
T4	5085	36	0	0
T5	3103	45	0	0
T13	43363	449	0	0
T14	343	1	0	0
T15	2453	42	0	0
T16	185745	0	0	0
T17	4542	79	0	0
T18	0	12144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1525312	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1525312	0	0
T1	2944	36	0	0
T2	114272	1300	0	0
T3	29975	188	0	0
T4	5085	71	0	0
T5	3103	55	0	0
T13	43363	1389	0	0
T14	343	2	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	88	0	0
T18	0	12639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3478797	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3478797	0	0
T1	2944	74	0	0
T2	114272	982	0	0
T3	29975	191	0	0
T4	5085	65	0	0
T5	3103	55	0	0
T13	43363	1388	0	0
T14	343	2	0	0
T15	2453	40	0	0
T16	185745	0	0	0
T17	4542	88	0	0
T18	0	11346	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1523774	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1523774	0	0
T1	2944	16	0	0
T2	114272	485	0	0
T3	29975	255	0	0
T4	5085	37	0	0
T5	3103	59	0	0
T13	43363	718	0	0
T14	343	1	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	91	0	0
T18	0	13152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3157660	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3157660	0	0
T1	2944	46	0	0
T2	114272	875	0	0
T3	29975	283	0	0
T4	5085	27	0	0
T5	3103	59	0	0
T13	43363	718	0	0
T14	343	1	0	0
T15	2453	38	0	0
T16	185745	0	0	0
T17	4542	91	0	0
T18	0	10583	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	1537381	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	1537381	0	0
T1	2944	45	0	0
T2	114272	666	0	0
T3	29975	203	0	0
T4	5085	15	0	0
T5	3103	70	0	0
T13	43363	1220	0	0
T14	343	3	0	0
T15	2453	49	0	0
T16	185745	0	0	0
T17	4542	89	0	0
T18	0	10924	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	304132712	3188153	0	0
DepthKnown_A	304132712	304001807	0	0
RvalidKnown_A	304132712	304001807	0	0
WreadyKnown_A	304132712	304001807	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	3188153	0	0
T1	2944	16	0	0
T2	114272	92	0	0
T3	29975	170	0	0
T4	5085	49	0	0
T5	3103	70	0	0
T13	43363	1220	0	0
T14	343	3	0	0
T15	2453	49	0	0
T16	185745	0	0	0
T17	4542	89	0	0
T18	0	10509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304132712	304001807	0	0
T1	2944	2781	0	0
T2	114272	114195	0	0
T3	29975	29906	0	0
T4	5085	5023	0	0
T5	3103	3062	0	0
T13	43363	42492	0	0
T14	343	325	0	0
T15	2453	2437	0	0
T16	185745	185685	0	0
T17	4542	4492	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0