Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_peri
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.08 100.00 95.42 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tlul_assert_device_adc_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_alert_handler 100.00 100.00 100.00 100.00
tlul_assert_device_aon_timer_aon 100.00 100.00 100.00 100.00
tlul_assert_device_ast 100.00 100.00 100.00 100.00
tlul_assert_device_clkmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_gpio 100.00 100.00 100.00 100.00
tlul_assert_device_i2c0 100.00 100.00 100.00 100.00
tlul_assert_device_i2c1 100.00 100.00 100.00 100.00
tlul_assert_device_i2c2 100.00 100.00 100.00 100.00
tlul_assert_device_lc_ctrl 100.00 100.00 100.00 100.00
tlul_assert_device_otp_ctrl__core 100.00 100.00 100.00 100.00
tlul_assert_device_otp_ctrl__prim 100.00 100.00 100.00 100.00
tlul_assert_device_pattgen 100.00 100.00 100.00 100.00
tlul_assert_device_pinmux_aon 100.00 100.00 100.00 100.00
tlul_assert_device_pwm_aon 100.00 100.00 100.00 100.00
tlul_assert_device_pwrmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_rstmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_rv_timer 100.00 100.00 100.00 100.00
tlul_assert_device_sensor_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_spi_device 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_ret_aon__ram 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_ret_aon__regs 100.00 100.00 100.00 100.00
tlul_assert_device_sysrst_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_uart0 100.00 100.00 100.00 100.00
tlul_assert_device_uart1 100.00 100.00 100.00 100.00
tlul_assert_device_uart2 100.00 100.00 100.00 100.00
tlul_assert_device_uart3 100.00 100.00 100.00 100.00
tlul_assert_host_main 100.00 100.00 100.00 100.00
u_s1n_28 98.72 100.00 94.89 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : xbar_peri
Line No.TotalCoveredPercent
TOTAL111111100.00
CONT_ASSIGN11200
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN20811100.00
ALWAYS2125555100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv' or '../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 excluded
126 1 1
127 1 1
129 1 1
130 1 1
132 1 1
133 1 1
135 1 1
136 1 1
138 1 1
139 1 1
141 1 1
142 1 1
144 1 1
145 1 1
147 1 1
148 1 1
150 1 1
151 1 1
153 1 1
154 1 1
156 1 1
157 1 1
159 1 1
160 1 1
162 1 1
163 1 1
165 1 1
166 1 1
168 1 1
169 1 1
171 1 1
172 1 1
174 1 1
175 1 1
177 1 1
178 1 1
180 1 1
181 1 1
183 1 1
184 1 1
186 1 1
187 1 1
189 1 1
190 1 1
192 1 1
193 1 1
195 1 1
196 1 1
198 1 1
199 1 1
201 1 1
202 1 1
204 1 1
205 1 1
207 1 1
208 1 1
212 1 1
213 1 1
215 1 1
217 1 1
219 1 1
221 1 1
223 1 1
225 1 1
227 1 1
229 1 1
231 1 1
233 1 1
235 1 1
237 1 1
239 1 1
241 1 1
243 1 1
245 1 1
247 1 1
249 1 1
251 1 1
253 1 1
255 1 1
257 1 1
259 1 1
261 1 1
263 1 1
265 1 1
267 1 1
269 1 1
271 1 1
273 1 1
275 1 1
277 1 1
279 1 1
281 1 1
283 1 1
285 1 1
287 1 1
289 1 1
291 1 1
293 1 1
295 1 1
297 1 1
299 1 1
301 1 1
303 1 1
305 1 1
307 1 1
309 1 1
311 1 1
313 1 1
315 1 1
317 1 1
319 1 1
MISSING_ELSE


Cond Coverage for Module : xbar_peri
TotalCoveredPercent
Conditions5454100.00
Logical5454100.00
Non-Logical00
Event00

 LINE       213
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART0)) == tl_peri_pkg::ADDR_SPACE_UART0)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART1)) == tl_peri_pkg::ADDR_SPACE_UART1)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART2)) == tl_peri_pkg::ADDR_SPACE_UART2)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       225
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART3)) == tl_peri_pkg::ADDR_SPACE_UART3)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       229
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C0)) == tl_peri_pkg::ADDR_SPACE_I2C0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       233
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C1)) == tl_peri_pkg::ADDR_SPACE_I2C1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       237
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C2)) == tl_peri_pkg::ADDR_SPACE_I2C2)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PATTGEN)) == tl_peri_pkg::ADDR_SPACE_PATTGEN)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_GPIO)) == tl_peri_pkg::ADDR_SPACE_GPIO)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       249
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SPI_DEVICE)) == tl_peri_pkg::ADDR_SPACE_SPI_DEVICE)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       253
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RV_TIMER)) == tl_peri_pkg::ADDR_SPACE_RV_TIMER)
            ---------------------------------------------------1---------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWRMGR_AON)) == tl_peri_pkg::ADDR_SPACE_PWRMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       261
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RSTMGR_AON)) == tl_peri_pkg::ADDR_SPACE_RSTMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       265
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_CLKMGR_AON)) == tl_peri_pkg::ADDR_SPACE_CLKMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       269
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PINMUX_AON)) == tl_peri_pkg::ADDR_SPACE_PINMUX_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       273
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__CORE)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__CORE)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       277
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__PRIM)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__PRIM)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       281
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_LC_CTRL)) == tl_peri_pkg::ADDR_SPACE_LC_CTRL)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       285
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SENSOR_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SENSOR_CTRL_AON)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       289
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ALERT_HANDLER)) == tl_peri_pkg::ADDR_SPACE_ALERT_HANDLER)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AST)) == tl_peri_pkg::ADDR_SPACE_AST)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       297
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__RAM)
            -----------------------------------------------------------------1-----------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       301
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__REGS)
            ------------------------------------------------------------------1------------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       305
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AON_TIMER_AON)) == tl_peri_pkg::ADDR_SPACE_AON_TIMER_AON)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       309
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ADC_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_ADC_CTRL_AON)
            -------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       313
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SYSRST_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SYSRST_CTRL_AON)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       317
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWM_AON)) == tl_peri_pkg::ADDR_SPACE_PWM_AON)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : xbar_peri
TotalCoveredPercent
Totals 618 618 100.00
Total Bits 8218 8218 100.00
Total Bits 0->1 4109 4109 100.00
Total Bits 1->0 4109 4109 100.00

Ports 618 618 100.00
Port Bits 8218 8218 100.00
Port Bits 0->1 4109 4109 100.00
Port Bits 1->0 4109 4109 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_peri_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_peri_ni Yes Yes T1,T13,T19 Yes T1,T2,T3 INPUT
tl_main_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 INPUT
tl_main_i.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 INPUT
tl_main_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart0_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart0_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_uart0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[29:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_uart0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart0_i.d_error Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_source[7:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_uart0_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_uart0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart1_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[29:17] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_error Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
tl_uart1_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_uart1_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_uart1_i.d_data[31:0] Yes Yes T3,T4,T5 Yes T1,T3,T4 INPUT
tl_uart1_i.d_sink Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_uart1_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_uart1_i.d_size[1:0] Yes Yes T1,T4,T5 Yes T2,T3,T4 INPUT
tl_uart1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T3,T4,T16 INPUT
tl_uart1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart2_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart2_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_uart2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[16:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[29:18] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_i.d_error Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_uart2_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_uart2_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_uart2_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_uart2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart3_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart3_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_uart3_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_uart3_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[29:18] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_uart3_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart3_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_uart3_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_uart3_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_uart3_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_uart3_i.d_sink Yes Yes T3,T5,T15 Yes T3,T4,T5 INPUT
tl_uart3_i.d_source[7:0] Yes Yes T3,T5,T15 Yes T3,T4,T5 INPUT
tl_uart3_i.d_size[1:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_uart3_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T5 INPUT
tl_uart3_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c0_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[18:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_error Yes Yes T2,T3,T16 Yes T2,T3,T5 INPUT
tl_i2c0_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i2c0_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_i2c0_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T5 INPUT
tl_i2c0_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T5 INPUT
tl_i2c0_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i2c0_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i2c0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_i2c0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c1_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[18:17] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_error Yes Yes T1,T2,T3 Yes T2,T3,T5 INPUT
tl_i2c1_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_i2c1_i.d_data[31:0] Yes Yes T2,T3,T5 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_sink Yes Yes T2,T3,T5 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_i2c1_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T3,T5,T15 INPUT
tl_i2c1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T3,T5,T15 INPUT
tl_i2c1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c2_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c2_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_i2c2_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[18] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_error Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_i2c2_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i2c2_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i2c2_i.d_sink Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_i2c2_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T3,T4,T16 INPUT
tl_i2c2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pattgen_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pattgen_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_pattgen_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[16:6] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_address[19:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_error Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_pattgen_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_pattgen_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T3,T4 INPUT
tl_pattgen_i.d_data[31:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_pattgen_i.d_sink Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_pattgen_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_pattgen_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T2,T3,T4 INPUT
tl_pattgen_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pwm_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_error Yes Yes T3,T5,T15 Yes T3,T5,T15 INPUT
tl_pwm_aon_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_pwm_aon_i.d_data[31:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_pwm_aon_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_pwm_aon_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_pwm_aon_i.d_size[1:0] Yes Yes T3,T5,T15 Yes T3,T4,T5 INPUT
tl_pwm_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_pwm_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_gpio_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_gpio_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[17:6] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[29:19] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_error Yes Yes T2,T3,T4 Yes T2,T3,T5 INPUT
tl_gpio_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T3,T4 INPUT
tl_gpio_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_gpio_i.d_sink Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_gpio_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T3,T5 INPUT
tl_gpio_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_gpio_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_spi_device_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_spi_device_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_spi_device_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[12:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[15:13] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[29:19] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_spi_device_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_error Yes Yes T2,T3,T4 Yes T3,T4,T16 INPUT
tl_spi_device_i.d_user.data_intg[6:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_spi_device_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_spi_device_i.d_data[31:0] Yes Yes T3,T5,T15 Yes T2,T3,T4 INPUT
tl_spi_device_i.d_sink Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_spi_device_i.d_source[7:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_spi_device_i.d_size[1:0] Yes Yes T3,T16,T5 Yes T3,T5,T15 INPUT
tl_spi_device_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_opcode[0] Yes Yes *T3,*T4,*T16 Yes T3,T4,T5 INPUT
tl_spi_device_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_rv_timer_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_rv_timer_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[8:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[19:9] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pwrmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[21:7] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_error Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T2,T3,T5 INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T3,T4,T5 INPUT
tl_pwrmgr_aon_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_pwrmgr_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_pwrmgr_aon_i.d_size[1:0] Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_pwrmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_rstmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[21:17] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_clkmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[21:18] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_pinmux_aon_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_pinmux_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_pinmux_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_error Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T3,T4 INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T1,T3,T4 INPUT
tl_pinmux_aon_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_pinmux_aon_i.d_sink Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_pinmux_aon_i.d_source[7:0] Yes Yes T3,T4,T5 Yes T1,T3,T4 INPUT
tl_pinmux_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T3,T4,T5 INPUT
tl_pinmux_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_pinmux_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_valid Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_otp_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_otp_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[15:12] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_error Yes Yes T2,T3,T4 Yes T3,T5,T15 INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T3,T5,T15 Yes T2,T3,T5 INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
tl_otp_ctrl__core_i.d_data[31:0] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
tl_otp_ctrl__core_i.d_sink Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
tl_otp_ctrl__core_i.d_source[7:0] Yes Yes T2,T3,T5 Yes T3,T4,T5 INPUT
tl_otp_ctrl__core_i.d_size[1:0] Yes Yes T2,T3,T5 Yes T3,T5,T15 INPUT
tl_otp_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_opcode[0] Yes Yes *T2,*T3,*T5 Yes T2,T3,T4 INPUT
tl_otp_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[14:5] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[17:15] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_error Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_otp_ctrl__prim_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_otp_ctrl__prim_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_otp_ctrl__prim_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T4 INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_lc_ctrl_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[17:8] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_error Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_data[31:0] Yes Yes T3,T4,T5 Yes T3,T5,T15 INPUT
tl_lc_ctrl_i.d_sink Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_source[7:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_size[1:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T3,T4,T5 INPUT
tl_lc_ctrl_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[18:17] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[21:20] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 INPUT
tl_sensor_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_opcode[0] Yes Yes *T2,*T3,*T5 Yes T2,T3,T5 INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_alert_handler_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_alert_handler_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[10:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[15:11] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[19:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[21] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error Yes Yes T3,T5,T15 Yes T3,T4,T16 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T1,T3,T4 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T3,T4,T16 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[20:12] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T3,T4,T5 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_aon_timer_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_aon_timer_aon_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_aon_timer_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_error Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_aon_timer_aon_i.d_data[31:0] Yes Yes T2,T3,T5 Yes T3,T4,T5 INPUT
tl_aon_timer_aon_i.d_sink Yes Yes T3,T4,T5 Yes T2,T3,T4 INPUT
tl_aon_timer_aon_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_aon_timer_aon_i.d_size[1:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_aon_timer_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_opcode[0] Yes Yes *T3,*T5,*T15 Yes T2,T3,T5 INPUT
tl_aon_timer_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[15:8] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[21:18] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[17:7] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_ast_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.instr_type[3:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_ast_o.a_user.rsvd[4:0] Yes Yes T1,T2,T14 Yes T1,T2,T14 OUTPUT
tl_ast_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[9:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[18:10] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[21:20] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_error Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_ast_i.d_sink Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_ast_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_ast_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_ast_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_ast_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : xbar_peri
Line No.TotalCoveredPercent
Branches 28 28 100.00
IF 213 28 28 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv' or '../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 213 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART0)) == tl_peri_pkg::ADDR_SPACE_UART0)) -2-: 217 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART1)) == tl_peri_pkg::ADDR_SPACE_UART1)) -3-: 221 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART2)) == tl_peri_pkg::ADDR_SPACE_UART2)) -4-: 225 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART3)) == tl_peri_pkg::ADDR_SPACE_UART3)) -5-: 229 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C0)) == tl_peri_pkg::ADDR_SPACE_I2C0)) -6-: 233 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C1)) == tl_peri_pkg::ADDR_SPACE_I2C1)) -7-: 237 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C2)) == tl_peri_pkg::ADDR_SPACE_I2C2)) -8-: 241 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PATTGEN)) == tl_peri_pkg::ADDR_SPACE_PATTGEN)) -9-: 245 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_GPIO)) == tl_peri_pkg::ADDR_SPACE_GPIO)) -10-: 249 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SPI_DEVICE)) == tl_peri_pkg::ADDR_SPACE_SPI_DEVICE)) -11-: 253 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RV_TIMER)) == tl_peri_pkg::ADDR_SPACE_RV_TIMER)) -12-: 257 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWRMGR_AON)) == tl_peri_pkg::ADDR_SPACE_PWRMGR_AON)) -13-: 261 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RSTMGR_AON)) == tl_peri_pkg::ADDR_SPACE_RSTMGR_AON)) -14-: 265 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_CLKMGR_AON)) == tl_peri_pkg::ADDR_SPACE_CLKMGR_AON)) -15-: 269 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PINMUX_AON)) == tl_peri_pkg::ADDR_SPACE_PINMUX_AON)) -16-: 273 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__CORE)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__CORE)) -17-: 277 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__PRIM)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__PRIM)) -18-: 281 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_LC_CTRL)) == tl_peri_pkg::ADDR_SPACE_LC_CTRL)) -19-: 285 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SENSOR_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SENSOR_CTRL_AON)) -20-: 289 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ALERT_HANDLER)) == tl_peri_pkg::ADDR_SPACE_ALERT_HANDLER)) -21-: 293 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AST)) == tl_peri_pkg::ADDR_SPACE_AST)) -22-: 297 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__RAM)) -23-: 301 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__REGS)) -24-: 305 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AON_TIMER_AON)) == tl_peri_pkg::ADDR_SPACE_AON_TIMER_AON)) -25-: 309 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ADC_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_ADC_CTRL_AON)) -26-: 313 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SYSRST_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SYSRST_CTRL_AON)) -27-: 317 if (((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWM_AON)) == tl_peri_pkg::ADDR_SPACE_PWM_AON))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T3,T4
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T2,T3,T4
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T3,T4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T2,T3,T4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3

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