Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1827572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

287160

1

T1

6

T2

116

T3

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	713995	1			T1	28		T2	452		T3	199
values[0x0]	685875	1			T1	7		T2	94		T3	41
values[0x1]	714862	1			T1	34		T2	472		T3	199

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1416492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

698240

1

T1

24

T2

409

T3

178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7982	1			T2	2		T3	1		T4	2
valid_sources[0x01]	8281	1			T3	2		T4	2		T13	4
valid_sources[0x02]	9007	1			T3	2		T4	4		T13	3
valid_sources[0x03]	7765	1			T2	1		T3	1		T4	2
valid_sources[0x04]	8154	1			T3	4		T4	7		T13	6
valid_sources[0x05]	7677	1			T2	33		T3	10		T4	3
valid_sources[0x06]	8671	1			T2	2		T3	3		T4	5
valid_sources[0x07]	8391	1			T1	1		T4	1		T13	1
valid_sources[0x08]	8532	1			T2	17		T3	1		T4	3
valid_sources[0x09]	8404	1			T2	1		T4	2		T13	7
valid_sources[0x0a]	9311	1			T3	1		T4	6		T15	10
valid_sources[0x0b]	7702	1			T3	2		T4	1		T13	1
valid_sources[0x0c]	7107	1			T2	23		T3	4		T4	4
valid_sources[0x0d]	8438	1			T4	3		T13	1		T15	11
valid_sources[0x0e]	9328	1			T2	3		T3	2		T4	1
valid_sources[0x0f]	7797	1			T3	7		T4	4		T13	4
valid_sources[0x10]	8075	1			T1	1		T13	5		T15	13
valid_sources[0x11]	7790	1			T2	37		T3	1		T4	1
valid_sources[0x12]	8764	1			T2	2		T3	1		T4	2
valid_sources[0x13]	7742	1			T2	9		T4	1		T13	5
valid_sources[0x14]	8093	1			T2	2		T3	1		T4	1
valid_sources[0x15]	9055	1			T13	7		T15	5		T19	2
valid_sources[0x16]	7952	1			T3	5		T4	2		T13	3
valid_sources[0x17]	7878	1			T1	1		T2	4		T3	7
valid_sources[0x18]	8365	1			T2	2		T3	6		T13	2
valid_sources[0x19]	8648	1			T2	1		T4	1		T13	10
valid_sources[0x1a]	7627	1			T1	1		T2	17		T4	7
valid_sources[0x1b]	7582	1			T2	1		T3	2		T4	2
valid_sources[0x1c]	8178	1			T4	1		T13	7		T14	22
valid_sources[0x1d]	7725	1			T2	5		T3	4		T4	3
valid_sources[0x1e]	8069	1			T1	2		T2	3		T3	5
valid_sources[0x1f]	7649	1			T2	2		T3	3		T4	1
valid_sources[0x20]	8250	1			T2	1		T13	3		T15	9
valid_sources[0x21]	8259	1			T1	1		T2	3		T3	2
valid_sources[0x22]	7044	1			T2	1		T3	3		T4	2
valid_sources[0x23]	8369	1			T2	3		T3	5		T4	3
valid_sources[0x24]	8739	1			T2	3		T3	1		T13	1
valid_sources[0x25]	9058	1			T2	11		T3	2		T4	3
valid_sources[0x26]	8768	1			T2	2		T4	4		T13	4
valid_sources[0x27]	8888	1			T3	4		T4	3		T13	4
valid_sources[0x28]	8244	1			T4	2		T13	11		T15	9
valid_sources[0x29]	8043	1			T1	1		T2	1		T4	4
valid_sources[0x2a]	8746	1			T3	4		T4	4		T13	5
valid_sources[0x2b]	7646	1			T2	21		T3	1		T4	3
valid_sources[0x2c]	8843	1			T2	1		T4	3		T13	6
valid_sources[0x2d]	7879	1			T4	4		T13	4		T15	7
valid_sources[0x2e]	8631	1			T2	1		T3	1		T4	4
valid_sources[0x2f]	9877	1			T1	2		T2	2		T13	9
valid_sources[0x30]	8471	1			T4	4		T13	11		T15	11
valid_sources[0x31]	7920	1			T2	1		T4	2		T13	6
valid_sources[0x32]	7824	1			T1	5		T3	1		T4	1
valid_sources[0x33]	9520	1			T2	4		T4	1		T13	8
valid_sources[0x34]	9984	1			T3	2		T4	4		T13	5
valid_sources[0x35]	8089	1			T2	7		T3	3		T4	3
valid_sources[0x36]	8416	1			T2	1		T3	3		T4	7
valid_sources[0x37]	8026	1			T2	1		T4	3		T13	3
valid_sources[0x38]	7337	1			T1	3		T2	1		T4	7
valid_sources[0x39]	7845	1			T2	1		T3	2		T4	6
valid_sources[0x3a]	8308	1			T3	3		T4	1		T13	3
valid_sources[0x3b]	8532	1			T1	1		T2	4		T4	2
valid_sources[0x3c]	9098	1			T2	1		T3	2		T4	2
valid_sources[0x3d]	7961	1			T2	1		T3	7		T4	2
valid_sources[0x3e]	8038	1			T4	5		T13	4		T15	6
valid_sources[0x3f]	8149	1			T3	2		T4	5		T13	14
valid_sources[0x40]	7579	1			T2	1		T3	1		T4	4
valid_sources[0x41]	8076	1			T2	2		T3	3		T13	5
valid_sources[0x42]	8155	1			T2	4		T4	3		T13	4
valid_sources[0x43]	7691	1			T3	2		T4	1		T13	6
valid_sources[0x44]	8301	1			T2	2		T4	4		T13	9
valid_sources[0x45]	11329	1			T2	29		T3	1		T4	5
valid_sources[0x46]	8089	1			T1	1		T3	4		T4	1
valid_sources[0x47]	9225	1			T2	4		T3	8		T4	4
valid_sources[0x48]	9270	1			T2	1		T4	2		T13	6
valid_sources[0x49]	8796	1			T1	2		T2	1		T4	2
valid_sources[0x4a]	8259	1			T2	2		T4	3		T13	9
valid_sources[0x4b]	8616	1			T2	1		T4	2		T13	3
valid_sources[0x4c]	7485	1			T2	4		T3	1		T4	1
valid_sources[0x4d]	7259	1			T1	1		T2	3		T3	8
valid_sources[0x4e]	7851	1			T2	5		T3	2		T4	6
valid_sources[0x4f]	7561	1			T2	1		T3	1		T4	6
valid_sources[0x50]	8912	1			T1	1		T3	3		T4	4
valid_sources[0x51]	8221	1			T3	1		T13	6		T15	2
valid_sources[0x52]	7625	1			T2	29		T3	4		T4	4
valid_sources[0x53]	8441	1			T2	3		T4	5		T13	8
valid_sources[0x54]	8742	1			T1	2		T2	4		T4	3
valid_sources[0x55]	8660	1			T3	6		T4	2		T13	2
valid_sources[0x56]	8241	1			T1	1		T3	2		T4	2
valid_sources[0x57]	8681	1			T2	4		T3	1		T4	2
valid_sources[0x58]	8550	1			T2	1		T3	2		T4	2
valid_sources[0x59]	8319	1			T1	1		T2	2		T4	1
valid_sources[0x5a]	8164	1			T2	1		T4	2		T13	10
valid_sources[0x5b]	8441	1			T3	2		T4	1		T13	6
valid_sources[0x5c]	8697	1			T1	1		T4	5		T13	3
valid_sources[0x5d]	7973	1			T2	1		T3	3		T4	1
valid_sources[0x5e]	9116	1			T2	5		T3	2		T4	2
valid_sources[0x5f]	8290	1			T4	3		T13	13		T15	7
valid_sources[0x60]	7803	1			T1	1		T2	1		T3	1
valid_sources[0x61]	8010	1			T4	6		T13	8		T15	5
valid_sources[0x62]	7662	1			T2	2		T4	1		T13	3
valid_sources[0x63]	8146	1			T1	1		T4	1		T13	10
valid_sources[0x64]	8393	1			T2	35		T4	1		T13	2
valid_sources[0x65]	7696	1			T2	15		T4	1		T13	7
valid_sources[0x66]	6882	1			T2	1		T3	1		T4	1
valid_sources[0x67]	7847	1			T2	6		T3	2		T4	4
valid_sources[0x68]	8358	1			T1	1		T3	9		T4	4
valid_sources[0x69]	8882	1			T2	1		T4	3		T13	5
valid_sources[0x6a]	7838	1			T2	7		T3	1		T4	4
valid_sources[0x6b]	8196	1			T2	2		T3	5		T4	3
valid_sources[0x6c]	8414	1			T1	1		T2	1		T3	1
valid_sources[0x6d]	8645	1			T2	14		T4	5		T13	2
valid_sources[0x6e]	7919	1			T3	1		T4	1		T13	11
valid_sources[0x6f]	8039	1			T3	2		T4	2		T13	4
valid_sources[0x70]	8280	1			T2	2		T3	3		T4	2
valid_sources[0x71]	7209	1			T1	2		T3	1		T4	2
valid_sources[0x72]	9392	1			T2	4		T3	3		T4	4
valid_sources[0x73]	8363	1			T1	3		T2	17		T3	1
valid_sources[0x74]	7327	1			T3	1		T4	3		T13	6
valid_sources[0x75]	7786	1			T1	2		T3	1		T4	1
valid_sources[0x76]	8587	1			T1	1		T2	4		T13	5
valid_sources[0x77]	8161	1			T2	5		T3	2		T4	2
valid_sources[0x78]	8150	1			T2	2		T3	6		T4	3
valid_sources[0x79]	8121	1			T3	3		T4	1		T13	5
valid_sources[0x7a]	8568	1			T2	6		T3	2		T4	3
valid_sources[0x7b]	8416	1			T2	10		T3	2		T4	2
valid_sources[0x7c]	9904	1			T2	1		T4	3		T13	17
valid_sources[0x7d]	7947	1			T2	4		T3	2		T4	2
valid_sources[0x7e]	8380	1			T2	31		T3	3		T4	4
valid_sources[0x7f]	8427	1			T1	1		T2	8		T3	1
valid_sources[0x80]	8169	1			T2	1		T3	7		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29994

1

T1

3

T2

39

T3

16

values[0x0]

all_enables

biggest_size

227284

1

T1

2

T2

42

T3

21

values[0x1]

all_enables

biggest_size

29882

1

T1

1

T2

35

T3

10