Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	375800157	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	375800157	0	0
T1	2089920	34972	0	0
T2	2090424	95620	0	0
T3	1064616	41309	0	0
T4	23010736	532884	0	0
T12	39088	1208	0	0
T13	2270296	59285	0	0
T14	33992	674	0	0
T15	171976	10403	0	0
T16	239344	8039	0	0
T17	546728	11240	0	0
T18	0	266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2089920	2042096	0	0
T2	2090424	2062760	0	0
T3	1064616	1039024	0	0
T4	23010736	22983128	0	0
T12	39088	38304	0	0
T13	2270296	2269568	0	0
T14	33992	30912	0	0
T15	171976	169568	0	0
T16	239344	237888	0	0
T17	546728	536312	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2089920	2042096	0	0
T2	2090424	2062760	0	0
T3	1064616	1039024	0	0
T4	23010736	22983128	0	0
T12	39088	38304	0	0
T13	2270296	2269568	0	0
T14	33992	30912	0	0
T15	171976	169568	0	0
T16	239344	237888	0	0
T17	546728	536312	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2089920	2042096	0	0
T2	2090424	2062760	0	0
T3	1064616	1039024	0	0
T4	23010736	22983128	0	0
T12	39088	38304	0	0
T13	2270296	2269568	0	0
T14	33992	30912	0	0
T15	171976	169568	0	0
T16	239344	237888	0	0
T17	546728	536312	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T12	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	141347193	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	141347193	0	0
T1	37320	14498	0	0
T2	37329	32897	0	0
T3	19011	15904	0	0
T4	410906	208769	0	0
T12	698	302	0	0
T13	40541	24125	0	0
T14	607	260	0	0
T15	3071	2602	0	0
T16	4274	4007	0	0
T17	9763	4425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	94856829	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	94856829	0	0
T1	37320	5491	0	0
T2	37329	21685	0	0
T3	19011	9206	0	0
T4	410906	106519	0	0
T12	698	302	0	0
T13	40541	11660	0	0
T14	607	138	0	0
T15	3071	2601	0	0
T16	4274	2040	0	0
T17	9763	2465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1728208	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1728208	0	0
T1	37320	266	0	0
T2	37329	268	0	0
T3	19011	208	0	0
T4	410906	2437	0	0
T12	698	11	0	0
T13	40541	347	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	43	0	0
T17	9763	57	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3806112	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3806112	0	0
T1	37320	106	0	0
T2	37329	268	0	0
T3	19011	208	0	0
T4	410906	2193	0	0
T12	698	11	0	0
T13	40541	354	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	43	0	0
T17	9763	69	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1681336	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1681336	0	0
T1	37320	322	0	0
T2	37329	791	0	0
T3	19011	233	0	0
T4	410906	4244	0	0
T12	698	9	0	0
T13	40541	405	0	0
T14	607	4	0	0
T15	3071	286	0	0
T16	4274	42	0	0
T17	9763	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3766632	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3766632	0	0
T1	37320	201	0	0
T2	37329	791	0	0
T3	19011	233	0	0
T4	410906	4290	0	0
T12	698	9	0	0
T13	40541	314	0	0
T14	607	4	0	0
T15	3071	286	0	0
T16	4274	42	0	0
T17	9763	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1665768	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1665768	0	0
T1	37320	209	0	0
T2	37329	1396	0	0
T3	19011	208	0	0
T4	410906	4535	0	0
T12	698	8	0	0
T13	40541	447	0	0
T14	607	10	0	0
T15	3071	0	0	0
T16	4274	42	0	0
T17	9763	102	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	2509466	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	2509466	0	0
T1	37320	116	0	0
T2	37329	1396	0	0
T3	19011	208	0	0
T4	410906	4022	0	0
T12	698	8	0	0
T13	40541	321	0	0
T14	607	10	0	0
T15	3071	0	0	0
T16	4274	42	0	0
T17	9763	75	0	0
T18	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1645279	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1645279	0	0
T1	37320	298	0	0
T2	37329	528	0	0
T3	19011	219	0	0
T4	410906	5426	0	0
T12	698	14	0	0
T13	40541	482	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	34	0	0
T17	9763	51	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3261123	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3261123	0	0
T1	37320	127	0	0
T2	37329	528	0	0
T3	19011	219	0	0
T4	410906	5172	0	0
T12	698	14	0	0
T13	40541	477	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	34	0	0
T17	9763	95	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1659346	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1659346	0	0
T1	37320	300	0	0
T2	37329	528	0	0
T3	19011	204	0	0
T4	410906	2424	0	0
T12	698	4	0	0
T13	40541	418	0	0
T14	607	8	0	0
T15	3071	0	0	0
T16	4274	42	0	0
T17	9763	239	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3533439	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3533439	0	0
T1	37320	155	0	0
T2	37329	528	0	0
T3	19011	204	0	0
T4	410906	2026	0	0
T12	698	4	0	0
T13	40541	447	0	0
T14	607	8	0	0
T15	3071	0	0	0
T16	4274	42	0	0
T17	9763	218	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1675053	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1675053	0	0
T1	37320	233	0	0
T2	37329	521	0	0
T3	19011	344	0	0
T4	410906	6480	0	0
T12	698	8	0	0
T13	40541	513	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	44	0	0
T17	9763	54	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3715728	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3715728	0	0
T1	37320	140	0	0
T2	37329	521	0	0
T3	19011	344	0	0
T4	410906	5670	0	0
T12	698	8	0	0
T13	40541	512	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	44	0	0
T17	9763	58	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1756794	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1756794	0	0
T1	37320	488	0	0
T2	37329	694	0	0
T3	19011	450	0	0
T4	410906	6683	0	0
T12	698	13	0	0
T13	40541	477	0	0
T14	607	6	0	0
T15	3071	218	0	0
T16	4274	37	0	0
T17	9763	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3456006	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3456006	0	0
T1	37320	315	0	0
T2	37329	694	0	0
T3	19011	450	0	0
T4	410906	6063	0	0
T12	698	13	0	0
T13	40541	412	0	0
T14	607	6	0	0
T15	3071	218	0	0
T16	4274	37	0	0
T17	9763	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1686826	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1686826	0	0
T1	37320	236	0	0
T2	37329	788	0	0
T3	19011	452	0	0
T4	410906	4065	0	0
T12	698	14	0	0
T13	40541	474	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	46	0	0
T17	9763	43	0	0
T18	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	4347146	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	4347146	0	0
T1	37320	107	0	0
T2	37329	788	0	0
T3	19011	452	0	0
T4	410906	3996	0	0
T12	698	14	0	0
T13	40541	488	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	46	0	0
T17	9763	44	0	0
T18	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1677731	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1677731	0	0
T1	37320	366	0	0
T2	37329	856	0	0
T3	19011	459	0	0
T4	410906	7086	0	0
T12	698	8	0	0
T13	40541	471	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	41	0	0
T17	9763	63	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3577822	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3577822	0	0
T1	37320	175	0	0
T2	37329	856	0	0
T3	19011	459	0	0
T4	410906	5829	0	0
T12	698	8	0	0
T13	40541	357	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	41	0	0
T17	9763	52	0	0
T18	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1674631	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1674631	0	0
T1	37320	283	0	0
T2	37329	580	0	0
T3	19011	514	0	0
T4	410906	2760	0	0
T12	698	8	0	0
T13	40541	613	0	0
T14	607	4	0	0
T15	3071	241	0	0
T16	4274	29	0	0
T17	9763	83	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	2974489	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	2974489	0	0
T1	37320	106	0	0
T2	37329	580	0	0
T3	19011	514	0	0
T4	410906	2373	0	0
T12	698	8	0	0
T13	40541	528	0	0
T14	607	4	0	0
T15	3071	241	0	0
T16	4274	29	0	0
T17	9763	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1707644	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1707644	0	0
T1	37320	378	0	0
T2	37329	1059	0	0
T3	19011	253	0	0
T4	410906	2475	0	0
T12	698	6	0	0
T13	40541	455	0	0
T14	607	5	0	0
T15	3071	282	0	0
T16	4274	39	0	0
T17	9763	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3847180	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3847180	0	0
T1	37320	180	0	0
T2	37329	1059	0	0
T3	19011	253	0	0
T4	410906	2114	0	0
T12	698	6	0	0
T13	40541	455	0	0
T14	607	5	0	0
T15	3071	282	0	0
T16	4274	39	0	0
T17	9763	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1656095	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1656095	0	0
T1	37320	956	0	0
T2	37329	551	0	0
T3	19011	224	0	0
T4	410906	4133	0	0
T12	698	8	0	0
T13	40541	474	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	182	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3230735	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3230735	0	0
T1	37320	585	0	0
T2	37329	551	0	0
T3	19011	224	0	0
T4	410906	3302	0	0
T12	698	8	0	0
T13	40541	458	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	163	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1632061	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1632061	0	0
T1	37320	339	0	0
T2	37329	1097	0	0
T3	19011	227	0	0
T4	410906	5767	0	0
T12	698	12	0	0
T13	40541	380	0	0
T14	607	5	0	0
T15	3071	287	0	0
T16	4274	38	0	0
T17	9763	91	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	2845885	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	2845885	0	0
T1	37320	164	0	0
T2	37329	1097	0	0
T3	19011	227	0	0
T4	410906	5556	0	0
T12	698	12	0	0
T13	40541	467	0	0
T14	607	5	0	0
T15	3071	287	0	0
T16	4274	38	0	0
T17	9763	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1715108	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1715108	0	0
T1	37320	485	0	0
T2	37329	1075	0	0
T3	19011	249	0	0
T4	410906	2383	0	0
T12	698	11	0	0
T13	40541	351	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	39	0	0
T17	9763	56	0	0
T18	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3652336	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3652336	0	0
T1	37320	275	0	0
T2	37329	1075	0	0
T3	19011	249	0	0
T4	410906	2106	0	0
T12	698	11	0	0
T13	40541	374	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	39	0	0
T17	9763	32	0	0
T18	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1664284	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1664284	0	0
T1	37320	262	0	0
T2	37329	544	0	0
T3	19011	528	0	0
T4	410906	3784	0	0
T12	698	12	0	0
T13	40541	398	0	0
T14	607	1	0	0
T15	3071	0	0	0
T16	4274	33	0	0
T17	9763	83	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3421877	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3421877	0	0
T1	37320	152	0	0
T2	37329	544	0	0
T3	19011	527	0	0
T4	410906	3735	0	0
T12	698	12	0	0
T13	40541	401	0	0
T14	607	1	0	0
T15	3071	0	0	0
T16	4274	33	0	0
T17	9763	103	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1707039	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1707039	0	0
T1	37320	744	0	0
T2	37329	499	0	0
T3	19011	178	0	0
T4	410906	2301	0	0
T12	698	15	0	0
T13	40541	432	0	0
T14	607	9	0	0
T15	3071	283	0	0
T16	4274	30	0	0
T17	9763	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3736136	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3736136	0	0
T1	37320	273	0	0
T2	37329	499	0	0
T3	19011	178	0	0
T4	410906	2085	0	0
T12	698	15	0	0
T13	40541	477	0	0
T14	607	9	0	0
T15	3071	283	0	0
T16	4274	30	0	0
T17	9763	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1702482	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1702482	0	0
T1	37320	262	0	0
T2	37329	527	0	0
T3	19011	236	0	0
T4	410906	4996	0	0
T12	698	8	0	0
T13	40541	493	0	0
T14	607	2	0	0
T15	3071	253	0	0
T16	4274	36	0	0
T17	9763	117	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3033377	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3033377	0	0
T1	37320	145	0	0
T2	37329	527	0	0
T3	19011	236	0	0
T4	410906	4151	0	0
T12	698	8	0	0
T13	40541	444	0	0
T14	607	2	0	0
T15	3071	253	0	0
T16	4274	36	0	0
T17	9763	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1719677	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1719677	0	0
T1	37320	263	0	0
T2	37329	827	0	0
T3	19011	206	0	0
T4	410906	3896	0	0
T12	698	13	0	0
T13	40541	407	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	27	0	0
T17	9763	62	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3572762	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3572762	0	0
T1	37320	118	0	0
T2	37329	827	0	0
T3	19011	206	0	0
T4	410906	3594	0	0
T12	698	13	0	0
T13	40541	446	0	0
T14	607	5	0	0
T15	3071	0	0	0
T16	4274	27	0	0
T17	9763	63	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1682017	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1682017	0	0
T1	37320	329	0	0
T2	37329	1041	0	0
T3	19011	215	0	0
T4	410906	2056	0	0
T12	698	10	0	0
T13	40541	416	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	122	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3643719	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3643719	0	0
T1	37320	211	0	0
T2	37329	1041	0	0
T3	19011	215	0	0
T4	410906	2026	0	0
T12	698	10	0	0
T13	40541	436	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	133	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1690444	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1690444	0	0
T1	37320	340	0	0
T2	37329	308	0	0
T3	19011	227	0	0
T4	410906	8125	0	0
T12	698	12	0	0
T13	40541	483	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	80	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3112427	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3112427	0	0
T1	37320	202	0	0
T2	37329	308	0	0
T3	19011	227	0	0
T4	410906	6842	0	0
T12	698	12	0	0
T13	40541	499	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	31	0	0
T17	9763	39	0	0
T18	0	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1710144	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1710144	0	0
T1	37320	275	0	0
T2	37329	992	0	0
T3	19011	487	0	0
T4	410906	4979	0	0
T12	698	18	0	0
T13	40541	361	0	0
T14	607	7	0	0
T15	3071	287	0	0
T16	4274	47	0	0
T17	9763	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3468090	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3468090	0	0
T1	37320	152	0	0
T2	37329	992	0	0
T3	19011	487	0	0
T4	410906	4293	0	0
T12	698	18	0	0
T13	40541	377	0	0
T14	607	7	0	0
T15	3071	287	0	0
T16	4274	47	0	0
T17	9763	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1704940	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1704940	0	0
T1	37320	260	0	0
T2	37329	553	0	0
T3	19011	223	0	0
T4	410906	5854	0	0
T12	698	13	0	0
T13	40541	439	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	36	0	0
T17	9763	43	0	0
T18	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3679051	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3679051	0	0
T1	37320	158	0	0
T2	37329	553	0	0
T3	19011	223	0	0
T4	410906	5378	0	0
T12	698	13	0	0
T13	40541	422	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	36	0	0
T17	9763	30	0	0
T18	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1671854	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1671854	0	0
T1	37320	320	0	0
T2	37329	767	0	0
T3	19011	270	0	0
T4	410906	2444	0	0
T12	698	10	0	0
T13	40541	430	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	33	0	0
T17	9763	50	0	0
T18	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3144018	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3144018	0	0
T1	37320	199	0	0
T2	37329	767	0	0
T3	19011	270	0	0
T4	410906	2291	0	0
T12	698	10	0	0
T13	40541	456	0	0
T14	607	3	0	0
T15	3071	0	0	0
T16	4274	33	0	0
T17	9763	50	0	0
T18	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1680006	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1680006	0	0
T1	37320	576	0	0
T2	37329	842	0	0
T3	19011	218	0	0
T4	410906	4781	0	0
T12	698	13	0	0
T13	40541	348	0	0
T14	607	5	0	0
T15	3071	463	0	0
T16	4274	32	0	0
T17	9763	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3544424	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3544424	0	0
T1	37320	371	0	0
T2	37329	842	0	0
T3	19011	218	0	0
T4	410906	4068	0	0
T12	698	13	0	0
T13	40541	383	0	0
T14	607	5	0	0
T15	3071	463	0	0
T16	4274	32	0	0
T17	9763	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1670608	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1670608	0	0
T1	37320	279	0	0
T2	37329	1501	0	0
T3	19011	228	0	0
T4	410906	2176	0	0
T12	698	13	0	0
T13	40541	301	0	0
T14	607	10	0	0
T15	3071	0	0	0
T16	4274	34	0	0
T17	9763	132	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3912997	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3912997	0	0
T1	37320	168	0	0
T2	37329	1501	0	0
T3	19011	227	0	0
T4	410906	2097	0	0
T12	698	13	0	0
T13	40541	334	0	0
T14	607	10	0	0
T15	3071	0	0	0
T16	4274	34	0	0
T17	9763	169	0	0
T18	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1688553	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1688553	0	0
T1	37320	298	0	0
T2	37329	542	0	0
T3	19011	238	0	0
T4	410906	4176	0	0
T12	698	19	0	0
T13	40541	455	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	39	0	0
T17	9763	64	0	0
T18	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3772504	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3772504	0	0
T1	37320	141	0	0
T2	37329	542	0	0
T3	19011	238	0	0
T4	410906	3771	0	0
T12	698	19	0	0
T13	40541	532	0	0
T14	607	4	0	0
T15	3071	0	0	0
T16	4274	39	0	0
T17	9763	69	0	0
T18	0	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	1688475	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	1688475	0	0
T1	37320	385	0	0
T2	37329	844	0	0
T3	19011	603	0	0
T4	410906	4560	0	0
T12	698	12	0	0
T13	40541	570	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	40	0	0
T17	9763	62	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	340162948	3488251	0	0
DepthKnown_A	340162948	340043658	0	0
RvalidKnown_A	340162948	340043658	0	0
WreadyKnown_A	340162948	340043658	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	3488251	0	0
T1	37320	189	0	0
T2	37329	844	0	0
T3	19011	602	0	0
T4	410906	3527	0	0
T12	698	12	0	0
T13	40541	489	0	0
T14	607	6	0	0
T15	3071	0	0	0
T16	4274	40	0	0
T17	9763	101	0	0
T18	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	340162948	340043658	0	0
T1	37320	36466	0	0
T2	37329	36835	0	0
T3	19011	18554	0	0
T4	410906	410413	0	0
T12	698	684	0	0
T13	40541	40528	0	0
T14	607	552	0	0
T15	3071	3028	0	0
T16	4274	4248	0	0
T17	9763	9577	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0