Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1718756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

271240

1

T1

103

T2

121

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	670650	1			T1	276		T2	323		T3	40
values[0x0]	646980	1			T1	264		T2	313		T3	11
values[0x1]	672366	1			T1	308		T2	347		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1333543	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

656453

1

T1

270

T2

319

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8302	1			T3	1		T16	15		T14	152
valid_sources[0x01]	7786	1			T2	19		T3	1		T16	8
valid_sources[0x02]	7897	1			T2	13		T16	7		T14	76
valid_sources[0x03]	8103	1			T3	1		T16	6		T14	8
valid_sources[0x04]	7996	1			T16	11		T14	26		T15	6
valid_sources[0x05]	7844	1			T2	15		T16	10		T14	3
valid_sources[0x06]	7759	1			T16	9		T11	1		T14	1
valid_sources[0x07]	8661	1			T2	2		T3	1		T16	10
valid_sources[0x08]	7542	1			T1	1		T2	12		T3	1
valid_sources[0x09]	7378	1			T2	1		T3	1		T16	5
valid_sources[0x0a]	7671	1			T1	15		T3	1		T16	5
valid_sources[0x0b]	7465	1			T2	7		T16	24		T11	2
valid_sources[0x0c]	8141	1			T1	35		T2	14		T16	1
valid_sources[0x0d]	7897	1			T3	1		T16	7		T11	1
valid_sources[0x0e]	6903	1			T1	50		T2	16		T16	16
valid_sources[0x0f]	7219	1			T16	13		T11	2		T14	1
valid_sources[0x10]	8695	1			T16	15		T14	7		T15	11
valid_sources[0x11]	7814	1			T2	5		T3	1		T16	14
valid_sources[0x12]	7698	1			T16	14		T15	5		T18	2
valid_sources[0x13]	7501	1			T2	9		T16	1		T14	2
valid_sources[0x14]	9358	1			T2	8		T16	12		T15	2
valid_sources[0x15]	7606	1			T16	9		T11	1		T14	149
valid_sources[0x16]	7374	1			T2	17		T16	14		T14	6
valid_sources[0x17]	7423	1			T2	8		T16	5		T14	27
valid_sources[0x18]	7867	1			T16	13		T11	1		T14	24
valid_sources[0x19]	7328	1			T16	12		T15	8		T18	3
valid_sources[0x1a]	7791	1			T3	2		T16	11		T15	5
valid_sources[0x1b]	8150	1			T1	10		T3	4		T16	4
valid_sources[0x1c]	7204	1			T2	11		T3	2		T16	30
valid_sources[0x1d]	8093	1			T2	30		T16	6		T14	32
valid_sources[0x1e]	7719	1			T16	19		T15	2		T18	9
valid_sources[0x1f]	7922	1			T3	1		T16	9		T11	1
valid_sources[0x20]	8035	1			T1	21		T3	1		T16	9
valid_sources[0x21]	7717	1			T16	10		T11	1		T15	3
valid_sources[0x22]	7072	1			T2	12		T16	16		T14	1
valid_sources[0x23]	8431	1			T2	15		T16	10		T14	20
valid_sources[0x24]	8166	1			T2	18		T16	5		T14	17
valid_sources[0x25]	7401	1			T16	4		T15	4		T12	3
valid_sources[0x26]	7947	1			T16	11		T15	1		T18	2
valid_sources[0x27]	7325	1			T2	31		T3	1		T16	21
valid_sources[0x28]	8002	1			T1	2		T2	1		T16	12
valid_sources[0x29]	7189	1			T1	103		T2	10		T16	5
valid_sources[0x2a]	7902	1			T16	9		T11	1		T14	4
valid_sources[0x2b]	7970	1			T3	1		T16	3		T15	10
valid_sources[0x2c]	7819	1			T1	3		T3	1		T16	12
valid_sources[0x2d]	8530	1			T16	11		T11	3		T15	4
valid_sources[0x2e]	7722	1			T2	1		T3	1		T16	10
valid_sources[0x2f]	7993	1			T16	11		T11	1		T15	10
valid_sources[0x30]	7668	1			T2	14		T16	19		T14	23
valid_sources[0x31]	7765	1			T16	17		T14	1		T15	2
valid_sources[0x32]	7462	1			T3	1		T16	5		T14	12
valid_sources[0x33]	7526	1			T16	10		T11	1		T14	3
valid_sources[0x34]	7710	1			T3	1		T16	11		T11	1
valid_sources[0x35]	7704	1			T16	16		T14	36		T15	4
valid_sources[0x36]	8078	1			T16	8		T11	2		T15	13
valid_sources[0x37]	7324	1			T2	3		T16	11		T11	1
valid_sources[0x38]	9101	1			T16	11		T14	1		T15	6
valid_sources[0x39]	8978	1			T2	8		T3	2		T16	8
valid_sources[0x3a]	7323	1			T3	2		T16	14		T11	1
valid_sources[0x3b]	8030	1			T16	7		T14	2		T15	4
valid_sources[0x3c]	7466	1			T3	1		T16	14		T15	4
valid_sources[0x3d]	7576	1			T3	1		T16	14		T14	62
valid_sources[0x3e]	7501	1			T2	1		T16	5		T11	2
valid_sources[0x3f]	9251	1			T3	1		T16	12		T14	60
valid_sources[0x40]	7376	1			T3	1		T16	11		T15	6
valid_sources[0x41]	7551	1			T16	7		T15	8		T18	2
valid_sources[0x42]	7284	1			T1	12		T2	6		T16	14
valid_sources[0x43]	8676	1			T2	41		T16	9		T14	62
valid_sources[0x44]	8242	1			T16	11		T15	16		T18	2
valid_sources[0x45]	8140	1			T2	1		T3	1		T16	4
valid_sources[0x46]	7478	1			T2	11		T16	3		T14	57
valid_sources[0x47]	8578	1			T2	3		T16	6		T11	1
valid_sources[0x48]	7513	1			T1	9		T2	15		T16	8
valid_sources[0x49]	7544	1			T16	8		T11	1		T14	12
valid_sources[0x4a]	7672	1			T2	8		T16	17		T11	1
valid_sources[0x4b]	7753	1			T16	13		T11	1		T15	3
valid_sources[0x4c]	7260	1			T16	15		T11	2		T14	69
valid_sources[0x4d]	7698	1			T2	4		T16	12		T15	6
valid_sources[0x4e]	8195	1			T1	27		T2	3		T3	1
valid_sources[0x4f]	7909	1			T3	1		T16	14		T15	8
valid_sources[0x50]	7797	1			T16	15		T11	1		T14	5
valid_sources[0x51]	7490	1			T16	7		T14	10		T15	9
valid_sources[0x52]	7645	1			T3	1		T16	13		T15	7
valid_sources[0x53]	7484	1			T2	18		T16	17		T11	1
valid_sources[0x54]	7218	1			T2	17		T16	8		T14	26
valid_sources[0x55]	8167	1			T16	14		T15	8		T12	6
valid_sources[0x56]	8272	1			T2	5		T16	5		T15	6
valid_sources[0x57]	7588	1			T16	14		T14	1		T15	3
valid_sources[0x58]	8427	1			T16	7		T11	1		T14	70
valid_sources[0x59]	7529	1			T1	4		T16	6		T11	1
valid_sources[0x5a]	7895	1			T16	13		T15	4		T18	3
valid_sources[0x5b]	8050	1			T16	20		T14	1		T15	7
valid_sources[0x5c]	7347	1			T3	1		T16	21		T14	2
valid_sources[0x5d]	7203	1			T3	3		T16	14		T15	6
valid_sources[0x5e]	7261	1			T1	2		T16	11		T14	1
valid_sources[0x5f]	8023	1			T2	4		T16	8		T14	2
valid_sources[0x60]	7656	1			T1	24		T16	7		T14	76
valid_sources[0x61]	8225	1			T1	19		T2	33		T16	17
valid_sources[0x62]	8138	1			T3	1		T16	4		T11	1
valid_sources[0x63]	8007	1			T2	22		T3	2		T16	22
valid_sources[0x64]	7556	1			T2	9		T3	1		T16	12
valid_sources[0x65]	8375	1			T3	1		T16	7		T15	12
valid_sources[0x66]	7962	1			T3	1		T16	18		T15	8
valid_sources[0x67]	7478	1			T16	21		T11	3		T14	7
valid_sources[0x68]	8063	1			T3	1		T16	12		T15	2
valid_sources[0x69]	8356	1			T16	16		T15	8		T12	2
valid_sources[0x6a]	7355	1			T16	14		T14	21		T15	4
valid_sources[0x6b]	6947	1			T2	2		T16	11		T11	2
valid_sources[0x6c]	7891	1			T3	1		T16	9		T15	7
valid_sources[0x6d]	8445	1			T16	8		T14	17		T18	1
valid_sources[0x6e]	7408	1			T1	5		T16	15		T14	2
valid_sources[0x6f]	7896	1			T2	1		T16	12		T11	1
valid_sources[0x70]	7692	1			T3	1		T16	8		T15	9
valid_sources[0x71]	7397	1			T3	1		T16	14		T14	1
valid_sources[0x72]	8048	1			T2	8		T16	12		T11	1
valid_sources[0x73]	7657	1			T3	1		T16	16		T11	1
valid_sources[0x74]	7452	1			T16	7		T15	10		T19	71
valid_sources[0x75]	7609	1			T16	11		T15	8		T18	2
valid_sources[0x76]	7854	1			T2	49		T16	12		T14	5
valid_sources[0x77]	7051	1			T3	1		T16	7		T11	1
valid_sources[0x78]	7525	1			T16	19		T14	4		T15	3
valid_sources[0x79]	7402	1			T2	4		T16	3		T14	14
valid_sources[0x7a]	8046	1			T16	5		T14	72		T15	3
valid_sources[0x7b]	7964	1			T2	7		T16	5		T11	2
valid_sources[0x7c]	7673	1			T3	1		T16	22		T11	1
valid_sources[0x7d]	7366	1			T2	4		T3	1		T16	15
valid_sources[0x7e]	8300	1			T16	13		T14	19		T15	6
valid_sources[0x7f]	7686	1			T16	3		T15	5		T18	2
valid_sources[0x80]	7355	1			T16	11		T11	1		T15	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28298

1

T1

16

T2

12

T3

3

values[0x0]

all_enables

biggest_size

214782

1

T1

77

T2

97

T3

7

values[0x1]

all_enables

biggest_size

28160

1

T1

10

T2

12

T3

4