Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	349551470	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349551470	0	0
T1	5760944	1435329	0	0
T2	27019440	481367	0	0
T3	2765784	64751	0	0
T11	5951400	163346	0	0
T12	0	229	0	0
T14	6402368	160779	0	0
T15	196392	6577	0	0
T16	301336	13553	0	0
T17	22568	504	0	0
T18	9856224	153642	0	0
T19	192696	8601	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5760944	5760832	0	0
T2	27019440	27016192	0	0
T3	2765784	2763264	0	0
T11	5951400	5946864	0	0
T14	6402368	6313216	0	0
T15	196392	194208	0	0
T16	301336	300608	0	0
T17	22568	21224	0	0
T18	9856224	9849280	0	0
T19	192696	192248	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5760944	5760832	0	0
T2	27019440	27016192	0	0
T3	2765784	2763264	0	0
T11	5951400	5946864	0	0
T14	6402368	6313216	0	0
T15	196392	194208	0	0
T16	301336	300608	0	0
T17	22568	21224	0	0
T18	9856224	9849280	0	0
T19	192696	192248	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5760944	5760832	0	0
T2	27019440	27016192	0	0
T3	2765784	2763264	0	0
T11	5951400	5946864	0	0
T14	6402368	6313216	0	0
T15	196392	194208	0	0
T16	301336	300608	0	0
T17	22568	21224	0	0
T18	9856224	9849280	0	0
T19	192696	192248	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T11	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	125742468	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	125742468	0	0
T1	102874	588156	0	0
T2	482490	470292	0	0
T3	49389	25755	0	0
T11	106275	104426	0	0
T14	114328	67917	0	0
T15	3507	3243	0	0
T16	5381	5266	0	0
T17	403	192	0	0
T18	176004	64887	0	0
T19	3441	3342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	92091565	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	92091565	0	0
T1	102874	283873	0	0
T2	482490	3430	0	0
T3	49389	20659	0	0
T11	106275	29448	0	0
T14	114328	32073	0	0
T15	3507	1656	0	0
T16	5381	2763	0	0
T17	403	104	0	0
T18	176004	24841	0	0
T19	3441	1753	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1493291	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1493291	0	0
T1	102874	7598	0	0
T2	482490	172	0	0
T3	49389	326	0	0
T11	106275	24	0	0
T14	114328	938	0	0
T15	3507	22	0	0
T16	5381	103	0	0
T17	403	6	0	0
T18	176004	1426	0	0
T19	3441	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2991981	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2991981	0	0
T1	102874	8939	0	0
T2	482490	36	0	0
T3	49389	363	0	0
T11	106275	1350	0	0
T14	114328	1080	0	0
T15	3507	22	0	0
T16	5381	103	0	0
T17	403	6	0	0
T18	176004	812	0	0
T19	3441	61	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1530425	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1530425	0	0
T1	102874	10827	0	0
T2	482490	198	0	0
T3	49389	386	0	0
T11	106275	20	0	0
T14	114328	1381	0	0
T15	3507	24	0	0
T16	5381	113	0	0
T17	403	3	0	0
T18	176004	1094	0	0
T19	3441	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2906164	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2906164	0	0
T1	102874	9301	0	0
T2	482490	38	0	0
T3	49389	380	0	0
T11	106275	643	0	0
T14	114328	1473	0	0
T15	3507	24	0	0
T16	5381	113	0	0
T17	403	3	0	0
T18	176004	686	0	0
T19	3441	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1498552	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1498552	0	0
T1	102874	11931	0	0
T2	482490	206	0	0
T3	49389	238	0	0
T11	106275	0	0	0
T12	0	138	0	0
T14	114328	1064	0	0
T15	3507	30	0	0
T16	5381	89	0	0
T17	403	5	0	0
T18	176004	1181	0	0
T19	3441	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3553700	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3553700	0	0
T1	102874	10801	0	0
T2	482490	130	0	0
T3	49389	303	0	0
T11	106275	0	0	0
T12	0	91	0	0
T14	114328	1035	0	0
T15	3507	30	0	0
T16	5381	89	0	0
T17	403	5	0	0
T18	176004	637	0	0
T19	3441	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1482871	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1482871	0	0
T1	102874	15238	0	0
T2	482490	159	0	0
T3	49389	391	0	0
T11	106275	36	0	0
T14	114328	1107	0	0
T15	3507	25	0	0
T16	5381	85	0	0
T17	403	6	0	0
T18	176004	1199	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	4081731	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	4081731	0	0
T1	102874	17729	0	0
T2	482490	35	0	0
T3	49389	466	0	0
T11	106275	1265	0	0
T14	114328	1188	0	0
T15	3507	25	0	0
T16	5381	85	0	0
T17	403	6	0	0
T18	176004	578	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1510296	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1510296	0	0
T1	102874	11241	0	0
T2	482490	142	0	0
T3	49389	414	0	0
T11	106275	13	0	0
T14	114328	1050	0	0
T15	3507	41	0	0
T16	5381	114	0	0
T17	403	9	0	0
T18	176004	1670	0	0
T19	3441	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3048677	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3048677	0	0
T1	102874	11128	0	0
T2	482490	35	0	0
T3	49389	366	0	0
T11	106275	139	0	0
T14	114328	1069	0	0
T15	3507	41	0	0
T16	5381	114	0	0
T17	403	9	0	0
T18	176004	885	0	0
T19	3441	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1492002	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1492002	0	0
T1	102874	15724	0	0
T2	482490	145	0	0
T3	49389	234	0	0
T11	106275	37	0	0
T14	114328	956	0	0
T15	3507	28	0	0
T16	5381	119	0	0
T17	403	7	0	0
T18	176004	1296	0	0
T19	3441	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2778617	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2778617	0	0
T1	102874	14188	0	0
T2	482490	40	0	0
T3	49389	311	0	0
T11	106275	3468	0	0
T14	114328	1089	0	0
T15	3507	28	0	0
T16	5381	119	0	0
T17	403	7	0	0
T18	176004	693	0	0
T19	3441	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1447198	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1447198	0	0
T1	102874	6173	0	0
T2	482490	199	0	0
T3	49389	270	0	0
T11	106275	13	0	0
T14	114328	1007	0	0
T15	3507	30	0	0
T16	5381	113	0	0
T17	403	4	0	0
T18	176004	1330	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3513750	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3513750	0	0
T1	102874	5177	0	0
T2	482490	261	0	0
T3	49389	397	0	0
T11	106275	972	0	0
T14	114328	1072	0	0
T15	3507	30	0	0
T16	5381	113	0	0
T17	403	4	0	0
T18	176004	765	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1502597	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1502597	0	0
T1	102874	8988	0	0
T2	482490	82	0	0
T3	49389	313	0	0
T11	106275	18	0	0
T14	114328	1079	0	0
T15	3507	37	0	0
T16	5381	112	0	0
T17	403	5	0	0
T18	176004	1424	0	0
T19	3441	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	4158242	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	4158242	0	0
T1	102874	7294	0	0
T2	482490	26	0	0
T3	49389	239	0	0
T11	106275	1402	0	0
T14	114328	1171	0	0
T15	3507	37	0	0
T16	5381	112	0	0
T17	403	5	0	0
T18	176004	649	0	0
T19	3441	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1540257	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1540257	0	0
T1	102874	8164	0	0
T2	482490	190	0	0
T3	49389	264	0	0
T11	106275	16	0	0
T14	114328	1094	0	0
T15	3507	29	0	0
T16	5381	111	0	0
T17	403	7	0	0
T18	176004	1335	0	0
T19	3441	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	4426551	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	4426551	0	0
T1	102874	10227	0	0
T2	482490	839	0	0
T3	49389	305	0	0
T11	106275	968	0	0
T14	114328	1216	0	0
T15	3507	29	0	0
T16	5381	111	0	0
T17	403	7	0	0
T18	176004	719	0	0
T19	3441	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1403206	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1403206	0	0
T1	102874	9464	0	0
T2	482490	101	0	0
T3	49389	370	0	0
T11	106275	22	0	0
T14	114328	1034	0	0
T15	3507	32	0	0
T16	5381	99	0	0
T17	403	3	0	0
T18	176004	1392	0	0
T19	3441	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2854551	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2854551	0	0
T1	102874	9802	0	0
T2	482490	29	0	0
T3	49389	388	0	0
T11	106275	1690	0	0
T14	114328	1166	0	0
T15	3507	32	0	0
T16	5381	99	0	0
T17	403	3	0	0
T18	176004	745	0	0
T19	3441	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1486282	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1486282	0	0
T1	102874	7723	0	0
T2	482490	124	0	0
T3	49389	328	0	0
T11	106275	12	0	0
T14	114328	1607	0	0
T15	3507	23	0	0
T16	5381	111	0	0
T17	403	3	0	0
T18	176004	1397	0	0
T19	3441	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3228904	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3228904	0	0
T1	102874	6532	0	0
T2	482490	27	0	0
T3	49389	235	0	0
T11	106275	2953	0	0
T14	114328	1497	0	0
T15	3507	23	0	0
T16	5381	111	0	0
T17	403	3	0	0
T18	176004	830	0	0
T19	3441	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1504194	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1504194	0	0
T1	102874	11987	0	0
T2	482490	171	0	0
T3	49389	405	0	0
T11	106275	23	0	0
T14	114328	1146	0	0
T15	3507	26	0	0
T16	5381	85	0	0
T17	403	1	0	0
T18	176004	3127	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2997563	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2997563	0	0
T1	102874	12133	0	0
T2	482490	41	0	0
T3	49389	379	0	0
T11	106275	2156	0	0
T14	114328	1312	0	0
T15	3507	26	0	0
T16	5381	85	0	0
T17	403	1	0	0
T18	176004	1641	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1476384	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1476384	0	0
T1	102874	9936	0	0
T2	482490	135	0	0
T3	49389	362	0	0
T11	106275	44	0	0
T14	114328	976	0	0
T15	3507	35	0	0
T16	5381	86	0	0
T17	403	1	0	0
T18	176004	1174	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3046946	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3046946	0	0
T1	102874	11402	0	0
T2	482490	39	0	0
T3	49389	358	0	0
T11	106275	945	0	0
T14	114328	1207	0	0
T15	3507	35	0	0
T16	5381	86	0	0
T17	403	1	0	0
T18	176004	627	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1577171	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1577171	0	0
T1	102874	11103	0	0
T2	482490	191	0	0
T3	49389	348	0	0
T11	106275	24	0	0
T14	114328	1326	0	0
T15	3507	32	0	0
T16	5381	109	0	0
T17	403	1	0	0
T18	176004	1224	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	4077633	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	4077633	0	0
T1	102874	14036	0	0
T2	482490	43	0	0
T3	49389	434	0	0
T11	106275	363	0	0
T14	114328	1305	0	0
T15	3507	32	0	0
T16	5381	109	0	0
T17	403	1	0	0
T18	176004	779	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1516985	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1516985	0	0
T1	102874	8720	0	0
T2	482490	125	0	0
T3	49389	326	0	0
T11	106275	15	0	0
T14	114328	1518	0	0
T15	3507	29	0	0
T16	5381	105	0	0
T17	403	3	0	0
T18	176004	1660	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	4094629	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	4094629	0	0
T1	102874	11472	0	0
T2	482490	84	0	0
T3	49389	344	0	0
T11	106275	3	0	0
T14	114328	1288	0	0
T15	3507	29	0	0
T16	5381	105	0	0
T17	403	3	0	0
T18	176004	753	0	0
T19	3441	66	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1521399	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1521399	0	0
T1	102874	9975	0	0
T2	482490	144	0	0
T3	49389	415	0	0
T11	106275	26	0	0
T14	114328	916	0	0
T15	3507	37	0	0
T16	5381	92	0	0
T17	403	4	0	0
T18	176004	1447	0	0
T19	3441	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2886702	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2886702	0	0
T1	102874	9642	0	0
T2	482490	31	0	0
T3	49389	344	0	0
T11	106275	961	0	0
T14	114328	1076	0	0
T15	3507	37	0	0
T16	5381	92	0	0
T17	403	4	0	0
T18	176004	753	0	0
T19	3441	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1525578	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1525578	0	0
T1	102874	7936	0	0
T2	482490	112	0	0
T3	49389	388	0	0
T11	106275	11	0	0
T14	114328	1044	0	0
T15	3507	33	0	0
T16	5381	97	0	0
T17	403	3	0	0
T18	176004	2962	0	0
T19	3441	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2881027	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2881027	0	0
T1	102874	9066	0	0
T2	482490	32	0	0
T3	49389	354	0	0
T11	106275	548	0	0
T14	114328	1040	0	0
T15	3507	33	0	0
T16	5381	97	0	0
T17	403	3	0	0
T18	176004	1444	0	0
T19	3441	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1447057	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1447057	0	0
T1	102874	11383	0	0
T2	482490	120	0	0
T3	49389	295	0	0
T11	106275	7	0	0
T14	114328	1057	0	0
T15	3507	28	0	0
T16	5381	126	0	0
T17	403	5	0	0
T18	176004	1447	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3508082	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3508082	0	0
T1	102874	11817	0	0
T2	482490	895	0	0
T3	49389	360	0	0
T11	106275	93	0	0
T14	114328	1075	0	0
T15	3507	28	0	0
T16	5381	126	0	0
T17	403	5	0	0
T18	176004	647	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1509459	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1509459	0	0
T1	102874	11709	0	0
T2	482490	200	0	0
T3	49389	297	0	0
T11	106275	12	0	0
T14	114328	1267	0	0
T15	3507	27	0	0
T16	5381	89	0	0
T17	403	3	0	0
T18	176004	1591	0	0
T19	3441	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3153014	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3153014	0	0
T1	102874	10986	0	0
T2	482490	38	0	0
T3	49389	207	0	0
T11	106275	708	0	0
T14	114328	1095	0	0
T15	3507	27	0	0
T16	5381	89	0	0
T17	403	3	0	0
T18	176004	748	0	0
T19	3441	70	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1527493	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1527493	0	0
T1	102874	9389	0	0
T2	482490	110	0	0
T3	49389	249	0	0
T11	106275	27	0	0
T14	114328	1253	0	0
T15	3507	24	0	0
T16	5381	106	0	0
T17	403	1	0	0
T18	176004	1327	0	0
T19	3441	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3539781	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3539781	0	0
T1	102874	7703	0	0
T2	482490	28	0	0
T3	49389	201	0	0
T11	106275	1125	0	0
T14	114328	1232	0	0
T15	3507	24	0	0
T16	5381	106	0	0
T17	403	1	0	0
T18	176004	791	0	0
T19	3441	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1476365	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1476365	0	0
T1	102874	12594	0	0
T2	482490	145	0	0
T3	49389	302	0	0
T11	106275	22	0	0
T14	114328	1082	0	0
T15	3507	27	0	0
T16	5381	99	0	0
T17	403	2	0	0
T18	176004	1424	0	0
T19	3441	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3893845	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3893845	0	0
T1	102874	11455	0	0
T2	482490	40	0	0
T3	49389	306	0	0
T11	106275	1860	0	0
T14	114328	1125	0	0
T15	3507	27	0	0
T16	5381	99	0	0
T17	403	2	0	0
T18	176004	756	0	0
T19	3441	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1512487	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1512487	0	0
T1	102874	11634	0	0
T2	482490	185	0	0
T3	49389	324	0	0
T11	106275	9	0	0
T14	114328	872	0	0
T15	3507	38	0	0
T16	5381	89	0	0
T17	403	4	0	0
T18	176004	980	0	0
T19	3441	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2862981	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2862981	0	0
T1	102874	10555	0	0
T2	482490	61	0	0
T3	49389	339	0	0
T11	106275	835	0	0
T14	114328	1021	0	0
T15	3507	38	0	0
T16	5381	89	0	0
T17	403	4	0	0
T18	176004	621	0	0
T19	3441	63	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1482734	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1482734	0	0
T1	102874	11399	0	0
T2	482490	205	0	0
T3	49389	243	0	0
T11	106275	26	0	0
T14	114328	901	0	0
T15	3507	39	0	0
T16	5381	96	0	0
T17	403	3	0	0
T18	176004	3278	0	0
T19	3441	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3063133	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3063133	0	0
T1	102874	11241	0	0
T2	482490	155	0	0
T3	49389	244	0	0
T11	106275	887	0	0
T14	114328	850	0	0
T15	3507	39	0	0
T16	5381	96	0	0
T17	403	3	0	0
T18	176004	1421	0	0
T19	3441	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1527720	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1527720	0	0
T1	102874	12124	0	0
T2	482490	131	0	0
T3	49389	481	0	0
T11	106275	14	0	0
T14	114328	1025	0	0
T15	3507	34	0	0
T16	5381	95	0	0
T17	403	4	0	0
T18	176004	1346	0	0
T19	3441	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3386421	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3386421	0	0
T1	102874	14645	0	0
T2	482490	330	0	0
T3	49389	486	0	0
T11	106275	461	0	0
T14	114328	1151	0	0
T15	3507	34	0	0
T16	5381	95	0	0
T17	403	4	0	0
T18	176004	675	0	0
T19	3441	73	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1484799	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1484799	0	0
T1	102874	8754	0	0
T2	482490	198	0	0
T3	49389	388	0	0
T11	106275	1	0	0
T14	114328	1166	0	0
T15	3507	34	0	0
T16	5381	113	0	0
T17	403	5	0	0
T18	176004	1361	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	2963535	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	2963535	0	0
T1	102874	7427	0	0
T2	482490	46	0	0
T3	49389	399	0	0
T11	106275	1	0	0
T14	114328	1112	0	0
T15	3507	34	0	0
T16	5381	113	0	0
T17	403	5	0	0
T18	176004	868	0	0
T19	3441	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1527954	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1527954	0	0
T1	102874	8357	0	0
T2	482490	137	0	0
T3	49389	287	0	0
T11	106275	17	0	0
T14	114328	969	0	0
T15	3507	38	0	0
T16	5381	108	0	0
T17	403	4	0	0
T18	176004	1350	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3485066	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3485066	0	0
T1	102874	7468	0	0
T2	482490	29	0	0
T3	49389	334	0	0
T11	106275	2125	0	0
T14	114328	1035	0	0
T15	3507	38	0	0
T16	5381	108	0	0
T17	403	4	0	0
T18	176004	692	0	0
T19	3441	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	1547641	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	1547641	0	0
T1	102874	9356	0	0
T2	482490	189	0	0
T3	49389	395	0	0
T11	106275	27	0	0
T14	114328	966	0	0
T15	3507	37	0	0
T16	5381	98	0	0
T17	403	2	0	0
T18	176004	1448	0	0
T19	3441	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	316887722	3781814	0	0
DepthKnown_A	316887722	316768878	0	0
RvalidKnown_A	316887722	316768878	0	0
WreadyKnown_A	316887722	316768878	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	3781814	0	0
T1	102874	11707	0	0
T2	482490	41	0	0
T3	49389	456	0	0
T11	106275	1035	0	0
T14	114328	1008	0	0
T15	3507	37	0	0
T16	5381	98	0	0
T17	403	2	0	0
T18	176004	809	0	0
T19	3441	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	316887722	316768878	0	0
T1	102874	102872	0	0
T2	482490	482432	0	0
T3	49389	49344	0	0
T11	106275	106194	0	0
T14	114328	112736	0	0
T15	3507	3468	0	0
T16	5381	5368	0	0
T17	403	379	0	0
T18	176004	175880	0	0
T19	3441	3433	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0