Group : tl_agent_pkg::pending_req_on_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::pending_req_on_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

28 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.adc_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwm_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 0 2 100.00 100 1 1 0


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1075 1 T4 1 T6 1 T24 14
values[0x1] 18 1 T66 2 T156 1 T237 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1081 1 T4 1 T6 1 T24 14
values[0x1] 12 1 T82 1 T238 1 T212 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1074 1 T4 1 T6 1 T24 14
values[0x1] 19 1 T239 1 T240 1 T8 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1076 1 T4 1 T6 1 T24 14
values[0x1] 17 1 T54 1 T241 1 T7 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1081 1 T4 1 T6 1 T24 14
values[0x1] 12 1 T95 2 T242 1 T7 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1072 1 T4 1 T6 1 T24 14
values[0x1] 21 1 T93 1 T95 1 T128 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1084 1 T4 1 T6 1 T24 14
values[0x1] 9 1 T243 1 T244 1 T245 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1088 1 T4 1 T6 1 T24 14
values[0x1] 5 1 T95 1 T66 1 T242 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1079 1 T4 1 T6 1 T24 13
values[0x1] 14 1 T24 1 T246 1 T247 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1071 1 T4 1 T6 1 T24 14
values[0x1] 22 1 T63 1 T241 1 T82 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 654 1 T4 1 T6 1 T24 10
values[0x1] 439 1 T24 4 T15 1 T54 3


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1076 1 T4 1 T6 1 T24 14
values[0x1] 17 1 T66 1 T7 1 T248 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1077 1 T4 1 T6 1 T24 14
values[0x1] 16 1 T241 1 T229 1 T210 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1079 1 T4 1 T6 1 T24 13
values[0x1] 14 1 T24 1 T128 1 T249 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1081 1 T4 1 T6 1 T24 14
values[0x1] 12 1 T163 1 T229 1 T250 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1077 1 T4 1 T6 1 T24 14
values[0x1] 16 1 T95 1 T251 1 T210 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1072 1 T4 1 T6 1 T24 14
values[0x1] 21 1 T54 1 T66 1 T182 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1077 1 T4 1 T6 1 T24 14
values[0x1] 16 1 T251 1 T13 2 T252 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1073 1 T4 1 T6 1 T24 14
values[0x1] 20 1 T82 1 T237 1 T120 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1086 1 T4 1 T6 1 T24 14
values[0x1] 7 1 T240 1 T192 1 T246 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1076 1 T4 1 T6 1 T24 14
values[0x1] 17 1 T15 1 T95 1 T156 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1075 1 T4 1 T6 1 T24 13
values[0x1] 18 1 T24 1 T95 1 T182 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1073 1 T4 1 T6 1 T24 14
values[0x1] 20 1 T66 1 T242 1 T241 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1078 1 T4 1 T6 1 T24 14
values[0x1] 15 1 T95 1 T248 1 T253 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1074 1 T4 1 T6 1 T24 14
values[0x1] 19 1 T54 1 T93 1 T63 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1079 1 T4 1 T6 1 T24 14
values[0x1] 14 1 T95 1 T251 1 T248 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1083 1 T4 1 T6 1 T24 13
values[0x1] 10 1 T24 1 T95 1 T192 1


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_req_pending

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 1076 1 T4 1 T6 1 T24 14
values[0x1] 17 1 T95 1 T156 1 T251 1

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