Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1844619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

291689

1

T1

123

T2

72

T3

660

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	722088	1			T1	299		T2	218		T3	1653
values[0x0]	693324	1			T1	301		T2	190		T3	1669
values[0x1]	720896	1			T1	315		T2	244		T3	1630

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1430288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

706020

1

T1

283

T2

218

T3

1602

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7910	1			T2	6		T3	22		T6	3
valid_sources[0x01]	8028	1			T1	3		T3	20		T6	3
valid_sources[0x02]	7701	1			T1	14		T3	19		T6	1
valid_sources[0x03]	8794	1			T1	13		T3	18		T4	4
valid_sources[0x04]	8373	1			T3	18		T6	1		T20	37
valid_sources[0x05]	8712	1			T1	7		T3	22		T6	2
valid_sources[0x06]	7250	1			T1	1		T3	22		T5	1
valid_sources[0x07]	7782	1			T1	23		T3	19		T5	4
valid_sources[0x08]	7661	1			T1	3		T3	18		T19	2
valid_sources[0x09]	9442	1			T1	13		T3	20		T6	2
valid_sources[0x0a]	7863	1			T1	10		T3	18		T5	1
valid_sources[0x0b]	8554	1			T1	2		T2	7		T3	20
valid_sources[0x0c]	8552	1			T1	20		T3	21		T6	4
valid_sources[0x0d]	8331	1			T1	11		T3	22		T6	8
valid_sources[0x0e]	7723	1			T3	17		T6	5		T20	1
valid_sources[0x0f]	8444	1			T1	2		T3	19		T6	2
valid_sources[0x10]	9109	1			T1	1		T3	21		T6	4
valid_sources[0x11]	9451	1			T1	8		T3	20		T4	1
valid_sources[0x12]	9825	1			T1	7		T3	19		T6	3
valid_sources[0x13]	8059	1			T3	19		T6	3		T20	2
valid_sources[0x14]	7854	1			T1	1		T3	19		T4	1
valid_sources[0x15]	9384	1			T3	20		T6	5		T19	2
valid_sources[0x16]	8774	1			T1	1		T3	18		T6	2
valid_sources[0x17]	8460	1			T2	16		T3	21		T6	6
valid_sources[0x18]	8685	1			T1	6		T3	19		T4	2
valid_sources[0x19]	8059	1			T1	3		T3	20		T19	1
valid_sources[0x1a]	7814	1			T1	1		T3	18		T6	5
valid_sources[0x1b]	7767	1			T1	8		T3	23		T6	5
valid_sources[0x1c]	9238	1			T1	4		T3	19		T20	1
valid_sources[0x1d]	8649	1			T1	14		T3	19		T4	2
valid_sources[0x1e]	8392	1			T1	3		T3	20		T4	3
valid_sources[0x1f]	7911	1			T3	17		T6	3		T20	7
valid_sources[0x20]	8315	1			T1	19		T3	20		T6	3
valid_sources[0x21]	8795	1			T3	21		T4	4		T6	2
valid_sources[0x22]	8647	1			T2	36		T3	18		T6	4
valid_sources[0x23]	7206	1			T3	21		T6	1		T19	1
valid_sources[0x24]	8250	1			T3	21		T6	3		T18	6
valid_sources[0x25]	7992	1			T3	21		T6	5		T20	15
valid_sources[0x26]	8642	1			T1	2		T3	17		T4	4
valid_sources[0x27]	7836	1			T3	18		T6	5		T19	1
valid_sources[0x28]	7025	1			T3	19		T6	2		T20	7
valid_sources[0x29]	8428	1			T1	3		T3	17		T6	3
valid_sources[0x2a]	9922	1			T1	5		T3	19		T6	5
valid_sources[0x2b]	8336	1			T3	18		T4	1		T6	3
valid_sources[0x2c]	8557	1			T3	19		T6	2		T20	18
valid_sources[0x2d]	8248	1			T1	1		T3	19		T6	2
valid_sources[0x2e]	9932	1			T1	1		T3	19		T6	3
valid_sources[0x2f]	7844	1			T1	4		T3	17		T6	8
valid_sources[0x30]	8457	1			T2	33		T3	18		T20	19
valid_sources[0x31]	8404	1			T2	18		T3	21		T6	6
valid_sources[0x32]	9062	1			T1	11		T3	19		T4	1
valid_sources[0x33]	7774	1			T1	4		T2	19		T3	20
valid_sources[0x34]	7643	1			T1	14		T3	18		T6	3
valid_sources[0x35]	8115	1			T1	1		T3	17		T6	4
valid_sources[0x36]	8004	1			T3	20		T6	5		T19	1
valid_sources[0x37]	7609	1			T2	12		T3	17		T6	1
valid_sources[0x38]	7744	1			T3	19		T6	1		T20	7
valid_sources[0x39]	8457	1			T1	11		T3	18		T4	1
valid_sources[0x3a]	8272	1			T3	18		T6	3		T18	4
valid_sources[0x3b]	7985	1			T1	3		T3	20		T6	2
valid_sources[0x3c]	7570	1			T3	18		T6	5		T20	8
valid_sources[0x3d]	7440	1			T2	10		T3	21		T6	4
valid_sources[0x3e]	8449	1			T1	4		T3	18		T6	2
valid_sources[0x3f]	8054	1			T1	1		T3	20		T4	6
valid_sources[0x40]	9127	1			T1	7		T3	18		T6	1
valid_sources[0x41]	9214	1			T1	3		T3	17		T6	2
valid_sources[0x42]	8487	1			T1	7		T3	20		T6	5
valid_sources[0x43]	8530	1			T3	20		T6	2		T20	11
valid_sources[0x44]	8905	1			T1	2		T3	19		T6	4
valid_sources[0x45]	7868	1			T1	4		T3	18		T6	3
valid_sources[0x46]	7104	1			T3	18		T6	2		T20	22
valid_sources[0x47]	7815	1			T1	2		T3	19		T6	1
valid_sources[0x48]	8536	1			T1	3		T3	19		T6	7
valid_sources[0x49]	8320	1			T1	2		T3	21		T6	6
valid_sources[0x4a]	7819	1			T3	21		T4	3		T6	5
valid_sources[0x4b]	7661	1			T3	18		T6	2		T20	30
valid_sources[0x4c]	8607	1			T1	3		T3	16		T20	22
valid_sources[0x4d]	7769	1			T3	18		T6	4		T20	8
valid_sources[0x4e]	8610	1			T1	5		T2	17		T3	20
valid_sources[0x4f]	8295	1			T1	10		T3	20		T6	2
valid_sources[0x50]	8948	1			T1	9		T3	21		T6	3
valid_sources[0x51]	8636	1			T1	6		T3	20		T5	1
valid_sources[0x52]	9077	1			T1	9		T3	21		T6	4
valid_sources[0x53]	7482	1			T3	21		T6	3		T19	1
valid_sources[0x54]	8032	1			T1	6		T3	18		T4	1
valid_sources[0x55]	8037	1			T1	5		T3	18		T6	6
valid_sources[0x56]	8756	1			T3	19		T6	9		T17	1
valid_sources[0x57]	8044	1			T1	1		T3	18		T5	2
valid_sources[0x58]	9193	1			T3	21		T6	2		T19	1
valid_sources[0x59]	8707	1			T1	31		T2	7		T3	19
valid_sources[0x5a]	8032	1			T1	11		T3	22		T6	4
valid_sources[0x5b]	7697	1			T1	1		T3	22		T6	6
valid_sources[0x5c]	8128	1			T1	3		T3	20		T6	4
valid_sources[0x5d]	8345	1			T3	20		T4	2		T6	2
valid_sources[0x5e]	8103	1			T3	20		T6	4		T20	5
valid_sources[0x5f]	9522	1			T1	10		T3	22		T6	4
valid_sources[0x60]	8362	1			T1	3		T2	16		T3	19
valid_sources[0x61]	7806	1			T3	20		T6	3		T19	1
valid_sources[0x62]	7476	1			T3	18		T4	8		T6	3
valid_sources[0x63]	7665	1			T1	2		T3	20		T6	1
valid_sources[0x64]	8119	1			T1	15		T3	20		T4	1
valid_sources[0x65]	8593	1			T1	7		T3	18		T6	2
valid_sources[0x66]	8699	1			T1	5		T3	21		T6	4
valid_sources[0x67]	8706	1			T1	4		T2	33		T3	21
valid_sources[0x68]	9563	1			T3	18		T6	4		T20	15
valid_sources[0x69]	7946	1			T3	18		T6	6		T20	10
valid_sources[0x6a]	8560	1			T3	18		T6	6		T19	1
valid_sources[0x6b]	8347	1			T1	4		T3	18		T6	3
valid_sources[0x6c]	7868	1			T1	5		T3	20		T5	3
valid_sources[0x6d]	8640	1			T3	18		T6	5		T20	38
valid_sources[0x6e]	9030	1			T2	9		T3	21		T6	5
valid_sources[0x6f]	9321	1			T3	18		T20	3		T17	7
valid_sources[0x70]	8598	1			T1	15		T3	21		T6	4
valid_sources[0x71]	8394	1			T1	1		T3	19		T6	2
valid_sources[0x72]	7916	1			T1	6		T3	19		T6	4
valid_sources[0x73]	8021	1			T3	20		T6	2		T21	1
valid_sources[0x74]	8391	1			T1	13		T3	20		T6	11
valid_sources[0x75]	9011	1			T1	4		T2	6		T3	19
valid_sources[0x76]	8352	1			T2	13		T3	18		T4	3
valid_sources[0x77]	7835	1			T1	3		T3	19		T4	1
valid_sources[0x78]	8187	1			T1	3		T3	18		T6	8
valid_sources[0x79]	7910	1			T3	23		T4	2		T6	10
valid_sources[0x7a]	8173	1			T3	21		T6	2		T19	1
valid_sources[0x7b]	7882	1			T1	6		T3	20		T6	2
valid_sources[0x7c]	8888	1			T1	4		T3	19		T6	1
valid_sources[0x7d]	9628	1			T2	12		T3	19		T20	41
valid_sources[0x7e]	7943	1			T1	1		T3	17		T6	1
valid_sources[0x7f]	8346	1			T1	12		T3	19		T6	4
valid_sources[0x80]	9226	1			T3	20		T5	3		T20	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30472

1

T1

12

T2

7

T3

77

values[0x0]

all_enables

biggest_size

231037

1

T1

98

T2

56

T3

535

values[0x1]

all_enables

biggest_size

30180

1

T1

13

T2

9

T3

48