Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	368333671	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	368333671	0	0
T1	26155864	462759	0	0
T2	1486464	20866	0	0
T3	27067152	2016660	0	0
T4	2055984	30388	0	0
T5	742896	14566	0	0
T6	26221888	473922	0	0
T17	0	3924	0	0
T18	143304	2653	0	0
T19	9079224	209400	0	0
T20	355768	15451	0	0
T21	13272000	320848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26155864	26154016	0	0
T2	1486464	1486016	0	0
T3	27067152	27066760	0	0
T4	2055984	2049432	0	0
T5	742896	739256	0	0
T6	26221888	26219816	0	0
T18	143304	140168	0	0
T19	9079224	9077040	0	0
T20	355768	353304	0	0
T21	13272000	13268080	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26155864	26154016	0	0
T2	1486464	1486016	0	0
T3	27067152	27066760	0	0
T4	2055984	2049432	0	0
T5	742896	739256	0	0
T6	26221888	26219816	0	0
T18	143304	140168	0	0
T19	9079224	9077040	0	0
T20	355768	353304	0	0
T21	13272000	13268080	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	26155864	26154016	0	0
T2	1486464	1486016	0	0
T3	27067152	27066760	0	0
T4	2055984	2049432	0	0
T5	742896	739256	0	0
T6	26221888	26219816	0	0
T18	143304	140168	0	0
T19	9079224	9077040	0	0
T20	355768	353304	0	0
T21	13272000	13268080	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	130753955	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	130753955	0	0
T1	467069	452739	0	0
T2	26544	5408	0	0
T3	483342	22673	0	0
T4	36714	14047	0	0
T5	13266	6788	0	0
T6	468248	200953	0	0
T18	2559	1064	0	0
T19	162129	90180	0	0
T20	6353	6019	0	0
T21	237000	142043	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	98682072	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	98682072	0	0
T1	467069	2938	0	0
T2	26544	5034	0	0
T3	483342	179210	0	0
T4	36714	4624	0	0
T5	13266	1802	0	0
T6	468248	69507	0	0
T18	2559	517	0	0
T19	162129	36342	0	0
T20	6353	3144	0	0
T21	237000	53582	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1563830	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1563830	0	0
T1	467069	129	0	0
T2	26544	136	0	0
T3	483342	0	0	0
T4	36714	348	0	0
T5	13266	197	0	0
T6	468248	5904	0	0
T17	0	59	0	0
T18	2559	36	0	0
T19	162129	1561	0	0
T20	6353	105	0	0
T21	237000	2948	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	4041377	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	4041377	0	0
T1	467069	25	0	0
T2	26544	100	0	0
T3	483342	0	0	0
T4	36714	152	0	0
T5	13266	67	0	0
T6	468248	2506	0	0
T17	0	87	0	0
T18	2559	43	0	0
T19	162129	2154	0	0
T20	6353	105	0	0
T21	237000	2707	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1500407	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1500407	0	0
T1	467069	167	0	0
T2	26544	128	0	0
T3	483342	1012	0	0
T4	36714	282	0	0
T5	13266	139	0	0
T6	468248	3774	0	0
T17	0	36	0	0
T18	2559	0	0	0
T19	162129	1983	0	0
T20	6353	114	0	0
T21	237000	2712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3322223	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3322223	0	0
T1	467069	47	0	0
T2	26544	90	0	0
T3	483342	91997	0	0
T4	36714	148	0	0
T5	13266	88	0	0
T6	468248	1717	0	0
T17	0	53	0	0
T18	2559	0	0	0
T19	162129	129	0	0
T20	6353	114	0	0
T21	237000	3834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1489052	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1489052	0	0
T1	467069	116	0	0
T2	26544	148	0	0
T3	483342	3576	0	0
T4	36714	289	0	0
T5	13266	116	0	0
T6	468248	3654	0	0
T18	2559	4	0	0
T19	162129	755	0	0
T20	6353	129	0	0
T21	237000	2848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	4330678	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	4330678	0	0
T1	467069	25	0	0
T2	26544	154	0	0
T3	483342	275493	0	0
T4	36714	116	0	0
T5	13266	39	0	0
T6	468248	1775	0	0
T18	2559	18	0	0
T19	162129	1369	0	0
T20	6353	129	0	0
T21	237000	1187	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1497561	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1497561	0	0
T1	467069	155	0	0
T2	26544	183	0	0
T3	483342	0	0	0
T4	36714	235	0	0
T5	13266	154	0	0
T6	468248	7856	0	0
T17	0	142	0	0
T18	2559	9	0	0
T19	162129	1175	0	0
T20	6353	109	0	0
T21	237000	3591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3001436	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3001436	0	0
T1	467069	34	0	0
T2	26544	170	0	0
T3	483342	0	0	0
T4	36714	128	0	0
T5	13266	68	0	0
T6	468248	3613	0	0
T17	0	141	0	0
T18	2559	5	0	0
T19	162129	621	0	0
T20	6353	109	0	0
T21	237000	2102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1543317	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1543317	0	0
T1	467069	180	0	0
T2	26544	210	0	0
T3	483342	0	0	0
T4	36714	433	0	0
T5	13266	205	0	0
T6	468248	3663	0	0
T17	0	92	0	0
T18	2559	35	0	0
T19	162129	1389	0	0
T20	6353	114	0	0
T21	237000	1382	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3088289	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3088289	0	0
T1	467069	39	0	0
T2	26544	166	0	0
T3	483342	0	0	0
T4	36714	130	0	0
T5	13266	83	0	0
T6	468248	1814	0	0
T17	0	108	0	0
T18	2559	17	0	0
T19	162129	1609	0	0
T20	6353	114	0	0
T21	237000	3164	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1516611	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1516611	0	0
T1	467069	176	0	0
T2	26544	93	0	0
T3	483342	1041	0	0
T4	36714	258	0	0
T5	13266	120	0	0
T6	468248	5806	0	0
T18	2559	19	0	0
T19	162129	1274	0	0
T20	6353	107	0	0
T21	237000	2913	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	4005328	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	4005328	0	0
T1	467069	34	0	0
T2	26544	110	0	0
T3	483342	77361	0	0
T4	36714	113	0	0
T5	13266	58	0	0
T6	468248	2599	0	0
T18	2559	29	0	0
T19	162129	115	0	0
T20	6353	107	0	0
T21	237000	1642	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1576843	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1576843	0	0
T1	467069	142	0	0
T2	26544	195	0	0
T3	483342	0	0	0
T4	36714	281	0	0
T5	13266	163	0	0
T6	468248	6138	0	0
T17	0	108	0	0
T18	2559	49	0	0
T19	162129	233	0	0
T20	6353	119	0	0
T21	237000	1320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3957997	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3957997	0	0
T1	467069	41	0	0
T2	26544	204	0	0
T3	483342	0	0	0
T4	36714	88	0	0
T5	13266	62	0	0
T6	468248	2866	0	0
T17	0	146	0	0
T18	2559	67	0	0
T19	162129	857	0	0
T20	6353	119	0	0
T21	237000	1687	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1539174	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1539174	0	0
T1	467069	172	0	0
T2	26544	182	0	0
T3	483342	1292	0	0
T4	36714	314	0	0
T5	13266	124	0	0
T6	468248	6393	0	0
T18	2559	11	0	0
T19	162129	1182	0	0
T20	6353	132	0	0
T21	237000	2657	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3758911	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3758911	0	0
T1	467069	39	0	0
T2	26544	176	0	0
T3	483342	101370	0	0
T4	36714	148	0	0
T5	13266	84	0	0
T6	468248	3084	0	0
T17	0	123	0	0
T18	2559	0	0	0
T19	162129	942	0	0
T20	6353	132	0	0
T21	237000	1926	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1547222	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1547222	0	0
T1	467069	116	0	0
T2	26544	172	0	0
T3	483342	2364	0	0
T4	36714	340	0	0
T5	13266	117	0	0
T6	468248	4091	0	0
T18	2559	19	0	0
T19	162129	1244	0	0
T20	6353	121	0	0
T21	237000	2529	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3672263	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3672263	0	0
T1	467069	27	0	0
T2	26544	158	0	0
T3	483342	176723	0	0
T4	36714	205	0	0
T5	13266	58	0	0
T6	468248	1959	0	0
T18	2559	23	0	0
T19	162129	1317	0	0
T20	6353	121	0	0
T21	237000	1823	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1478657	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1478657	0	0
T1	467069	158	0	0
T2	26544	250	0	0
T3	483342	0	0	0
T4	36714	228	0	0
T5	13266	138	0	0
T6	468248	3606	0	0
T17	0	97	0	0
T18	2559	28	0	0
T19	162129	2049	0	0
T20	6353	129	0	0
T21	237000	944	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3870842	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3870842	0	0
T1	467069	51	0	0
T2	26544	215	0	0
T3	483342	0	0	0
T4	36714	147	0	0
T5	13266	64	0	0
T6	468248	1720	0	0
T17	0	60	0	0
T18	2559	36	0	0
T19	162129	1208	0	0
T20	6353	129	0	0
T21	237000	1430	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1540742	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1540742	0	0
T1	467069	176	0	0
T2	26544	216	0	0
T3	483342	2110	0	0
T4	36714	400	0	0
T5	13266	116	0	0
T6	468248	3355	0	0
T18	2559	27	0	0
T19	162129	563	0	0
T20	6353	98	0	0
T21	237000	1127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3238980	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3238980	0	0
T1	467069	43	0	0
T2	26544	191	0	0
T3	483342	169269	0	0
T4	36714	187	0	0
T5	13266	68	0	0
T6	468248	1833	0	0
T18	2559	40	0	0
T19	162129	650	0	0
T20	6353	98	0	0
T21	237000	873	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1525486	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1525486	0	0
T1	467069	113	0	0
T2	26544	294	0	0
T3	483342	0	0	0
T4	36714	262	0	0
T5	13266	133	0	0
T6	468248	3354	0	0
T17	0	91	0	0
T18	2559	20	0	0
T19	162129	4205	0	0
T20	6353	110	0	0
T21	237000	2432	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	4351482	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	4351482	0	0
T1	467069	29	0	0
T2	26544	240	0	0
T3	483342	0	0	0
T4	36714	95	0	0
T5	13266	86	0	0
T6	468248	1547	0	0
T17	0	108	0	0
T18	2559	4	0	0
T19	162129	4621	0	0
T20	6353	110	0	0
T21	237000	981	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1540087	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1540087	0	0
T1	467069	165	0	0
T2	26544	180	0	0
T3	483342	0	0	0
T4	36714	252	0	0
T5	13266	83	0	0
T6	468248	5475	0	0
T17	0	128	0	0
T18	2559	5	0	0
T19	162129	1506	0	0
T20	6353	110	0	0
T21	237000	4509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3111460	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3111460	0	0
T1	467069	36	0	0
T2	26544	205	0	0
T3	483342	0	0	0
T4	36714	115	0	0
T5	13266	42	0	0
T6	468248	2633	0	0
T17	0	113	0	0
T18	2559	5	0	0
T19	162129	546	0	0
T20	6353	110	0	0
T21	237000	2831	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1552068	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1552068	0	0
T1	467069	154	0	0
T2	26544	120	0	0
T3	483342	1223	0	0
T4	36714	341	0	0
T5	13266	151	0	0
T6	468248	3762	0	0
T18	2559	28	0	0
T19	162129	1340	0	0
T20	6353	114	0	0
T21	237000	5636	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3550248	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3550248	0	0
T1	467069	677	0	0
T2	26544	97	0	0
T3	483342	95125	0	0
T4	36714	163	0	0
T5	13266	35	0	0
T6	468248	1691	0	0
T18	2559	33	0	0
T19	162129	443	0	0
T20	6353	114	0	0
T21	237000	2785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1540364	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1540364	0	0
T1	467069	148	0	0
T2	26544	234	0	0
T3	483342	1276	0	0
T4	36714	310	0	0
T5	13266	195	0	0
T6	468248	3840	0	0
T18	2559	51	0	0
T19	162129	1734	0	0
T20	6353	126	0	0
T21	237000	2279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3543306	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3543306	0	0
T1	467069	122	0	0
T2	26544	241	0	0
T3	483342	104574	0	0
T4	36714	169	0	0
T5	13266	99	0	0
T6	468248	1844	0	0
T18	2559	49	0	0
T19	162129	498	0	0
T20	6353	126	0	0
T21	237000	1277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1538588	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1538588	0	0
T1	467069	113	0	0
T2	26544	232	0	0
T3	483342	1106	0	0
T4	36714	242	0	0
T5	13266	134	0	0
T6	468248	5354	0	0
T18	2559	17	0	0
T19	162129	2194	0	0
T20	6353	124	0	0
T21	237000	1721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	2900756	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	2900756	0	0
T1	467069	28	0	0
T2	26544	239	0	0
T3	483342	84488	0	0
T4	36714	121	0	0
T5	13266	99	0	0
T6	468248	2486	0	0
T18	2559	2	0	0
T19	162129	2183	0	0
T20	6353	124	0	0
T21	237000	1897	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1546051	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1546051	0	0
T1	467069	209	0	0
T2	26544	184	0	0
T3	483342	0	0	0
T4	36714	319	0	0
T5	13266	233	0	0
T6	468248	6135	0	0
T17	0	174	0	0
T18	2559	18	0	0
T19	162129	2665	0	0
T20	6353	106	0	0
T21	237000	3282	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3603397	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3603397	0	0
T1	467069	126	0	0
T2	26544	198	0	0
T3	483342	0	0	0
T4	36714	125	0	0
T5	13266	100	0	0
T6	468248	2921	0	0
T17	0	178	0	0
T18	2559	9	0	0
T19	162129	1554	0	0
T20	6353	106	0	0
T21	237000	2467	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1530172	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1530172	0	0
T1	467069	128	0	0
T2	26544	231	0	0
T3	483342	1256	0	0
T4	36714	303	0	0
T5	13266	178	0	0
T6	468248	6746	0	0
T18	2559	20	0	0
T19	162129	1366	0	0
T20	6353	106	0	0
T21	237000	3773	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3655652	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3655652	0	0
T1	467069	27	0	0
T2	26544	224	0	0
T3	483342	104232	0	0
T4	36714	131	0	0
T5	13266	58	0	0
T6	468248	3958	0	0
T18	2559	5	0	0
T19	162129	1928	0	0
T20	6353	106	0	0
T21	237000	2271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1527796	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1527796	0	0
T1	467069	187	0	0
T2	26544	146	0	0
T3	483342	1269	0	0
T4	36714	375	0	0
T5	13266	132	0	0
T6	468248	3599	0	0
T17	0	115	0	0
T18	2559	0	0	0
T19	162129	2987	0	0
T20	6353	127	0	0
T21	237000	3283	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	4368452	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	4368452	0	0
T1	467069	60	0	0
T2	26544	176	0	0
T3	483342	96479	0	0
T4	36714	169	0	0
T5	13266	22	0	0
T6	468248	1756	0	0
T17	0	154	0	0
T18	2559	0	0	0
T19	162129	1812	0	0
T20	6353	127	0	0
T21	237000	2180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1442170	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1442170	0	0
T1	467069	150	0	0
T2	26544	126	0	0
T3	483342	1290	0	0
T4	36714	285	0	0
T5	13266	214	0	0
T6	468248	4385	0	0
T18	2559	32	0	0
T19	162129	3247	0	0
T20	6353	111	0	0
T21	237000	1150	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3514884	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3514884	0	0
T1	467069	792	0	0
T2	26544	210	0	0
T3	483342	101582	0	0
T4	36714	100	0	0
T5	13266	76	0	0
T6	468248	2084	0	0
T18	2559	24	0	0
T19	162129	2296	0	0
T20	6353	111	0	0
T21	237000	1075	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1509647	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1509647	0	0
T1	467069	168	0	0
T2	26544	435	0	0
T3	483342	0	0	0
T4	36714	296	0	0
T5	13266	137	0	0
T6	468248	5953	0	0
T17	0	74	0	0
T18	2559	7	0	0
T19	162129	1616	0	0
T20	6353	130	0	0
T21	237000	1767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3529125	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3529125	0	0
T1	467069	38	0	0
T2	26544	314	0	0
T3	483342	0	0	0
T4	36714	83	0	0
T5	13266	86	0	0
T6	468248	2708	0	0
T17	0	76	0	0
T18	2559	2	0	0
T19	162129	1032	0	0
T20	6353	130	0	0
T21	237000	677	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1549010	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1549010	0	0
T1	467069	129	0	0
T2	26544	326	0	0
T3	483342	0	0	0
T4	36714	259	0	0
T5	13266	129	0	0
T6	468248	6031	0	0
T17	0	163	0	0
T18	2559	20	0	0
T19	162129	2849	0	0
T20	6353	122	0	0
T21	237000	1717	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3546950	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3546950	0	0
T1	467069	29	0	0
T2	26544	221	0	0
T3	483342	0	0	0
T4	36714	137	0	0
T5	13266	54	0	0
T6	468248	2901	0	0
T17	0	121	0	0
T18	2559	13	0	0
T19	162129	2797	0	0
T20	6353	122	0	0
T21	237000	1510	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1524608	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1524608	0	0
T1	467069	173	0	0
T2	26544	205	0	0
T3	483342	0	0	0
T4	36714	312	0	0
T5	13266	178	0	0
T6	468248	7413	0	0
T17	0	159	0	0
T18	2559	34	0	0
T19	162129	1826	0	0
T20	6353	122	0	0
T21	237000	4847	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3349274	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3349274	0	0
T1	467069	39	0	0
T2	26544	171	0	0
T3	483342	0	0	0
T4	36714	131	0	0
T5	13266	64	0	0
T6	468248	3634	0	0
T17	0	145	0	0
T18	2559	11	0	0
T19	162129	1378	0	0
T20	6353	122	0	0
T21	237000	4519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1479384	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1479384	0	0
T1	467069	143	0	0
T2	26544	181	0	0
T3	483342	3857	0	0
T4	36714	449	0	0
T5	13266	168	0	0
T6	468248	5794	0	0
T18	2559	24	0	0
T19	162129	1752	0	0
T20	6353	129	0	0
T21	237000	2888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3647678	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3647678	0	0
T1	467069	428	0	0
T2	26544	177	0	0
T3	483342	313412	0	0
T4	36714	150	0	0
T5	13266	41	0	0
T6	468248	2854	0	0
T18	2559	38	0	0
T19	162129	457	0	0
T20	6353	129	0	0
T21	237000	2030	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1581733	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1581733	0	0
T1	467069	134	0	0
T2	26544	205	0	0
T3	483342	0	0	0
T4	36714	265	0	0
T5	13266	105	0	0
T6	468248	5782	0	0
T17	0	174	0	0
T18	2559	18	0	0
T19	162129	1185	0	0
T20	6353	108	0	0
T21	237000	3679	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3472348	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3472348	0	0
T1	467069	27	0	0
T2	26544	191	0	0
T3	483342	0	0	0
T4	36714	96	0	0
T5	13266	44	0	0
T6	468248	2674	0	0
T17	0	122	0	0
T18	2559	13	0	0
T19	162129	460	0	0
T20	6353	108	0	0
T21	237000	2891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1498115	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1498115	0	0
T1	467069	156	0	0
T2	26544	184	0	0
T3	483342	0	0	0
T4	36714	329	0	0
T5	13266	228	0	0
T6	468248	5633	0	0
T17	0	177	0	0
T18	2559	11	0	0
T19	162129	1162	0	0
T20	6353	99	0	0
T21	237000	2239	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3546585	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3546585	0	0
T1	467069	32	0	0
T2	26544	178	0	0
T3	483342	0	0	0
T4	36714	95	0	0
T5	13266	73	0	0
T6	468248	2770	0	0
T17	0	176	0	0
T18	2559	17	0	0
T19	162129	1319	0	0
T20	6353	99	0	0
T21	237000	1376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	1526141	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	1526141	0	0
T1	467069	188	0	0
T2	26544	209	0	0
T3	483342	0	0	0
T4	36714	180	0	0
T5	13266	187	0	0
T6	468248	3986	0	0
T17	0	95	0	0
T18	2559	13	0	0
T19	162129	1494	0	0
T20	6353	123	0	0
T21	237000	1468	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	331689331	3712887	0	0
DepthKnown_A	331689331	331560934	0	0
RvalidKnown_A	331689331	331560934	0	0
WreadyKnown_A	331689331	331560934	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	3712887	0	0
T1	467069	42	0	0
T2	26544	203	0	0
T3	483342	0	0	0
T4	36714	88	0	0
T5	13266	84	0	0
T6	468248	2033	0	0
T17	0	129	0	0
T18	2559	14	0	0
T19	162129	2047	0	0
T20	6353	123	0	0
T21	237000	440	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	331689331	331560934	0	0
T1	467069	467036	0	0
T2	26544	26536	0	0
T3	483342	483335	0	0
T4	36714	36597	0	0
T5	13266	13201	0	0
T6	468248	468211	0	0
T18	2559	2503	0	0
T19	162129	162090	0	0
T20	6353	6309	0	0
T21	237000	236930	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0