Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1726196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

271768

1

T1

6

T2

138

T3

520

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	674706	1			T1	51		T2	316		T3	1302
values[0x0]	647437	1			T1	3		T2	331		T3	1204
values[0x1]	675821	1			T1	34		T2	332		T3	1232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1337787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

660177

1

T1

30

T2

327

T3

1192

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7130	1			T1	2		T2	4		T3	27
valid_sources[0x01]	9235	1			T2	4		T3	15		T4	24
valid_sources[0x02]	8265	1			T2	3		T3	10		T4	14
valid_sources[0x03]	7182	1			T2	4		T3	11		T4	22
valid_sources[0x04]	8818	1			T2	4		T3	13		T4	15
valid_sources[0x05]	7427	1			T1	1		T2	3		T3	13
valid_sources[0x06]	7736	1			T2	4		T3	20		T4	23
valid_sources[0x07]	7456	1			T2	4		T3	16		T4	35
valid_sources[0x08]	7548	1			T2	4		T3	13		T4	30
valid_sources[0x09]	8404	1			T1	1		T2	4		T3	18
valid_sources[0x0a]	7576	1			T2	3		T3	11		T4	18
valid_sources[0x0b]	7914	1			T2	3		T3	14		T4	13
valid_sources[0x0c]	7216	1			T2	4		T3	16		T4	19
valid_sources[0x0d]	7803	1			T2	4		T3	12		T4	13
valid_sources[0x0e]	8632	1			T2	4		T3	11		T4	17
valid_sources[0x0f]	7744	1			T2	5		T3	14		T4	19
valid_sources[0x10]	7513	1			T2	4		T3	22		T4	19
valid_sources[0x11]	7345	1			T1	1		T2	5		T3	10
valid_sources[0x12]	6968	1			T2	4		T3	14		T4	9
valid_sources[0x13]	8448	1			T1	1		T2	4		T3	15
valid_sources[0x14]	7555	1			T2	4		T3	13		T4	30
valid_sources[0x15]	7940	1			T1	1		T2	3		T3	18
valid_sources[0x16]	7187	1			T1	1		T2	4		T3	21
valid_sources[0x17]	7746	1			T2	5		T3	18		T4	15
valid_sources[0x18]	7416	1			T2	4		T3	12		T4	15
valid_sources[0x19]	7678	1			T1	1		T2	4		T3	16
valid_sources[0x1a]	7765	1			T2	4		T3	30		T4	14
valid_sources[0x1b]	7618	1			T2	4		T3	9		T4	27
valid_sources[0x1c]	7202	1			T2	4		T3	13		T4	19
valid_sources[0x1d]	7914	1			T2	5		T3	20		T4	5
valid_sources[0x1e]	7777	1			T1	1		T2	5		T3	13
valid_sources[0x1f]	7789	1			T2	4		T3	17		T4	14
valid_sources[0x20]	7928	1			T1	1		T2	5		T3	18
valid_sources[0x21]	7236	1			T2	4		T3	18		T4	26
valid_sources[0x22]	8619	1			T2	4		T3	17		T4	27
valid_sources[0x23]	8122	1			T1	1		T2	4		T3	12
valid_sources[0x24]	7589	1			T1	1		T2	3		T3	22
valid_sources[0x25]	7525	1			T2	2		T3	17		T4	15
valid_sources[0x26]	7113	1			T2	3		T3	15		T4	16
valid_sources[0x27]	6704	1			T2	4		T3	13		T4	9
valid_sources[0x28]	8348	1			T1	1		T2	4		T3	8
valid_sources[0x29]	8138	1			T1	1		T2	4		T3	14
valid_sources[0x2a]	7326	1			T2	6		T3	12		T4	16
valid_sources[0x2b]	7796	1			T2	4		T3	10		T4	14
valid_sources[0x2c]	7814	1			T1	1		T2	4		T3	11
valid_sources[0x2d]	8480	1			T2	3		T3	10		T4	25
valid_sources[0x2e]	7314	1			T1	1		T2	3		T3	14
valid_sources[0x2f]	7985	1			T2	4		T3	15		T4	17
valid_sources[0x30]	8247	1			T2	4		T3	19		T4	9
valid_sources[0x31]	7465	1			T1	1		T2	3		T3	19
valid_sources[0x32]	6990	1			T1	1		T2	4		T3	8
valid_sources[0x33]	8273	1			T2	4		T3	7		T4	22
valid_sources[0x34]	7647	1			T2	3		T3	17		T4	34
valid_sources[0x35]	7334	1			T2	4		T3	12		T4	16
valid_sources[0x36]	7857	1			T1	1		T2	4		T3	13
valid_sources[0x37]	7758	1			T1	1		T2	3		T3	13
valid_sources[0x38]	7355	1			T2	5		T3	14		T4	19
valid_sources[0x39]	8146	1			T2	4		T3	17		T4	14
valid_sources[0x3a]	8430	1			T2	3		T3	20		T4	16
valid_sources[0x3b]	7851	1			T2	3		T3	7		T4	12
valid_sources[0x3c]	8043	1			T2	4		T3	13		T4	17
valid_sources[0x3d]	8000	1			T2	3		T3	25		T4	22
valid_sources[0x3e]	7745	1			T2	4		T3	8		T4	17
valid_sources[0x3f]	7447	1			T2	4		T3	18		T4	16
valid_sources[0x40]	6994	1			T2	4		T3	25		T4	17
valid_sources[0x41]	8017	1			T2	4		T3	11		T4	23
valid_sources[0x42]	9504	1			T2	4		T3	16		T4	22
valid_sources[0x43]	7805	1			T2	6		T3	13		T4	17
valid_sources[0x44]	8948	1			T2	4		T3	25		T4	20
valid_sources[0x45]	7681	1			T2	4		T3	13		T4	19
valid_sources[0x46]	7756	1			T2	2		T3	17		T4	16
valid_sources[0x47]	8202	1			T2	4		T3	8		T4	16
valid_sources[0x48]	7816	1			T2	4		T3	20		T4	14
valid_sources[0x49]	7007	1			T2	3		T3	16		T4	15
valid_sources[0x4a]	7622	1			T2	4		T3	14		T4	29
valid_sources[0x4b]	9348	1			T2	4		T3	15		T4	13
valid_sources[0x4c]	8576	1			T2	4		T3	2		T4	16
valid_sources[0x4d]	7829	1			T2	3		T3	9		T4	15
valid_sources[0x4e]	8452	1			T1	2		T2	4		T3	16
valid_sources[0x4f]	7458	1			T2	5		T3	18		T4	23
valid_sources[0x50]	7404	1			T2	2		T3	9		T4	39
valid_sources[0x51]	7482	1			T1	1		T2	4		T3	22
valid_sources[0x52]	6489	1			T2	3		T3	21		T4	25
valid_sources[0x53]	8006	1			T2	4		T3	20		T4	16
valid_sources[0x54]	7155	1			T2	4		T3	11		T4	18
valid_sources[0x55]	7753	1			T2	4		T3	20		T4	34
valid_sources[0x56]	7606	1			T2	3		T3	16		T4	23
valid_sources[0x57]	8067	1			T2	4		T3	10		T4	20
valid_sources[0x58]	7562	1			T2	4		T3	9		T4	30
valid_sources[0x59]	7012	1			T2	5		T3	15		T4	29
valid_sources[0x5a]	7367	1			T1	1		T2	4		T3	13
valid_sources[0x5b]	8645	1			T2	3		T3	23		T4	12
valid_sources[0x5c]	7443	1			T2	2		T3	17		T4	30
valid_sources[0x5d]	7184	1			T1	1		T2	5		T3	18
valid_sources[0x5e]	7438	1			T2	4		T3	12		T4	13
valid_sources[0x5f]	7656	1			T1	1		T2	4		T3	15
valid_sources[0x60]	7226	1			T2	4		T3	16		T4	16
valid_sources[0x61]	7554	1			T1	1		T2	4		T3	20
valid_sources[0x62]	7638	1			T2	4		T3	15		T4	48
valid_sources[0x63]	7732	1			T1	1		T2	4		T3	15
valid_sources[0x64]	8245	1			T1	1		T2	4		T3	8
valid_sources[0x65]	7410	1			T2	4		T3	19		T4	17
valid_sources[0x66]	8593	1			T2	5		T3	16		T4	17
valid_sources[0x67]	8552	1			T2	3		T3	18		T4	12
valid_sources[0x68]	7513	1			T1	2		T2	4		T3	19
valid_sources[0x69]	8895	1			T1	1		T2	3		T3	17
valid_sources[0x6a]	7838	1			T1	1		T2	4		T3	14
valid_sources[0x6b]	7546	1			T1	3		T2	4		T3	24
valid_sources[0x6c]	8363	1			T2	3		T3	12		T4	23
valid_sources[0x6d]	7883	1			T2	4		T3	15		T4	16
valid_sources[0x6e]	7676	1			T1	1		T2	4		T3	18
valid_sources[0x6f]	7419	1			T2	4		T3	13		T4	15
valid_sources[0x70]	7339	1			T2	4		T3	16		T4	26
valid_sources[0x71]	8259	1			T2	3		T3	17		T4	22
valid_sources[0x72]	7653	1			T2	3		T3	11		T4	30
valid_sources[0x73]	9064	1			T2	4		T3	8		T4	14
valid_sources[0x74]	8031	1			T2	4		T3	13		T4	22
valid_sources[0x75]	8238	1			T1	1		T2	5		T3	15
valid_sources[0x76]	7721	1			T1	1		T2	4		T3	23
valid_sources[0x77]	7408	1			T2	5		T3	13		T4	13
valid_sources[0x78]	9483	1			T1	1		T2	5		T3	10
valid_sources[0x79]	7788	1			T2	4		T3	17		T4	25
valid_sources[0x7a]	7736	1			T2	4		T3	13		T4	18
valid_sources[0x7b]	7472	1			T1	1		T2	4		T3	11
valid_sources[0x7c]	8191	1			T2	3		T3	15		T4	17
valid_sources[0x7d]	8995	1			T1	1		T2	4		T3	9
valid_sources[0x7e]	7780	1			T2	4		T3	18		T4	12
valid_sources[0x7f]	7820	1			T1	2		T2	3		T3	11
valid_sources[0x80]	7600	1			T1	2		T2	3		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28490

1

T1

3

T2

9

T3

49

values[0x0]

all_enables

biggest_size

214787

1

T1

1

T2

113

T3

412

values[0x1]

all_enables

biggest_size

28491

1

T1

2

T2

16

T3

59