Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

28 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon 100.00 1 100 1 64 64
alert_handler 100.00 1 100 1 64 64
aon_timer_aon 100.00 1 100 1 64 64
ast 100.00 1 100 1 64 64
clkmgr_aon 100.00 1 100 1 64 64
gpio 100.00 1 100 1 64 64
i2c0 100.00 1 100 1 64 64
i2c1 100.00 1 100 1 64 64
i2c2 100.00 1 100 1 64 64
lc_ctrl 100.00 1 100 1 64 64
main 100.00 1 100 1 64 64
otp_ctrl__core 100.00 1 100 1 64 64
otp_ctrl__prim 100.00 1 100 1 64 64
pattgen 100.00 1 100 1 64 64
pinmux_aon 100.00 1 100 1 64 64
pwm_aon 100.00 1 100 1 64 64
pwrmgr_aon 100.00 1 100 1 64 64
rstmgr_aon 100.00 1 100 1 64 64
rv_timer 100.00 1 100 1 64 64
sensor_ctrl_aon 100.00 1 100 1 64 64
spi_device 100.00 1 100 1 64 64
sram_ctrl_ret_aon__ram 100.00 1 100 1 64 64
sram_ctrl_ret_aon__regs 100.00 1 100 1 64 64
sysrst_ctrl_aon 100.00 1 100 1 64 64
uart0 100.00 1 100 1 64 64
uart1 100.00 1 100 1 64 64
uart2 100.00 1 100 1 64 64
uart3 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance adc_ctrl_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : alert_handler
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance alert_handler

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance alert_handler
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : aon_timer_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance aon_timer_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : ast
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance ast

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance ast
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : clkmgr_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance clkmgr_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : gpio
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance gpio
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : i2c0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance i2c0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : i2c1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance i2c1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : i2c2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance i2c2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : lc_ctrl
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance lc_ctrl
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : main
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance main

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance main
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : otp_ctrl__core
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl__core

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance otp_ctrl__core
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : otp_ctrl__prim
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl__prim

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance otp_ctrl__prim
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : pattgen
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance pattgen
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : pinmux_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance pinmux_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : pwm_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance pwm_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : pwrmgr_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance pwrmgr_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rstmgr_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rstmgr_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : rv_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance rv_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sensor_ctrl_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sensor_ctrl_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : spi_device
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance spi_device
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sram_ctrl_ret_aon__ram
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon__ram

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sram_ctrl_ret_aon__ram
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sram_ctrl_ret_aon__regs
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon__regs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sram_ctrl_ret_aon__regs
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : sysrst_ctrl_aon
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance sysrst_ctrl_aon
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : uart0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance uart0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : uart1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance uart1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : uart2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance uart2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0



Group Instance : uart3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance uart3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_dly 3 0 3 100.00 100 1 1 0
cp_rsp_dly 3 0 3 100.00 100 1 1 0


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 250 1 T2 1 T16 1 T20 1
small_delay 333 1 T1 1 T3 1 T4 1
zero 317 1 T5 1 T15 1 T17 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 100 1 T21 1 T27 1 T155 1
small_delay 483 1 T1 1 T2 1 T3 1
zero 317 1 T5 1 T15 1 T17 1

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