Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	347626329	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	347626329	0	0
T1	2270576	32171	0	0
T2	53565624	724038	0	0
T3	4055352	103538	0	0
T4	6509944	144875	0	0
T5	82824	3390	0	0
T15	3103856	136468	0	0
T16	10512824	1585352	0	0
T17	210560	9050	0	0
T18	4901792	71443	0	0
T19	16229192	388331	0	0
T20	0	389112	0	0
T21	0	102356	0	0
T22	0	3756	0	0
T23	0	463235	0	0
T24	0	4881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2270576	2268728	0	0
T2	53565624	53564560	0	0
T3	4055352	4054176	0	0
T4	6509944	6501040	0	0
T5	82824	81424	0	0
T15	3103856	3068184	0	0
T16	10512824	10512768	0	0
T17	210560	208880	0	0
T18	4901792	4898992	0	0
T19	16229192	16225552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2270576	2268728	0	0
T2	53565624	53564560	0	0
T3	4055352	4054176	0	0
T4	6509944	6501040	0	0
T5	82824	81424	0	0
T15	3103856	3068184	0	0
T16	10512824	10512768	0	0
T17	210560	208880	0	0
T18	4901792	4898992	0	0
T19	16229192	16225552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2270576	2268728	0	0
T2	53565624	53564560	0	0
T3	4055352	4054176	0	0
T4	6509944	6501040	0	0
T5	82824	81424	0	0
T15	3103856	3068184	0	0
T16	10512824	10512768	0	0
T17	210560	208880	0	0
T18	4901792	4898992	0	0
T19	16229192	16225552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	135443722	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	135443722	0	0
T1	40546	14652	0	0
T2	956529	4524	0	0
T3	72417	28813	0	0
T4	116249	54968	0	0
T5	1479	1320	0	0
T15	55426	53745	0	0
T16	187729	10189	0	0
T17	3760	3517	0	0
T18	87532	17670	0	0
T19	289807	153920	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	86340737	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	86340737	0	0
T1	40546	4912	0	0
T2	956529	357495	0	0
T3	72417	22957	0	0
T4	116249	28371	0	0
T5	1479	690	0	0
T15	55426	30131	0	0
T16	187729	782487	0	0
T17	3760	1845	0	0
T18	87532	18125	0	0
T19	289807	87445	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1488510	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1488510	0	0
T1	40546	271	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	2097	0	0
T5	1479	40	0	0
T15	55426	1018	0	0
T16	187729	0	0	0
T17	3760	64	0	0
T18	87532	548	0	0
T19	289807	2720	0	0
T21	0	1081	0	0
T22	0	111	0	0
T24	0	584	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2607534	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2607534	0	0
T1	40546	101	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	1855	0	0
T5	1479	40	0	0
T15	55426	1018	0	0
T16	187729	0	0	0
T17	3760	64	0	0
T18	87532	553	0	0
T19	289807	2909	0	0
T21	0	988	0	0
T22	0	111	0	0
T24	0	304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1487292	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1487292	0	0
T1	40546	365	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	603	0	0
T5	1479	21	0	0
T15	55426	923	0	0
T16	187729	0	0	0
T17	3760	81	0	0
T18	87532	635	0	0
T19	289807	2587	0	0
T21	0	4540	0	0
T22	0	94	0	0
T23	0	1360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3445347	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3445347	0	0
T1	40546	131	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	479	0	0
T5	1479	21	0	0
T15	55426	923	0	0
T16	187729	0	0	0
T17	3760	81	0	0
T18	87532	594	0	0
T19	289807	2583	0	0
T21	0	3537	0	0
T22	0	94	0	0
T23	0	93342	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1498081	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1498081	0	0
T1	40546	396	0	0
T2	956529	1296	0	0
T3	72417	1749	0	0
T4	116249	551	0	0
T5	1479	22	0	0
T15	55426	931	0	0
T16	187729	0	0	0
T17	3760	65	0	0
T18	87532	681	0	0
T19	289807	2476	0	0
T21	0	885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3003822	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3003822	0	0
T1	40546	170	0	0
T2	956529	102092	0	0
T3	72417	1701	0	0
T4	116249	451	0	0
T5	1479	22	0	0
T15	55426	931	0	0
T16	187729	0	0	0
T17	3760	65	0	0
T18	87532	679	0	0
T19	289807	2582	0	0
T21	0	183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1540167	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1540167	0	0
T1	40546	488	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	4309	0	0
T5	1479	28	0	0
T15	55426	1021	0	0
T16	187729	2007	0	0
T17	3760	68	0	0
T18	87532	801	0	0
T19	289807	2636	0	0
T21	0	839	0	0
T22	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3250646	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3250646	0	0
T1	40546	205	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	3142	0	0
T5	1479	28	0	0
T15	55426	1020	0	0
T16	187729	159404	0	0
T17	3760	68	0	0
T18	87532	635	0	0
T19	289807	2550	0	0
T21	0	1814	0	0
T22	0	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1497273	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1497273	0	0
T1	40546	451	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	643	0	0
T5	1479	23	0	0
T15	55426	666	0	0
T16	187729	0	0	0
T17	3760	73	0	0
T18	87532	613	0	0
T19	289807	2370	0	0
T21	0	287	0	0
T22	0	125	0	0
T23	0	2678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3310832	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3310832	0	0
T1	40546	195	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	596	0	0
T5	1479	23	0	0
T15	55426	666	0	0
T16	187729	0	0	0
T17	3760	73	0	0
T18	87532	676	0	0
T19	289807	2492	0	0
T21	0	181	0	0
T22	0	125	0	0
T23	0	199032	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1522061	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1522061	0	0
T1	40546	254	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	2963	0	0
T5	1479	26	0	0
T15	55426	966	0	0
T16	187729	0	0	0
T17	3760	71	0	0
T18	87532	806	0	0
T19	289807	2423	0	0
T21	0	3418	0	0
T22	0	108	0	0
T24	0	589	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2953370	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2953370	0	0
T1	40546	153	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	2196	0	0
T5	1479	26	0	0
T15	55426	965	0	0
T16	187729	0	0	0
T17	3760	71	0	0
T18	87532	792	0	0
T19	289807	2322	0	0
T21	0	1259	0	0
T22	0	108	0	0
T24	0	267	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1501918	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1501918	0	0
T1	40546	287	0	0
T2	956529	0	0	0
T3	72417	1324	0	0
T4	116249	750	0	0
T5	1479	16	0	0
T15	55426	1111	0	0
T16	187729	1082	0	0
T17	3760	63	0	0
T18	87532	530	0	0
T19	289807	2414	0	0
T21	0	2170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3310101	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3310101	0	0
T1	40546	164	0	0
T2	956529	0	0	0
T3	72417	1415	0	0
T4	116249	654	0	0
T5	1479	16	0	0
T15	55426	1111	0	0
T16	187729	83758	0	0
T17	3760	63	0	0
T18	87532	579	0	0
T19	289807	2469	0	0
T21	0	1678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1468855	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1468855	0	0
T1	40546	310	0	0
T2	956529	0	0	0
T3	72417	1758	0	0
T4	116249	2402	0	0
T5	1479	28	0	0
T15	55426	826	0	0
T16	187729	1106	0	0
T17	3760	67	0	0
T18	87532	675	0	0
T19	289807	2655	0	0
T21	0	1292	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3000192	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3000192	0	0
T1	40546	130	0	0
T2	956529	0	0	0
T3	72417	1086	0	0
T4	116249	1747	0	0
T5	1479	28	0	0
T15	55426	826	0	0
T16	187729	93270	0	0
T17	3760	67	0	0
T18	87532	702	0	0
T19	289807	2505	0	0
T21	0	653	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1492202	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1492202	0	0
T1	40546	398	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	683	0	0
T5	1479	26	0	0
T15	55426	916	0	0
T16	187729	1196	0	0
T17	3760	73	0	0
T18	87532	549	0	0
T19	289807	2273	0	0
T21	0	1390	0	0
T22	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2944117	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2944117	0	0
T1	40546	152	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	548	0	0
T5	1479	26	0	0
T15	55426	916	0	0
T16	187729	88467	0	0
T17	3760	73	0	0
T18	87532	530	0	0
T19	289807	2327	0	0
T21	0	1926	0	0
T22	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1469652	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1469652	0	0
T1	40546	251	0	0
T2	956529	1273	0	0
T3	72417	6391	0	0
T4	116249	2999	0	0
T5	1479	26	0	0
T15	55426	956	0	0
T16	187729	0	0	0
T17	3760	65	0	0
T18	87532	781	0	0
T19	289807	2459	0	0
T21	0	3577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2600891	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2600891	0	0
T1	40546	130	0	0
T2	956529	92376	0	0
T3	72417	4698	0	0
T4	116249	1845	0	0
T5	1479	26	0	0
T15	55426	955	0	0
T16	187729	0	0	0
T17	3760	65	0	0
T18	87532	770	0	0
T19	289807	2328	0	0
T21	0	3034	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1534885	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1534885	0	0
T1	40546	285	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	603	0	0
T5	1479	35	0	0
T15	55426	870	0	0
T16	187729	1163	0	0
T17	3760	64	0	0
T18	87532	471	0	0
T19	289807	2681	0	0
T20	0	1089	0	0
T21	0	2236	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3234917	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3234917	0	0
T1	40546	113	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	587	0	0
T5	1479	35	0	0
T15	55426	870	0	0
T16	187729	89728	0	0
T17	3760	64	0	0
T18	87532	557	0	0
T19	289807	2521	0	0
T20	0	84726	0	0
T21	0	3576	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1449659	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1449659	0	0
T1	40546	373	0	0
T2	956529	0	0	0
T3	72417	2137	0	0
T4	116249	536	0	0
T5	1479	32	0	0
T15	55426	687	0	0
T16	187729	1051	0	0
T17	3760	56	0	0
T18	87532	648	0	0
T19	289807	2483	0	0
T21	0	975	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3648332	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3648332	0	0
T1	40546	114	0	0
T2	956529	0	0	0
T3	72417	1529	0	0
T4	116249	420	0	0
T5	1479	32	0	0
T15	55426	687	0	0
T16	187729	72143	0	0
T17	3760	56	0	0
T18	87532	670	0	0
T19	289807	2518	0	0
T21	0	2548	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1471822	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1471822	0	0
T1	40546	403	0	0
T2	956529	0	0	0
T3	72417	2551	0	0
T4	116249	607	0	0
T5	1479	21	0	0
T15	55426	1642	0	0
T16	187729	0	0	0
T17	3760	63	0	0
T18	87532	618	0	0
T19	289807	2488	0	0
T21	0	2852	0	0
T22	0	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2887334	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2887334	0	0
T1	40546	175	0	0
T2	956529	0	0	0
T3	72417	1736	0	0
T4	116249	467	0	0
T5	1479	21	0	0
T15	55426	1641	0	0
T16	187729	0	0	0
T17	3760	63	0	0
T18	87532	744	0	0
T19	289807	2644	0	0
T21	0	1384	0	0
T22	0	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1468199	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1468199	0	0
T1	40546	260	0	0
T2	956529	0	0	0
T3	72417	2363	0	0
T4	116249	634	0	0
T5	1479	19	0	0
T15	55426	743	0	0
T16	187729	0	0	0
T17	3760	69	0	0
T18	87532	774	0	0
T19	289807	4630	0	0
T21	0	629	0	0
T22	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3589391	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3589391	0	0
T1	40546	147	0	0
T2	956529	0	0	0
T3	72417	1891	0	0
T4	116249	568	0	0
T5	1479	19	0	0
T15	55426	743	0	0
T16	187729	0	0	0
T17	3760	69	0	0
T18	87532	991	0	0
T19	289807	4579	0	0
T21	0	685	0	0
T22	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1490154	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1490154	0	0
T1	40546	306	0	0
T2	956529	1025	0	0
T3	72417	0	0	0
T4	116249	456	0	0
T5	1479	29	0	0
T15	55426	1728	0	0
T16	187729	1375	0	0
T17	3760	73	0	0
T18	87532	548	0	0
T19	289807	2544	0	0
T21	0	969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3019715	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3019715	0	0
T1	40546	143	0	0
T2	956529	88960	0	0
T3	72417	0	0	0
T4	116249	462	0	0
T5	1479	29	0	0
T15	55426	1728	0	0
T16	187729	104865	0	0
T17	3760	73	0	0
T18	87532	685	0	0
T19	289807	2559	0	0
T21	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1511814	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1511814	0	0
T1	40546	308	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	788	0	0
T5	1479	27	0	0
T15	55426	1247	0	0
T16	187729	0	0	0
T17	3760	63	0	0
T18	87532	700	0	0
T19	289807	2646	0	0
T21	0	2856	0	0
T22	0	109	0	0
T24	0	878	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	4342896	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	4342896	0	0
T1	40546	116	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	643	0	0
T5	1479	27	0	0
T15	55426	1247	0	0
T16	187729	0	0	0
T17	3760	63	0	0
T18	87532	780	0	0
T19	289807	2487	0	0
T21	0	1743	0	0
T22	0	109	0	0
T24	0	317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1495230	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1495230	0	0
T1	40546	351	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	2432	0	0
T5	1479	25	0	0
T15	55426	701	0	0
T16	187729	0	0	0
T17	3760	68	0	0
T18	87532	607	0	0
T19	289807	2535	0	0
T21	0	2732	0	0
T22	0	83	0	0
T24	0	826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2678640	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2678640	0	0
T1	40546	142	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	2189	0	0
T5	1479	25	0	0
T15	55426	701	0	0
T16	187729	0	0	0
T17	3760	68	0	0
T18	87532	656	0	0
T19	289807	2649	0	0
T21	0	1852	0	0
T22	0	83	0	0
T24	0	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1496951	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1496951	0	0
T1	40546	258	0	0
T2	956529	0	0	0
T3	72417	1475	0	0
T4	116249	747	0	0
T5	1479	19	0	0
T15	55426	1420	0	0
T16	187729	0	0	0
T17	3760	62	0	0
T18	87532	695	0	0
T19	289807	2378	0	0
T20	0	1272	0	0
T21	0	1763	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3108331	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3108331	0	0
T1	40546	129	0	0
T2	956529	0	0	0
T3	72417	1420	0	0
T4	116249	544	0	0
T5	1479	19	0	0
T15	55426	1420	0	0
T16	187729	0	0	0
T17	3760	62	0	0
T18	87532	700	0	0
T19	289807	2524	0	0
T20	0	93545	0	0
T21	0	2131	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1534549	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1534549	0	0
T1	40546	268	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	583	0	0
T5	1479	16	0	0
T15	55426	444	0	0
T16	187729	0	0	0
T17	3760	56	0	0
T18	87532	748	0	0
T19	289807	2452	0	0
T20	0	1333	0	0
T21	0	1838	0	0
T22	0	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3406350	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3406350	0	0
T1	40546	120	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	472	0	0
T5	1479	16	0	0
T15	55426	444	0	0
T16	187729	0	0	0
T17	3760	56	0	0
T18	87532	755	0	0
T19	289807	2420	0	0
T20	0	103143	0	0
T21	0	2321	0	0
T22	0	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1510087	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1510087	0	0
T1	40546	306	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	702	0	0
T5	1479	22	0	0
T15	55426	1004	0	0
T16	187729	0	0	0
T17	3760	74	0	0
T18	87532	611	0	0
T19	289807	6693	0	0
T21	0	1079	0	0
T22	0	107	0	0
T23	0	1953	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2615965	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2615965	0	0
T1	40546	83	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	471	0	0
T5	1479	22	0	0
T15	55426	1004	0	0
T16	187729	0	0	0
T17	3760	74	0	0
T18	87532	620	0	0
T19	289807	6744	0	0
T21	0	699	0	0
T22	0	107	0	0
T23	0	164870	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1528429	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1528429	0	0
T1	40546	241	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	559	0	0
T5	1479	23	0	0
T15	55426	1744	0	0
T16	187729	0	0	0
T17	3760	68	0	0
T18	87532	618	0	0
T19	289807	2270	0	0
T21	0	2407	0	0
T22	0	111	0	0
T24	0	598	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2729066	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2729066	0	0
T1	40546	106	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	533	0	0
T5	1479	23	0	0
T15	55426	1744	0	0
T16	187729	0	0	0
T17	3760	68	0	0
T18	87532	523	0	0
T19	289807	2151	0	0
T21	0	2502	0	0
T22	0	111	0	0
T24	0	246	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1526419	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1526419	0	0
T1	40546	273	0	0
T2	956529	0	0	0
T3	72417	2077	0	0
T4	116249	3003	0	0
T5	1479	27	0	0
T15	55426	749	0	0
T16	187729	0	0	0
T17	3760	77	0	0
T18	87532	823	0	0
T19	289807	2399	0	0
T21	0	1218	0	0
T22	0	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3662479	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3662479	0	0
T1	40546	149	0	0
T2	956529	0	0	0
T3	72417	1539	0	0
T4	116249	2007	0	0
T5	1479	27	0	0
T15	55426	749	0	0
T16	187729	0	0	0
T17	3760	77	0	0
T18	87532	790	0	0
T19	289807	2580	0	0
T21	0	515	0	0
T22	0	136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1476199	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1476199	0	0
T1	40546	294	0	0
T2	956529	0	0	0
T3	72417	2000	0	0
T4	116249	872	0	0
T5	1479	29	0	0
T15	55426	1273	0	0
T16	187729	0	0	0
T17	3760	76	0	0
T18	87532	529	0	0
T19	289807	2373	0	0
T21	0	1790	0	0
T22	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2916703	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2916703	0	0
T1	40546	142	0	0
T2	956529	0	0	0
T3	72417	1452	0	0
T4	116249	676	0	0
T5	1479	29	0	0
T15	55426	1273	0	0
T16	187729	0	0	0
T17	3760	76	0	0
T18	87532	560	0	0
T19	289807	2423	0	0
T21	0	2241	0	0
T22	0	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1507358	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1507358	0	0
T1	40546	429	0	0
T2	956529	930	0	0
T3	72417	0	0	0
T4	116249	2721	0	0
T5	1479	27	0	0
T15	55426	908	0	0
T16	187729	1209	0	0
T17	3760	63	0	0
T18	87532	677	0	0
T19	289807	2749	0	0
T21	0	2575	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3811551	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3811551	0	0
T1	40546	194	0	0
T2	956529	74067	0	0
T3	72417	0	0	0
T4	116249	1823	0	0
T5	1479	27	0	0
T15	55426	908	0	0
T16	187729	90852	0	0
T17	3760	63	0	0
T18	87532	664	0	0
T19	289807	2411	0	0
T21	0	1144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1500405	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1500405	0	0
T1	40546	387	0	0
T2	956529	0	0	0
T3	72417	3276	0	0
T4	116249	469	0	0
T5	1479	32	0	0
T15	55426	463	0	0
T16	187729	0	0	0
T17	3760	75	0	0
T18	87532	740	0	0
T19	289807	2382	0	0
T21	0	5373	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3134466	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3134466	0	0
T1	40546	149	0	0
T2	956529	0	0	0
T3	72417	3317	0	0
T4	116249	466	0	0
T5	1479	32	0	0
T15	55426	463	0	0
T16	187729	0	0	0
T17	3760	75	0	0
T18	87532	556	0	0
T19	289807	2516	0	0
T21	0	4429	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1479411	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1479411	0	0
T1	40546	211	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	471	0	0
T5	1479	28	0	0
T15	55426	445	0	0
T16	187729	0	0	0
T17	3760	78	0	0
T18	87532	551	0	0
T19	289807	2193	0	0
T20	0	1215	0	0
T21	0	2431	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	3415400	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	3415400	0	0
T1	40546	126	0	0
T2	956529	0	0	0
T3	72417	0	0	0
T4	116249	425	0	0
T5	1479	28	0	0
T15	55426	445	0	0
T16	187729	0	0	0
T17	3760	78	0	0
T18	87532	588	0	0
T19	289807	2443	0	0
T20	0	102789	0	0
T21	0	1068	0	0
T22	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	1506297	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	1506297	0	0
T1	40546	364	0	0
T2	956529	0	0	0
T3	72417	1711	0	0
T4	116249	619	0	0
T5	1479	23	0	0
T15	55426	896	0	0
T16	187729	0	0	0
T17	3760	69	0	0
T18	87532	681	0	0
T19	289807	2514	0	0
T21	0	2053	0	0
T22	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	307721509	2759603	0	0
DepthKnown_A	307721509	307606644	0	0
RvalidKnown_A	307721509	307606644	0	0
WreadyKnown_A	307721509	307606644	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	2759603	0	0
T1	40546	140	0	0
T2	956529	0	0	0
T3	72417	1172	0	0
T4	116249	468	0	0
T5	1479	23	0	0
T15	55426	896	0	0
T16	187729	0	0	0
T17	3760	69	0	0
T18	87532	641	0	0
T19	289807	2307	0	0
T21	0	2911	0	0
T22	0	97	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307721509	307606644	0	0
T1	40546	40513	0	0
T2	956529	956510	0	0
T3	72417	72396	0	0
T4	116249	116090	0	0
T5	1479	1454	0	0
T15	55426	54789	0	0
T16	187729	187728	0	0
T17	3760	3730	0	0
T18	87532	87482	0	0
T19	289807	289742	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0