Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1720123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

270494

1

T1

366

T2

295

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	673210	1			T1	836		T2	793		T3	51
values[0x0]	642648	1			T1	918		T2	766		T3	51
values[0x1]	674759	1			T1	900		T2	776		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1332455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

658162

1

T1

874

T2

778

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7299	1			T2	12		T15	9		T16	3
valid_sources[0x01]	8314	1			T2	12		T3	1		T15	4
valid_sources[0x02]	6898	1			T2	5		T3	2		T15	3
valid_sources[0x03]	7345	1			T1	5		T2	7		T3	2
valid_sources[0x04]	8298	1			T2	13		T15	2		T16	7
valid_sources[0x05]	7522	1			T2	14		T3	1		T15	5
valid_sources[0x06]	8554	1			T1	3		T2	19		T3	2
valid_sources[0x07]	7481	1			T2	11		T14	2		T15	11
valid_sources[0x08]	8320	1			T1	4		T2	28		T15	8
valid_sources[0x09]	7784	1			T2	10		T15	2		T16	1
valid_sources[0x0a]	8138	1			T2	17		T3	1		T15	2
valid_sources[0x0b]	7917	1			T1	78		T2	3		T3	1
valid_sources[0x0c]	7112	1			T2	10		T3	1		T15	2
valid_sources[0x0d]	7876	1			T2	6		T3	1		T15	3
valid_sources[0x0e]	7598	1			T2	22		T3	2		T15	10
valid_sources[0x0f]	7052	1			T2	11		T3	2		T15	12
valid_sources[0x10]	8003	1			T1	4		T2	22		T3	1
valid_sources[0x11]	8716	1			T2	10		T3	1		T15	11
valid_sources[0x12]	7531	1			T2	10		T15	1		T16	3
valid_sources[0x13]	7201	1			T2	4		T14	1		T15	4
valid_sources[0x14]	8336	1			T1	41		T2	7		T3	2
valid_sources[0x15]	6883	1			T1	4		T2	10		T15	5
valid_sources[0x16]	8362	1			T1	5		T2	6		T3	1
valid_sources[0x17]	7361	1			T1	3		T2	4		T3	1
valid_sources[0x18]	7868	1			T1	25		T2	12		T15	5
valid_sources[0x19]	7130	1			T2	3		T3	1		T14	2
valid_sources[0x1a]	8229	1			T1	34		T2	5		T3	1
valid_sources[0x1b]	7550	1			T2	7		T14	1		T15	3
valid_sources[0x1c]	8219	1			T1	5		T2	15		T3	1
valid_sources[0x1d]	7351	1			T1	3		T2	10		T15	7
valid_sources[0x1e]	8250	1			T2	12		T3	3		T15	2
valid_sources[0x1f]	7324	1			T2	5		T3	3		T15	5
valid_sources[0x20]	7370	1			T1	3		T2	14		T3	2
valid_sources[0x21]	7785	1			T1	48		T2	2		T13	1
valid_sources[0x22]	8897	1			T2	7		T15	2		T13	3
valid_sources[0x23]	7778	1			T2	11		T15	4		T13	1
valid_sources[0x24]	7727	1			T2	9		T3	1		T15	5
valid_sources[0x25]	7277	1			T1	17		T2	3		T15	2
valid_sources[0x26]	7177	1			T2	13		T14	1		T15	3
valid_sources[0x27]	8428	1			T1	18		T2	16		T3	1
valid_sources[0x28]	7601	1			T1	23		T2	5		T15	1
valid_sources[0x29]	7890	1			T2	10		T15	4		T16	2
valid_sources[0x2a]	7856	1			T2	3		T14	1		T15	7
valid_sources[0x2b]	8755	1			T1	39		T2	12		T15	2
valid_sources[0x2c]	7737	1			T2	6		T15	3		T16	7
valid_sources[0x2d]	7575	1			T1	20		T2	5		T15	7
valid_sources[0x2e]	7906	1			T1	3		T2	9		T3	1
valid_sources[0x2f]	7396	1			T2	4		T14	1		T16	5
valid_sources[0x30]	7790	1			T1	29		T2	5		T14	1
valid_sources[0x31]	7010	1			T2	12		T15	9		T16	5
valid_sources[0x32]	7357	1			T2	10		T3	1		T15	2
valid_sources[0x33]	7419	1			T1	13		T2	12		T3	3
valid_sources[0x34]	7389	1			T2	6		T3	1		T15	4
valid_sources[0x35]	7207	1			T2	12		T14	1		T15	9
valid_sources[0x36]	7325	1			T2	4		T14	1		T15	3
valid_sources[0x37]	8214	1			T2	15		T3	1		T15	1
valid_sources[0x38]	8481	1			T2	8		T3	2		T14	2
valid_sources[0x39]	7686	1			T1	23		T2	15		T16	4
valid_sources[0x3a]	7567	1			T1	27		T2	11		T15	9
valid_sources[0x3b]	7873	1			T1	56		T2	9		T15	9
valid_sources[0x3c]	7721	1			T1	41		T2	3		T14	1
valid_sources[0x3d]	7542	1			T2	8		T3	2		T15	8
valid_sources[0x3e]	7393	1			T1	35		T2	13		T3	1
valid_sources[0x3f]	7010	1			T1	3		T2	18		T15	2
valid_sources[0x40]	7591	1			T2	2		T15	3		T13	1
valid_sources[0x41]	7229	1			T1	2		T2	7		T3	1
valid_sources[0x42]	8352	1			T1	1		T2	2		T3	1
valid_sources[0x43]	7153	1			T1	1		T2	4		T15	7
valid_sources[0x44]	6942	1			T2	18		T15	9		T16	1
valid_sources[0x45]	7924	1			T2	13		T3	2		T15	4
valid_sources[0x46]	7584	1			T2	10		T3	1		T15	6
valid_sources[0x47]	8080	1			T2	9		T6	25		T20	7
valid_sources[0x48]	8558	1			T2	15		T15	1		T16	3
valid_sources[0x49]	7957	1			T1	39		T2	3		T3	2
valid_sources[0x4a]	7840	1			T1	8		T2	9		T3	1
valid_sources[0x4b]	7374	1			T1	54		T2	7		T15	3
valid_sources[0x4c]	7158	1			T2	5		T3	2		T15	1
valid_sources[0x4d]	8072	1			T1	9		T2	16		T15	4
valid_sources[0x4e]	7589	1			T1	67		T2	4		T3	2
valid_sources[0x4f]	8930	1			T1	11		T2	5		T3	4
valid_sources[0x50]	7741	1			T2	6		T15	3		T13	1
valid_sources[0x51]	8114	1			T2	6		T15	1		T6	35
valid_sources[0x52]	7042	1			T1	12		T2	20		T3	1
valid_sources[0x53]	6984	1			T1	3		T2	5		T3	2
valid_sources[0x54]	7926	1			T1	49		T2	3		T14	1
valid_sources[0x55]	7709	1			T2	5		T3	2		T15	2
valid_sources[0x56]	8937	1			T1	3		T2	3		T15	4
valid_sources[0x57]	7415	1			T1	4		T2	13		T3	1
valid_sources[0x58]	7720	1			T2	7		T14	1		T15	7
valid_sources[0x59]	7665	1			T1	6		T2	11		T3	1
valid_sources[0x5a]	8220	1			T1	9		T2	2		T15	6
valid_sources[0x5b]	7060	1			T1	38		T2	4		T14	1
valid_sources[0x5c]	8020	1			T2	7		T14	1		T15	4
valid_sources[0x5d]	7731	1			T2	9		T3	1		T15	6
valid_sources[0x5e]	8646	1			T1	23		T2	7		T3	1
valid_sources[0x5f]	9634	1			T2	7		T15	5		T16	6
valid_sources[0x60]	7919	1			T1	19		T2	5		T14	1
valid_sources[0x61]	6693	1			T2	22		T3	1		T14	1
valid_sources[0x62]	6807	1			T2	3		T15	4		T16	5
valid_sources[0x63]	8280	1			T2	8		T15	3		T13	13
valid_sources[0x64]	7884	1			T2	6		T15	3		T13	1
valid_sources[0x65]	7748	1			T2	3		T15	4		T16	6
valid_sources[0x66]	8162	1			T2	8		T15	5		T16	2
valid_sources[0x67]	7521	1			T2	7		T14	1		T15	6
valid_sources[0x68]	7469	1			T2	11		T15	2		T13	14
valid_sources[0x69]	7710	1			T1	6		T2	4		T14	1
valid_sources[0x6a]	7697	1			T2	7		T14	1		T15	5
valid_sources[0x6b]	7591	1			T2	5		T15	8		T16	4
valid_sources[0x6c]	8135	1			T1	2		T2	8		T15	11
valid_sources[0x6d]	7505	1			T1	2		T2	12		T15	2
valid_sources[0x6e]	6984	1			T2	2		T3	2		T15	11
valid_sources[0x6f]	9296	1			T1	57		T2	1		T15	4
valid_sources[0x70]	7605	1			T1	79		T2	8		T3	2
valid_sources[0x71]	8494	1			T2	17		T15	8		T16	1
valid_sources[0x72]	7989	1			T1	41		T2	9		T14	1
valid_sources[0x73]	8073	1			T2	14		T14	1		T15	3
valid_sources[0x74]	8040	1			T1	92		T2	4		T15	5
valid_sources[0x75]	7720	1			T2	17		T14	1		T15	4
valid_sources[0x76]	7442	1			T1	6		T2	9		T3	1
valid_sources[0x77]	7704	1			T2	4		T14	1		T15	3
valid_sources[0x78]	7327	1			T2	12		T3	2		T15	10
valid_sources[0x79]	7596	1			T2	7		T3	1		T15	5
valid_sources[0x7a]	8477	1			T2	13		T15	3		T16	1
valid_sources[0x7b]	7238	1			T2	10		T15	5		T16	2
valid_sources[0x7c]	8182	1			T2	9		T3	1		T15	5
valid_sources[0x7d]	7889	1			T2	2		T3	1		T14	1
valid_sources[0x7e]	7370	1			T1	1		T2	8		T14	2
valid_sources[0x7f]	7124	1			T1	44		T2	20		T3	1
valid_sources[0x80]	7170	1			T2	7		T15	1		T6	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28528

1

T1

40

T2

30

T3

1

values[0x0]

all_enables

biggest_size

213419

1

T1

293

T2

237

T3

13

values[0x1]

all_enables

biggest_size

28547

1

T1

33

T2

28

T14

7