Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	349621505	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	349621505	0	0
T1	20137152	2464583	0	0
T2	11415936	1605795	0	0
T3	10828160	266486	0	0
T6	9935408	196078	0	0
T13	1261736	55878	0	0
T14	218792	7039	0	0
T15	122248	5418	0	0
T16	101920	4196	0	0
T17	28056	962	0	0
T18	28392	811	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20137152	20137096	0	0
T2	11415936	11415768	0	0
T3	10828160	10824912	0	0
T6	9935408	9904720	0	0
T13	1261736	1255856	0	0
T14	218792	215320	0	0
T15	122248	121856	0	0
T16	101920	100520	0	0
T17	28056	27160	0	0
T18	28392	27104	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20137152	20137096	0	0
T2	11415936	11415768	0	0
T3	10828160	10824912	0	0
T6	9935408	9904720	0	0
T13	1261736	1255856	0	0
T14	218792	215320	0	0
T15	122248	121856	0	0
T16	101920	100520	0	0
T17	28056	27160	0	0
T18	28392	27104	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	20137152	20137096	0	0
T2	11415936	11415768	0	0
T3	10828160	10824912	0	0
T6	9935408	9904720	0	0
T13	1261736	1255856	0	0
T14	218792	215320	0	0
T15	122248	121856	0	0
T16	101920	100520	0	0
T17	28056	27160	0	0
T18	28392	27104	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T6	56	56	0	0
T13	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	127868170	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	127868170	0	0
T1	359592	171840	0	0
T2	203856	201103	0	0
T3	193360	109381	0	0
T6	177418	88178	0	0
T13	22531	21663	0	0
T14	3907	3443	0	0
T15	2183	2096	0	0
T16	1820	1628	0	0
T17	501	374	0	0
T18	507	313	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	90429874	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	90429874	0	0
T1	359592	679016	0	0
T2	203856	697955	0	0
T3	193360	55041	0	0
T6	177418	26340	0	0
T13	22531	12495	0	0
T14	3907	1760	0	0
T15	2183	1108	0	0
T16	1820	856	0	0
T17	501	196	0	0
T18	507	166	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1516953	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1516953	0	0
T1	359592	30944	0	0
T2	203856	353	0	0
T3	193360	800	0	0
T6	177418	3952	0	0
T13	22531	255	0	0
T14	3907	33	0	0
T15	2183	44	0	0
T16	1820	35	0	0
T17	501	2	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3024688	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3024688	0	0
T1	359592	27236	0	0
T2	203856	27921	0	0
T3	193360	1087	0	0
T6	177418	1590	0	0
T13	22531	255	0	0
T14	3907	33	0	0
T15	2183	44	0	0
T16	1820	35	0	0
T17	501	2	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1574252	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1574252	0	0
T1	359592	28306	0	0
T2	203856	396	0	0
T3	193360	1550	0	0
T6	177418	2307	0	0
T13	22531	250	0	0
T14	3907	50	0	0
T15	2183	35	0	0
T16	1820	32	0	0
T17	501	4	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3451824	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3451824	0	0
T1	359592	18896	0	0
T2	203856	28767	0	0
T3	193360	1687	0	0
T6	177418	1104	0	0
T13	22531	250	0	0
T14	3907	50	0	0
T15	2183	35	0	0
T16	1820	32	0	0
T17	501	4	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1590424	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1590424	0	0
T1	359592	32226	0	0
T2	203856	407	0	0
T3	193360	2155	0	0
T6	177418	1613	0	0
T13	22531	529	0	0
T14	3907	31	0	0
T15	2183	56	0	0
T16	1820	45	0	0
T17	501	9	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3830188	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3830188	0	0
T1	359592	25170	0	0
T2	203856	24185	0	0
T3	193360	1290	0	0
T6	177418	735	0	0
T13	22531	529	0	0
T14	3907	31	0	0
T15	2183	56	0	0
T16	1820	45	0	0
T17	501	9	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1612876	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1612876	0	0
T1	359592	37901	0	0
T2	203856	355	0	0
T3	193360	2518	0	0
T6	177418	1527	0	0
T13	22531	493	0	0
T14	3907	30	0	0
T15	2183	36	0	0
T16	1820	41	0	0
T17	501	5	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3545895	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3545895	0	0
T1	359592	32839	0	0
T2	203856	26487	0	0
T3	193360	3060	0	0
T6	177418	761	0	0
T13	22531	493	0	0
T14	3907	30	0	0
T15	2183	36	0	0
T16	1820	41	0	0
T17	501	5	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1547248	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1547248	0	0
T1	359592	30908	0	0
T2	203856	381	0	0
T3	193360	2018	0	0
T6	177418	1543	0	0
T13	22531	488	0	0
T14	3907	29	0	0
T15	2183	34	0	0
T16	1820	36	0	0
T17	501	9	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3088405	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3088405	0	0
T1	359592	23485	0	0
T2	203856	29563	0	0
T3	193360	1390	0	0
T6	177418	721	0	0
T13	22531	488	0	0
T14	3907	29	0	0
T15	2183	34	0	0
T16	1820	36	0	0
T17	501	9	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1582525	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1582525	0	0
T1	359592	35430	0	0
T2	203856	366	0	0
T3	193360	2871	0	0
T6	177418	1710	0	0
T13	22531	756	0	0
T14	3907	28	0	0
T15	2183	37	0	0
T16	1820	38	0	0
T17	501	6	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3334704	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3334704	0	0
T1	359592	28799	0	0
T2	203856	24481	0	0
T3	193360	2294	0	0
T6	177418	755	0	0
T13	22531	756	0	0
T14	3907	28	0	0
T15	2183	37	0	0
T16	1820	38	0	0
T17	501	6	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1550132	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1550132	0	0
T1	359592	36574	0	0
T2	203856	394	0	0
T3	193360	653	0	0
T6	177418	3129	0	0
T13	22531	246	0	0
T14	3907	30	0	0
T15	2183	50	0	0
T16	1820	33	0	0
T17	501	5	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3042364	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3042364	0	0
T1	359592	25132	0	0
T2	203856	28531	0	0
T3	193360	1084	0	0
T6	177418	1355	0	0
T13	22531	246	0	0
T14	3907	30	0	0
T15	2183	50	0	0
T16	1820	33	0	0
T17	501	5	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1542894	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1542894	0	0
T1	359592	36478	0	0
T2	203856	355	0	0
T3	193360	1739	0	0
T6	177418	3512	0	0
T13	22531	248	0	0
T14	3907	25	0	0
T15	2183	37	0	0
T16	1820	26	0	0
T17	501	10	0	0
T18	507	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	4399826	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	4399826	0	0
T1	359592	24831	0	0
T2	203856	26850	0	0
T3	193360	2675	0	0
T6	177418	1530	0	0
T13	22531	248	0	0
T14	3907	25	0	0
T15	2183	37	0	0
T16	1820	26	0	0
T17	501	10	0	0
T18	507	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1562685	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1562685	0	0
T1	359592	30994	0	0
T2	203856	375	0	0
T3	193360	1379	0	0
T6	177418	3387	0	0
T13	22531	546	0	0
T14	3907	37	0	0
T15	2183	40	0	0
T16	1820	33	0	0
T17	501	16	0	0
T18	507	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2647092	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2647092	0	0
T1	359592	23693	0	0
T2	203856	25860	0	0
T3	193360	801	0	0
T6	177418	1748	0	0
T13	22531	546	0	0
T14	3907	37	0	0
T15	2183	40	0	0
T16	1820	33	0	0
T17	501	16	0	0
T18	507	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1556461	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1556461	0	0
T1	359592	38152	0	0
T2	203856	404	0	0
T3	193360	1816	0	0
T6	177418	1834	0	0
T13	22531	1125	0	0
T14	3907	35	0	0
T15	2183	42	0	0
T16	1820	26	0	0
T17	501	9	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2962965	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2962965	0	0
T1	359592	21289	0	0
T2	203856	27611	0	0
T3	193360	2555	0	0
T6	177418	785	0	0
T13	22531	1125	0	0
T14	3907	35	0	0
T15	2183	42	0	0
T16	1820	26	0	0
T17	501	9	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1535153	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1535153	0	0
T1	359592	39048	0	0
T2	203856	354	0	0
T3	193360	2264	0	0
T6	177418	1667	0	0
T13	22531	505	0	0
T14	3907	39	0	0
T15	2183	36	0	0
T16	1820	36	0	0
T17	501	5	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3944543	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3944543	0	0
T1	359592	31140	0	0
T2	203856	29223	0	0
T3	193360	1655	0	0
T6	177418	832	0	0
T13	22531	505	0	0
T14	3907	39	0	0
T15	2183	36	0	0
T16	1820	36	0	0
T17	501	5	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1552366	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1552366	0	0
T1	359592	32298	0	0
T2	203856	287	0	0
T3	193360	2929	0	0
T6	177418	1821	0	0
T13	22531	235	0	0
T14	3907	37	0	0
T15	2183	50	0	0
T16	1820	33	0	0
T17	501	8	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2857922	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2857922	0	0
T1	359592	22923	0	0
T2	203856	22641	0	0
T3	193360	2581	0	0
T6	177418	818	0	0
T13	22531	235	0	0
T14	3907	37	0	0
T15	2183	50	0	0
T16	1820	33	0	0
T17	501	8	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1584224	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1584224	0	0
T1	359592	34022	0	0
T2	203856	337	0	0
T3	193360	1608	0	0
T6	177418	2245	0	0
T13	22531	257	0	0
T14	3907	32	0	0
T15	2183	50	0	0
T16	1820	35	0	0
T17	501	8	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	4242316	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	4242316	0	0
T1	359592	24673	0	0
T2	203856	25428	0	0
T3	193360	1364	0	0
T6	177418	1109	0	0
T13	22531	257	0	0
T14	3907	32	0	0
T15	2183	50	0	0
T16	1820	35	0	0
T17	501	8	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1536653	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1536653	0	0
T1	359592	43979	0	0
T2	203856	342	0	0
T3	193360	1676	0	0
T6	177418	1527	0	0
T13	22531	225	0	0
T14	3907	40	0	0
T15	2183	29	0	0
T16	1820	19	0	0
T17	501	5	0	0
T18	507	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3128321	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3128321	0	0
T1	359592	27785	0	0
T2	203856	25251	0	0
T3	193360	1518	0	0
T6	177418	696	0	0
T13	22531	225	0	0
T14	3907	40	0	0
T15	2183	29	0	0
T16	1820	19	0	0
T17	501	5	0	0
T18	507	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1556371	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1556371	0	0
T1	359592	35475	0	0
T2	203856	333	0	0
T3	193360	1457	0	0
T6	177418	1737	0	0
T13	22531	234	0	0
T14	3907	34	0	0
T15	2183	50	0	0
T16	1820	27	0	0
T17	501	8	0	0
T18	507	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2398078	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2398078	0	0
T1	359592	20312	0	0
T2	203856	21292	0	0
T3	193360	2224	0	0
T6	177418	722	0	0
T13	22531	234	0	0
T14	3907	34	0	0
T15	2183	50	0	0
T16	1820	27	0	0
T17	501	8	0	0
T18	507	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1570358	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1570358	0	0
T1	359592	33718	0	0
T2	203856	384	0	0
T3	193360	474	0	0
T6	177418	1460	0	0
T13	22531	516	0	0
T14	3907	39	0	0
T15	2183	41	0	0
T16	1820	23	0	0
T17	501	12	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3001819	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3001819	0	0
T1	359592	21486	0	0
T2	203856	26905	0	0
T3	193360	2271	0	0
T6	177418	673	0	0
T13	22531	516	0	0
T14	3907	39	0	0
T15	2183	41	0	0
T16	1820	23	0	0
T17	501	12	0	0
T18	507	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1586327	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1586327	0	0
T1	359592	40802	0	0
T2	203856	309	0	0
T3	193360	2669	0	0
T6	177418	1664	0	0
T13	22531	262	0	0
T14	3907	40	0	0
T15	2183	53	0	0
T16	1820	28	0	0
T17	501	7	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3922327	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3922327	0	0
T1	359592	30197	0	0
T2	203856	18097	0	0
T3	193360	2273	0	0
T6	177418	655	0	0
T13	22531	262	0	0
T14	3907	40	0	0
T15	2183	53	0	0
T16	1820	28	0	0
T17	501	7	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1513860	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1513860	0	0
T1	359592	35669	0	0
T2	203856	372	0	0
T3	193360	2565	0	0
T6	177418	1916	0	0
T13	22531	483	0	0
T14	3907	31	0	0
T15	2183	35	0	0
T16	1820	33	0	0
T17	501	4	0	0
T18	507	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3553751	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3553751	0	0
T1	359592	28094	0	0
T2	203856	27196	0	0
T3	193360	3437	0	0
T6	177418	823	0	0
T13	22531	483	0	0
T14	3907	31	0	0
T15	2183	35	0	0
T16	1820	33	0	0
T17	501	4	0	0
T18	507	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1554164	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1554164	0	0
T1	359592	34547	0	0
T2	203856	458	0	0
T3	193360	927	0	0
T6	177418	3366	0	0
T13	22531	249	0	0
T14	3907	35	0	0
T15	2183	26	0	0
T16	1820	18	0	0
T17	501	8	0	0
T18	507	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3644383	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3644383	0	0
T1	359592	25813	0	0
T2	203856	28837	0	0
T3	193360	1468	0	0
T6	177418	1319	0	0
T13	22531	249	0	0
T14	3907	35	0	0
T15	2183	26	0	0
T16	1820	18	0	0
T17	501	8	0	0
T18	507	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1489650	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1489650	0	0
T1	359592	33980	0	0
T2	203856	361	0	0
T3	193360	2063	0	0
T6	177418	1762	0	0
T13	22531	281	0	0
T14	3907	31	0	0
T15	2183	42	0	0
T16	1820	27	0	0
T17	501	11	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3305003	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3305003	0	0
T1	359592	27919	0	0
T2	203856	23225	0	0
T3	193360	3255	0	0
T6	177418	758	0	0
T13	22531	281	0	0
T14	3907	31	0	0
T15	2183	42	0	0
T16	1820	27	0	0
T17	501	11	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1545381	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1545381	0	0
T1	359592	36372	0	0
T2	203856	354	0	0
T3	193360	636	0	0
T6	177418	1726	0	0
T13	22531	265	0	0
T14	3907	36	0	0
T15	2183	44	0	0
T16	1820	24	0	0
T17	501	7	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2240455	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2240455	0	0
T1	359592	25672	0	0
T2	203856	28088	0	0
T3	193360	1660	0	0
T6	177418	834	0	0
T13	22531	265	0	0
T14	3907	36	0	0
T15	2183	44	0	0
T16	1820	24	0	0
T17	501	7	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1533671	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1533671	0	0
T1	359592	32432	0	0
T2	203856	449	0	0
T3	193360	931	0	0
T6	177418	1725	0	0
T13	22531	461	0	0
T14	3907	33	0	0
T15	2183	39	0	0
T16	1820	39	0	0
T17	501	10	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3459652	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3459652	0	0
T1	359592	28629	0	0
T2	203856	23132	0	0
T3	193360	2317	0	0
T6	177418	776	0	0
T13	22531	461	0	0
T14	3907	33	0	0
T15	2183	39	0	0
T16	1820	39	0	0
T17	501	10	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1554192	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1554192	0	0
T1	359592	31774	0	0
T2	203856	304	0	0
T3	193360	2135	0	0
T6	177418	1733	0	0
T13	22531	231	0	0
T14	3907	46	0	0
T15	2183	43	0	0
T16	1820	39	0	0
T17	501	4	0	0
T18	507	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3816842	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3816842	0	0
T1	359592	23654	0	0
T2	203856	21987	0	0
T3	193360	2191	0	0
T6	177418	752	0	0
T13	22531	231	0	0
T14	3907	46	0	0
T15	2183	43	0	0
T16	1820	39	0	0
T17	501	4	0	0
T18	507	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1562668	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1562668	0	0
T1	359592	37587	0	0
T2	203856	370	0	0
T3	193360	831	0	0
T6	177418	1655	0	0
T13	22531	740	0	0
T14	3907	31	0	0
T15	2183	32	0	0
T16	1820	31	0	0
T17	501	3	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3388451	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3388451	0	0
T1	359592	25642	0	0
T2	203856	25513	0	0
T3	193360	2452	0	0
T6	177418	715	0	0
T13	22531	740	0	0
T14	3907	31	0	0
T15	2183	32	0	0
T16	1820	31	0	0
T17	501	3	0	0
T18	507	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1607613	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1607613	0	0
T1	359592	33609	0	0
T2	203856	429	0	0
T3	193360	2235	0	0
T6	177418	2222	0	0
T13	22531	461	0	0
T14	3907	29	0	0
T15	2183	47	0	0
T16	1820	33	0	0
T17	501	10	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3609125	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3609125	0	0
T1	359592	23089	0	0
T2	203856	27371	0	0
T3	193360	1841	0	0
T6	177418	1019	0	0
T13	22531	461	0	0
T14	3907	29	0	0
T15	2183	47	0	0
T16	1820	33	0	0
T17	501	10	0	0
T18	507	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1503723	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1503723	0	0
T1	359592	29392	0	0
T2	203856	330	0	0
T3	193360	2290	0	0
T6	177418	1953	0	0
T13	22531	253	0	0
T14	3907	37	0	0
T15	2183	48	0	0
T16	1820	34	0	0
T17	501	7	0	0
T18	507	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	3012281	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	3012281	0	0
T1	359592	19216	0	0
T2	203856	27229	0	0
T3	193360	2605	0	0
T6	177418	890	0	0
T13	22531	253	0	0
T14	3907	37	0	0
T15	2183	48	0	0
T16	1820	34	0	0
T17	501	7	0	0
T18	507	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	1495835	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	1495835	0	0
T1	359592	32095	0	0
T2	203856	312	0	0
T3	193360	1834	0	0
T6	177418	1662	0	0
T13	22531	266	0	0
T14	3907	20	0	0
T15	2183	31	0	0
T16	1820	32	0	0
T17	501	4	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	315312268	2551582	0	0
DepthKnown_A	315312268	315184492	0	0
RvalidKnown_A	315312268	315184492	0	0
WreadyKnown_A	315312268	315184492	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	2551582	0	0
T1	359592	21401	0	0
T2	203856	25195	0	0
T3	193360	2006	0	0
T6	177418	730	0	0
T13	22531	266	0	0
T14	3907	20	0	0
T15	2183	31	0	0
T16	1820	32	0	0
T17	501	4	0	0
T18	507	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315312268	315184492	0	0
T1	359592	359591	0	0
T2	203856	203853	0	0
T3	193360	193302	0	0
T6	177418	176870	0	0
T13	22531	22426	0	0
T14	3907	3845	0	0
T15	2183	2176	0	0
T16	1820	1795	0	0
T17	501	485	0	0
T18	507	484	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0