Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1637193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258595

1

T1

20

T2

23

T3

68

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	641100	1			T1	49		T2	53		T3	178
values[0x0]	614530	1			T1	34		T2	61		T3	170
values[0x1]	640158	1			T1	56		T2	47		T3	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1269430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

626358

1

T1

44

T2

54

T3

162

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8640	1			T17	5		T22	30		T23	2
valid_sources[0x01]	6696	1			T17	4		T22	20		T20	38
valid_sources[0x02]	6844	1			T17	3		T23	1		T20	60
valid_sources[0x03]	7180	1			T17	2		T20	56		T18	21
valid_sources[0x04]	7006	1			T17	3		T23	1		T20	57
valid_sources[0x05]	7098	1			T17	2		T22	49		T20	75
valid_sources[0x06]	6882	1			T17	3		T23	1		T20	47
valid_sources[0x07]	7719	1			T17	3		T22	7		T20	64
valid_sources[0x08]	7139	1			T3	19		T17	3		T22	10
valid_sources[0x09]	7161	1			T4	5		T19	1		T17	3
valid_sources[0x0a]	7103	1			T2	1		T17	4		T22	9
valid_sources[0x0b]	6663	1			T17	3		T22	13		T23	1
valid_sources[0x0c]	7584	1			T3	15		T17	3		T20	46
valid_sources[0x0d]	7510	1			T17	3		T20	59		T21	3
valid_sources[0x0e]	7107	1			T17	3		T20	91		T21	2
valid_sources[0x0f]	6954	1			T19	1		T17	3		T23	2
valid_sources[0x10]	8195	1			T17	3		T22	5		T23	4
valid_sources[0x11]	7610	1			T3	25		T17	3		T22	12
valid_sources[0x12]	7251	1			T17	4		T22	19		T23	2
valid_sources[0x13]	7135	1			T19	1		T17	3		T22	15
valid_sources[0x14]	7358	1			T17	3		T22	13		T23	1
valid_sources[0x15]	6864	1			T17	3		T22	13		T20	35
valid_sources[0x16]	7209	1			T3	4		T17	3		T22	25
valid_sources[0x17]	8778	1			T3	3		T17	3		T22	10
valid_sources[0x18]	6822	1			T17	3		T22	6		T23	3
valid_sources[0x19]	6887	1			T17	3		T22	10		T23	3
valid_sources[0x1a]	6462	1			T19	1		T17	3		T22	31
valid_sources[0x1b]	7119	1			T4	2		T17	3		T23	2
valid_sources[0x1c]	7591	1			T17	3		T22	32		T20	35
valid_sources[0x1d]	7249	1			T17	2		T20	44		T18	9
valid_sources[0x1e]	7109	1			T17	3		T22	15		T23	1
valid_sources[0x1f]	6829	1			T2	11		T17	3		T23	4
valid_sources[0x20]	7004	1			T17	2		T23	3		T20	59
valid_sources[0x21]	8232	1			T4	5		T19	2		T17	2
valid_sources[0x22]	7827	1			T2	9		T17	3		T22	18
valid_sources[0x23]	7075	1			T4	2		T17	3		T20	37
valid_sources[0x24]	6582	1			T17	3		T22	20		T23	2
valid_sources[0x25]	7860	1			T17	3		T23	2		T20	78
valid_sources[0x26]	7985	1			T17	2		T22	41		T23	2
valid_sources[0x27]	7092	1			T17	2		T22	17		T23	1
valid_sources[0x28]	7329	1			T17	3		T23	1		T20	37
valid_sources[0x29]	7030	1			T19	2		T17	4		T20	63
valid_sources[0x2a]	7461	1			T19	3		T17	3		T22	8
valid_sources[0x2b]	7360	1			T19	2		T17	2		T23	1
valid_sources[0x2c]	8678	1			T17	2		T20	61		T18	11
valid_sources[0x2d]	6964	1			T17	3		T22	20		T23	4
valid_sources[0x2e]	7072	1			T1	52		T19	2		T17	3
valid_sources[0x2f]	6922	1			T3	5		T19	1		T17	3
valid_sources[0x30]	8177	1			T17	3		T22	11		T23	1
valid_sources[0x31]	7150	1			T17	4		T23	1		T20	44
valid_sources[0x32]	8476	1			T17	3		T23	2		T20	48
valid_sources[0x33]	8181	1			T4	2		T17	4		T22	19
valid_sources[0x34]	7574	1			T3	11		T17	3		T22	15
valid_sources[0x35]	8972	1			T17	3		T22	9		T23	1
valid_sources[0x36]	7782	1			T17	3		T22	19		T23	1
valid_sources[0x37]	7105	1			T17	2		T22	11		T23	1
valid_sources[0x38]	7271	1			T17	3		T23	1		T20	44
valid_sources[0x39]	7760	1			T1	26		T19	1		T17	3
valid_sources[0x3a]	8235	1			T3	21		T17	3		T23	1
valid_sources[0x3b]	7562	1			T19	1		T17	2		T22	15
valid_sources[0x3c]	7516	1			T3	2		T4	1		T17	3
valid_sources[0x3d]	7216	1			T17	3		T22	8		T23	3
valid_sources[0x3e]	6608	1			T17	3		T20	38		T21	7
valid_sources[0x3f]	6143	1			T19	1		T17	3		T22	15
valid_sources[0x40]	6630	1			T17	4		T22	10		T23	1
valid_sources[0x41]	7878	1			T1	9		T4	4		T17	3
valid_sources[0x42]	6717	1			T2	1		T17	3		T22	10
valid_sources[0x43]	8514	1			T17	4		T23	1		T20	72
valid_sources[0x44]	6997	1			T19	1		T17	3		T22	5
valid_sources[0x45]	6890	1			T19	1		T17	3		T23	1
valid_sources[0x46]	7975	1			T17	4		T22	17		T23	1
valid_sources[0x47]	6683	1			T4	1		T17	3		T23	1
valid_sources[0x48]	7882	1			T17	3		T22	8		T23	1
valid_sources[0x49]	7189	1			T19	1		T17	3		T20	67
valid_sources[0x4a]	6593	1			T17	3		T23	2		T20	34
valid_sources[0x4b]	8138	1			T2	3		T17	3		T23	1
valid_sources[0x4c]	6923	1			T17	3		T22	16		T23	1
valid_sources[0x4d]	8058	1			T4	1		T19	1		T17	2
valid_sources[0x4e]	7272	1			T4	1		T17	3		T22	7
valid_sources[0x4f]	6690	1			T1	44		T3	20		T19	1
valid_sources[0x50]	7449	1			T4	2		T17	3		T23	3
valid_sources[0x51]	7562	1			T4	5		T17	3		T22	7
valid_sources[0x52]	7403	1			T2	7		T17	3		T22	11
valid_sources[0x53]	7367	1			T17	2		T23	1		T20	46
valid_sources[0x54]	7031	1			T17	3		T22	27		T20	42
valid_sources[0x55]	6774	1			T3	15		T17	3		T22	5
valid_sources[0x56]	6644	1			T19	2		T17	2		T22	7
valid_sources[0x57]	6374	1			T17	3		T22	58		T23	1
valid_sources[0x58]	7220	1			T3	35		T17	3		T23	2
valid_sources[0x59]	8001	1			T17	4		T22	7		T23	3
valid_sources[0x5a]	7657	1			T3	31		T17	3		T22	32
valid_sources[0x5b]	6994	1			T4	2		T17	3		T22	10
valid_sources[0x5c]	6968	1			T4	4		T17	3		T22	29
valid_sources[0x5d]	7335	1			T17	4		T22	9		T20	55
valid_sources[0x5e]	6746	1			T3	15		T4	1		T19	1
valid_sources[0x5f]	7383	1			T17	2		T22	10		T23	1
valid_sources[0x60]	7860	1			T17	3		T23	6		T20	30
valid_sources[0x61]	7900	1			T17	3		T22	13		T20	48
valid_sources[0x62]	7176	1			T17	3		T22	14		T20	73
valid_sources[0x63]	7467	1			T19	1		T17	3		T22	20
valid_sources[0x64]	8215	1			T19	1		T17	2		T22	7
valid_sources[0x65]	8171	1			T17	4		T22	19		T20	61
valid_sources[0x66]	6768	1			T4	2		T17	3		T22	30
valid_sources[0x67]	7368	1			T3	2		T4	4		T17	3
valid_sources[0x68]	7487	1			T19	1		T17	3		T23	3
valid_sources[0x69]	8228	1			T17	2		T23	1		T20	38
valid_sources[0x6a]	6977	1			T4	1		T17	4		T23	2
valid_sources[0x6b]	7245	1			T17	3		T22	10		T23	2
valid_sources[0x6c]	7884	1			T17	3		T22	16		T20	49
valid_sources[0x6d]	6808	1			T17	2		T23	1		T20	35
valid_sources[0x6e]	7873	1			T19	1		T17	3		T23	3
valid_sources[0x6f]	7093	1			T2	2		T17	3		T22	11
valid_sources[0x70]	7603	1			T1	8		T19	2		T17	3
valid_sources[0x71]	6918	1			T19	2		T17	3		T22	9
valid_sources[0x72]	8251	1			T4	2		T19	2		T17	3
valid_sources[0x73]	7117	1			T17	3		T23	2		T20	67
valid_sources[0x74]	7495	1			T3	32		T19	1		T17	4
valid_sources[0x75]	7237	1			T17	3		T22	11		T20	45
valid_sources[0x76]	7499	1			T4	1		T17	4		T22	29
valid_sources[0x77]	7265	1			T3	21		T17	2		T22	33
valid_sources[0x78]	6979	1			T17	3		T22	10		T23	3
valid_sources[0x79]	6627	1			T17	3		T23	2		T20	28
valid_sources[0x7a]	6916	1			T17	4		T23	2		T20	48
valid_sources[0x7b]	7402	1			T19	1		T17	4		T23	2
valid_sources[0x7c]	7740	1			T3	27		T19	1		T17	3
valid_sources[0x7d]	7658	1			T17	3		T22	21		T23	1
valid_sources[0x7e]	7120	1			T17	3		T23	1		T20	51
valid_sources[0x7f]	6774	1			T3	23		T4	8		T19	1
valid_sources[0x80]	8027	1			T17	3		T22	18		T20	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27256

1

T1

5

T2

1

T3

7

values[0x0]

all_enables

biggest_size

204183

1

T1

12

T2

21

T3

54

values[0x1]

all_enables

biggest_size

27156

1

T1

3

T2

1

T3

7